Lines Matching +full:ddr +full:- +full:pmu
2 HiSilicon SoC uncore Performance Monitoring Unit (PMU)
13 two HHAs (0 - 1) and four DDRCs (0 - 3), respectively.
15 HiSilicon SoC uncore PMU driver
16 -------------------------------
18 Each device PMU has separate registers for event counting, control and
19 interrupt, and the PMU driver shall register perf PMU drivers like L3C,
27 Each L3C, HHA and DDRC is registered as a separate PMU with perf. The PMU
28 name will appear in event listing as hisi_sccl<sccl-id>_module<index-id>.
29 where "sccl-id" is the identifier of the SCCL and "index-id" is the index of
39 ID used to count the uncore PMU event. An "associated_cpus" sysfs attribute is
40 also provided to show the CPUs associated with this PMU. The "cpumask" indicates
47 hisi_sccl3_l3c0/rd_hit_cpipe/ [kernel PMU event]
48 ------------------------------------------
49 hisi_sccl3_l3c0/wr_hit_cpipe/ [kernel PMU event]
50 ------------------------------------------
51 hisi_sccl1_l3c0/rd_hit_cpipe/ [kernel PMU event]
52 ------------------------------------------
53 hisi_sccl1_l3c0/wr_hit_cpipe/ [kernel PMU event]
54 ------------------------------------------
56 $# perf stat -a -e hisi_sccl3_l3c0/rd_hit_cpipe/ sleep 5
57 $# perf stat -a -e hisi_sccl3_l3c0/config=0x02/ sleep 5
59 For HiSilicon uncore PMU v2 whose identifier is 0x30, the topology is the same
60 as PMU v1, but some new functions are added to the hardware.
62 1. L3C PMU supports filtering by core/thread within the cluster which can be
65 $# perf stat -a -e hisi_sccl3_l3c0/config=0x02,tt_core=0x3/ sleep 5
77 3'b111 represents atomic non-store operations, other values are reserved::
79 $# perf stat -a -e hisi_sccl3_l3c0/config=0x02,tt_req=0x4/ sleep 5
86 - 5'b00001: comes from L3C in this die;
87 - 5'b01000: comes from L3C in the cross-die;
88 - 5'b01001: comes from L3C which is in another socket;
89 - 5'b01110: comes from the local DDR;
90 - 5'b01111: comes from the cross-die DDR;
91 - 5'b10000: comes from cross-socket DDR;
94 cores. If datasrc_cfg is used in the multi-chips, the datasrc_skt shall be
97 $# perf stat -a -e hisi_sccl3_l3c0/config=0xb9,datasrc_cfg=0xE/,
103 SoC has a unique ID. Each ID is 11bits, include a 6-bit SCCL-ID and 5-bit
104 CCL/ICL-ID. For I/O die, the ICL-ID is followed by:
106 - 5'b00000: I/O_MGMT_ICL;
107 - 5'b00001: Network_ICL;
108 - 5'b00011: HAC_ICL;
109 - 5'b10000: PCIe_ICL;
111 5. uring_channel: UC PMU events 0x47~0x59 supports filtering by tx request
114 - 2'b11: count the events which sent to the uring_ext (MATA) channel;
115 - 2'b01: is the same as 2'b11;
116 - 2'b10: count the events which sent to the uring (non-MATA) channel;
117 - 2'b00: default value, count the events which sent to both uring and
120 6. ch: NoC PMU supports filtering the event counts of certain transaction
123 - 3'b010: Request channel
124 - 3'b100: Snoop channel
125 - 3'b110: Response channel
126 - 3'b111: Data channel
128 7. tt_en: NoC PMU supports counting only transactions that have tracetag set
131 For HiSilicon uncore PMU v3 whose identifier is 0x40, some uncore PMUs are
133 own dedicated PMU, and all such PMUs together cover the monitoring job of events
139 Z is the sub-id, indicating different PMUs for part of hardware device.
141 Usage of most PMUs with different sub-ids are identical. Specially, L3C PMU
143 of L3C PMU. L3C PMU driver uses that as hint of termination when delivering
146 - ext=0: Default, could be used with event names.
147 - ext=1 and ext=2: Must be used with event codes, event names are not supported.
151 $# perf stat -a -e hisi_sccl0_l3c1_0/rd_spipe/ sleep 5
155 $# perf stat -a -e hisi_sccl0_l3c1_0/event=0x1,ext=1/ sleep 5
157 As above, ``hisi_sccl0_l3c1_0`` locates PMU of Super CPU CLuster 0, L3 cache 1
166 tgtid_cmd & tgtid_msk. A set bit in srcid_msk/tgtid_msk means the PMU will not
171 the total counter values in the PMU counters.
177 the PMU devices in the SoC and its information if needed.