xref: /linux/Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml (revision a1ff5a7d78a036d6c2178ee5acd6ba4946243800)
1fd0ae78dSAnson Huang# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2fd0ae78dSAnson Huang%YAML 1.2
3fd0ae78dSAnson Huang---
4fd0ae78dSAnson Huang$id: http://devicetree.org/schemas/perf/fsl-imx-ddr.yaml#
5fd0ae78dSAnson Huang$schema: http://devicetree.org/meta-schemas/core.yaml#
6fd0ae78dSAnson Huang
7b1acb4e5SXu Yangtitle: Freescale(NXP) IMX8/9 DDR performance monitor
8fd0ae78dSAnson Huang
9fd0ae78dSAnson Huangmaintainers:
10fd0ae78dSAnson Huang  - Frank Li <frank.li@nxp.com>
11fd0ae78dSAnson Huang
12fd0ae78dSAnson Huangproperties:
13fd0ae78dSAnson Huang  compatible:
147f1f43f4SKrzysztof Kozlowski    oneOf:
157f1f43f4SKrzysztof Kozlowski      - enum:
16fd0ae78dSAnson Huang          - fsl,imx8-ddr-pmu
17fd0ae78dSAnson Huang          - fsl,imx8m-ddr-pmu
18d0c00977SJoakim Zhang          - fsl,imx8mq-ddr-pmu
19d0c00977SJoakim Zhang          - fsl,imx8mm-ddr-pmu
20d0c00977SJoakim Zhang          - fsl,imx8mn-ddr-pmu
21fd0ae78dSAnson Huang          - fsl,imx8mp-ddr-pmu
22b1acb4e5SXu Yang          - fsl,imx93-ddr-pmu
237f1f43f4SKrzysztof Kozlowski      - items:
247f1f43f4SKrzysztof Kozlowski          - enum:
257f1f43f4SKrzysztof Kozlowski              - fsl,imx8mm-ddr-pmu
267f1f43f4SKrzysztof Kozlowski              - fsl,imx8mn-ddr-pmu
277f1f43f4SKrzysztof Kozlowski              - fsl,imx8mq-ddr-pmu
287f1f43f4SKrzysztof Kozlowski              - fsl,imx8mp-ddr-pmu
297f1f43f4SKrzysztof Kozlowski          - const: fsl,imx8m-ddr-pmu
302fe44e7dSXu Yang      - items:
312fe44e7dSXu Yang          - const: fsl,imx8dxl-ddr-pmu
322fe44e7dSXu Yang          - const: fsl,imx8-ddr-pmu
33*f26f3748SXu Yang      - items:
34*f26f3748SXu Yang          - const: fsl,imx95-ddr-pmu
35*f26f3748SXu Yang          - const: fsl,imx93-ddr-pmu
36fd0ae78dSAnson Huang
37fd0ae78dSAnson Huang  reg:
38fd0ae78dSAnson Huang    maxItems: 1
39fd0ae78dSAnson Huang
40fd0ae78dSAnson Huang  interrupts:
41fd0ae78dSAnson Huang    maxItems: 1
42fd0ae78dSAnson Huang
43fd0ae78dSAnson Huangrequired:
44fd0ae78dSAnson Huang  - compatible
45fd0ae78dSAnson Huang  - reg
46fd0ae78dSAnson Huang  - interrupts
47fd0ae78dSAnson Huang
48fd0ae78dSAnson HuangadditionalProperties: false
49fd0ae78dSAnson Huang
50fd0ae78dSAnson Huangexamples:
51fd0ae78dSAnson Huang  - |
52fd0ae78dSAnson Huang    #include <dt-bindings/interrupt-controller/arm-gic.h>
53fd0ae78dSAnson Huang
54fd0ae78dSAnson Huang    ddr-pmu@5c020000 {
55fd0ae78dSAnson Huang        compatible = "fsl,imx8-ddr-pmu";
56fd0ae78dSAnson Huang        reg = <0x5c020000 0x10000>;
57fd0ae78dSAnson Huang        interrupt-parent = <&gic>;
58fd0ae78dSAnson Huang        interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
59fd0ae78dSAnson Huang    };
60