1ec8f24b7SThomas Gleixner# SPDX-License-Identifier: GPL-2.0-only 2fa8ad788SMark Rutland# 3fa8ad788SMark Rutland# Performance Monitor Drivers 4fa8ad788SMark Rutland# 5fa8ad788SMark Rutland 6fa8ad788SMark Rutlandmenu "Performance monitor support" 7bddb9b68SMark Rutland depends on PERF_EVENTS 8fa8ad788SMark Rutland 93de6be7aSRobin Murphyconfig ARM_CCI_PMU 108b0c93c2SRobin Murphy tristate "ARM CCI PMU driver" 118b0c93c2SRobin Murphy depends on (ARM && CPU_V7) || ARM64 123de6be7aSRobin Murphy select ARM_CCI 138b0c93c2SRobin Murphy help 148b0c93c2SRobin Murphy Support for PMU events monitoring on the ARM CCI (Cache Coherent 158b0c93c2SRobin Murphy Interconnect) family of products. 168b0c93c2SRobin Murphy 178b0c93c2SRobin Murphy If compiled as a module, it will be called arm-cci. 183de6be7aSRobin Murphy 193de6be7aSRobin Murphyconfig ARM_CCI400_PMU 208b0c93c2SRobin Murphy bool "support CCI-400" 218b0c93c2SRobin Murphy default y 228b0c93c2SRobin Murphy depends on ARM_CCI_PMU 233de6be7aSRobin Murphy select ARM_CCI400_COMMON 243de6be7aSRobin Murphy help 258b0c93c2SRobin Murphy CCI-400 provides 4 independent event counters counting events related 268b0c93c2SRobin Murphy to the connected slave/master interfaces, plus a cycle counter. 273de6be7aSRobin Murphy 283de6be7aSRobin Murphyconfig ARM_CCI5xx_PMU 298b0c93c2SRobin Murphy bool "support CCI-500/CCI-550" 308b0c93c2SRobin Murphy default y 318b0c93c2SRobin Murphy depends on ARM_CCI_PMU 323de6be7aSRobin Murphy help 338b0c93c2SRobin Murphy CCI-500/CCI-550 both provide 8 independent event counters, which can 348b0c93c2SRobin Murphy count events pertaining to the slave/master interfaces as well as the 358b0c93c2SRobin Murphy internal events to the CCI. 363de6be7aSRobin Murphy 371888d3ddSRobin Murphyconfig ARM_CCN 381888d3ddSRobin Murphy tristate "ARM CCN driver support" 39e656972bSJohn Garry depends on ARM || ARM64 || COMPILE_TEST 401888d3ddSRobin Murphy help 411888d3ddSRobin Murphy PMU (perf) driver supporting the ARM CCN (Cache Coherent Network) 421888d3ddSRobin Murphy interconnect. 431888d3ddSRobin Murphy 440ba64770SRobin Murphyconfig ARM_CMN 450ba64770SRobin Murphy tristate "Arm CMN-600 PMU support" 4682d8ea4bSRobin Murphy depends on ARM64 || COMPILE_TEST 470ba64770SRobin Murphy help 480ba64770SRobin Murphy Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh 490ba64770SRobin Murphy Network interconnect. 500ba64770SRobin Murphy 51*4d5a7680SRobin Murphyconfig ARM_NI 52*4d5a7680SRobin Murphy tristate "Arm NI-700 PMU support" 53*4d5a7680SRobin Murphy depends on ARM64 || COMPILE_TEST 54*4d5a7680SRobin Murphy help 55*4d5a7680SRobin Murphy Support for PMU events monitoring on the Arm NI-700 Network-on-Chip 56*4d5a7680SRobin Murphy interconnect and family. 57*4d5a7680SRobin Murphy 58fa8ad788SMark Rutlandconfig ARM_PMU 59bddb9b68SMark Rutland depends on ARM || ARM64 60fa8ad788SMark Rutland bool "ARM PMU framework" 61fa8ad788SMark Rutland default y 62fa8ad788SMark Rutland help 63fa8ad788SMark Rutland Say y if you want to use CPU performance monitors on ARM-based 64fa8ad788SMark Rutland systems. 65fa8ad788SMark Rutland 668d75537bSRob Herring (Arm)config ARM_V6_PMU 678d75537bSRob Herring (Arm) depends on ARM_PMU && (CPU_V6 || CPU_V6K) 688d75537bSRob Herring (Arm) def_bool y 698d75537bSRob Herring (Arm) 708d75537bSRob Herring (Arm)config ARM_V7_PMU 718d75537bSRob Herring (Arm) depends on ARM_PMU && CPU_V7 728d75537bSRob Herring (Arm) def_bool y 738d75537bSRob Herring (Arm) 748d75537bSRob Herring (Arm)config ARM_XSCALE_PMU 758d75537bSRob Herring (Arm) depends on ARM_PMU && CPU_XSCALE 768d75537bSRob Herring (Arm) def_bool y 778d75537bSRob Herring (Arm) 78f5bfa23fSAtish Patraconfig RISCV_PMU 79f5bfa23fSAtish Patra depends on RISCV 80f5bfa23fSAtish Patra bool "RISC-V PMU framework" 81f5bfa23fSAtish Patra default y 82f5bfa23fSAtish Patra help 83f5bfa23fSAtish Patra Say y if you want to use CPU performance monitors on RISCV-based 84f5bfa23fSAtish Patra systems. This provides the core PMU framework that abstracts common 85f5bfa23fSAtish Patra PMU functionalities in a core library so that different PMU drivers 86f5bfa23fSAtish Patra can reuse it. 87f5bfa23fSAtish Patra 889b3e150eSAtish Patraconfig RISCV_PMU_LEGACY 899b3e150eSAtish Patra depends on RISCV_PMU 909b3e150eSAtish Patra bool "RISC-V legacy PMU implementation" 919b3e150eSAtish Patra default y 929b3e150eSAtish Patra help 939b3e150eSAtish Patra Say y if you want to use the legacy CPU performance monitor 949b3e150eSAtish Patra implementation on RISC-V based systems. This only allows counting 959b3e150eSAtish Patra of cycle/instruction counter and doesn't support counter overflow, 969b3e150eSAtish Patra or programmable counters. It will be removed in future. 979b3e150eSAtish Patra 98e9991434SAtish Patraconfig RISCV_PMU_SBI 99e9991434SAtish Patra depends on RISCV_PMU && RISCV_SBI 100e9991434SAtish Patra bool "RISC-V PMU based on SBI PMU extension" 101e9991434SAtish Patra default y 102e9991434SAtish Patra help 103e9991434SAtish Patra Say y if you want to use the CPU performance monitor 104e9991434SAtish Patra using SBI PMU extension on RISC-V based systems. This option provides 105e9991434SAtish Patra full perf feature support i.e. counter overflow, privilege mode 106e9991434SAtish Patra filtering, counter configuration. 107e9991434SAtish Patra 108c2b24812SJi Sheng Teohconfig STARFIVE_STARLINK_PMU 1091d63d1d9SConor Dooley depends on ARCH_STARFIVE || COMPILE_TEST 1101d63d1d9SConor Dooley depends on 64BIT 111c2b24812SJi Sheng Teoh bool "StarFive StarLink PMU" 112c2b24812SJi Sheng Teoh help 113c2b24812SJi Sheng Teoh Provide support for StarLink Performance Monitor Unit. 114c2b24812SJi Sheng Teoh StarLink Performance Monitor Unit integrates one or more cores with 115c2b24812SJi Sheng Teoh an L3 memory system. The L3 cache events are added into perf event 116c2b24812SJi Sheng Teoh subsystem, allowing monitoring of various L3 cache perf events. 117c2b24812SJi Sheng Teoh 118bc969d6cSYu Chien Peter Linconfig ANDES_CUSTOM_PMU 119bc969d6cSYu Chien Peter Lin bool "Andes custom PMU support" 120bc969d6cSYu Chien Peter Lin depends on ARCH_RENESAS && RISCV_ALTERNATIVE && RISCV_PMU_SBI 121bc969d6cSYu Chien Peter Lin default y 122bc969d6cSYu Chien Peter Lin help 123bc969d6cSYu Chien Peter Lin The Andes cores implement the PMU overflow extension very 124bc969d6cSYu Chien Peter Lin similar to the standard Sscofpmf and Smcntrpmf extension. 125bc969d6cSYu Chien Peter Lin 126bc969d6cSYu Chien Peter Lin This will patch the overflow and pending CSRs and handle the 127bc969d6cSYu Chien Peter Lin non-standard behaviour via the regular SBI PMU driver and 128bc969d6cSYu Chien Peter Lin interface. 129bc969d6cSYu Chien Peter Lin 130bc969d6cSYu Chien Peter Lin If you don't know what to do here, say "Y". 131bc969d6cSYu Chien Peter Lin 13245736a72SMark Rutlandconfig ARM_PMU_ACPI 13345736a72SMark Rutland depends on ARM_PMU && ACPI 13445736a72SMark Rutland def_bool y 13545736a72SMark Rutland 1367d839b4bSNeil Leederconfig ARM_SMMU_V3_PMU 1377d839b4bSNeil Leeder tristate "ARM SMMUv3 Performance Monitors Extension" 1387c3f204eSVincent Whitchurch depends on ARM64 || (COMPILE_TEST && 64BIT) 13913e7accbSThomas Gleixner depends on GENERIC_MSI_IRQ 1407d839b4bSNeil Leeder help 1417d839b4bSNeil Leeder Provides support for the ARM SMMUv3 Performance Monitor Counter 1427d839b4bSNeil Leeder Groups (PMCG), which provide monitoring of transactions passing 1437d839b4bSNeil Leeder through the SMMU and allow the resulting information to be filtered 1447d839b4bSNeil Leeder based on the Stream ID of the corresponding master. 1457d839b4bSNeil Leeder 1467755cec6SMarc Zyngierconfig ARM_PMUV3 147009d6dc8SMarc Zyngier depends on HW_PERF_EVENTS && ((ARM && CPU_V7) || ARM64) 1487755cec6SMarc Zyngier bool "ARM PMUv3 support" if !ARM64 149009d6dc8SMarc Zyngier default ARM64 1507755cec6SMarc Zyngier help 1517755cec6SMarc Zyngier Say y if you want to use the ARM performance monitor unit (PMU) 1527755cec6SMarc Zyngier version 3. The PMUv3 is the CPU performance monitors on ARMv8 1537755cec6SMarc Zyngier (aarch32 and aarch64) systems that implement the PMUv3 1547755cec6SMarc Zyngier architecture. 1557755cec6SMarc Zyngier 1567520fa99SSuzuki K Pouloseconfig ARM_DSU_PMU 1577520fa99SSuzuki K Poulose tristate "ARM DynamIQ Shared Unit (DSU) PMU" 1587520fa99SSuzuki K Poulose depends on ARM64 1597520fa99SSuzuki K Poulose help 1607520fa99SSuzuki K Poulose Provides support for performance monitor unit in ARM DynamIQ Shared 1617520fa99SSuzuki K Poulose Unit (DSU). The DSU integrates one or more cores with an L3 memory 1627520fa99SSuzuki K Poulose system, control logic. The PMU allows counting various events related 1637520fa99SSuzuki K Poulose to DSU. 1647520fa99SSuzuki K Poulose 1659a66d36cSFrank Liconfig FSL_IMX8_DDR_PMU 1669a66d36cSFrank Li tristate "Freescale i.MX8 DDR perf monitor" 167e656972bSJohn Garry depends on ARCH_MXC || COMPILE_TEST 1689a66d36cSFrank Li help 1699a66d36cSFrank Li Provides support for the DDR performance monitor in i.MX8, which 1709a66d36cSFrank Li can give information about memory throughput and other related 1719a66d36cSFrank Li events. 1729a66d36cSFrank Li 17355691f99SXu Yangconfig FSL_IMX9_DDR_PMU 17455691f99SXu Yang tristate "Freescale i.MX9 DDR perf monitor" 17555691f99SXu Yang depends on ARCH_MXC 17655691f99SXu Yang help 17755691f99SXu Yang Provides support for the DDR performance monitor in i.MX9, which 17855691f99SXu Yang can give information about memory throughput and other related 17955691f99SXu Yang events. 18055691f99SXu Yang 18121bdbb71SNeil Leederconfig QCOM_L2_PMU 18221bdbb71SNeil Leeder bool "Qualcomm Technologies L2-cache PMU" 183bddb9b68SMark Rutland depends on ARCH_QCOM && ARM64 && ACPI 1846d0efeb1SIlia Lin select QCOM_KRYO_L2_ACCESSORS 18521bdbb71SNeil Leeder help 18621bdbb71SNeil Leeder Provides support for the L2 cache performance monitor unit (PMU) 18721bdbb71SNeil Leeder in Qualcomm Technologies processors. 18821bdbb71SNeil Leeder Adds the L2 cache PMU into the perf events subsystem for 18921bdbb71SNeil Leeder monitoring L2 cache events. 19021bdbb71SNeil Leeder 1913071f13dSAgustin Vega-Friasconfig QCOM_L3_PMU 1923071f13dSAgustin Vega-Frias bool "Qualcomm Technologies L3-cache PMU" 193bddb9b68SMark Rutland depends on ARCH_QCOM && ARM64 && ACPI 1943071f13dSAgustin Vega-Frias select QCOM_IRQ_COMBINER 1953071f13dSAgustin Vega-Frias help 1963071f13dSAgustin Vega-Frias Provides support for the L3 cache performance monitor unit (PMU) 1973071f13dSAgustin Vega-Frias in Qualcomm Technologies processors. 1983071f13dSAgustin Vega-Frias Adds the L3 cache PMU into the perf events subsystem for 1993071f13dSAgustin Vega-Frias monitoring L3 cache events. 2003071f13dSAgustin Vega-Frias 20169c32972SKulkarni, Ganapatraoconfig THUNDERX2_PMU 20269c32972SKulkarni, Ganapatrao tristate "Cavium ThunderX2 SoC PMU UNCORE" 203e656972bSJohn Garry depends on ARCH_THUNDER2 || COMPILE_TEST 204e656972bSJohn Garry depends on NUMA && ACPI 20569c32972SKulkarni, Ganapatrao default m 20669c32972SKulkarni, Ganapatrao help 20769c32972SKulkarni, Ganapatrao Provides support for ThunderX2 UNCORE events. 20869c32972SKulkarni, Ganapatrao The SoC has PMU support in its L3 cache controller (L3C) and 20969c32972SKulkarni, Ganapatrao in the DDR4 Memory Controller (DMC). 21069c32972SKulkarni, Ganapatrao 211832c927dSTai Nguyenconfig XGENE_PMU 212e656972bSJohn Garry depends on ARCH_XGENE || (COMPILE_TEST && 64BIT) 213832c927dSTai Nguyen bool "APM X-Gene SoC PMU" 214832c927dSTai Nguyen default n 215832c927dSTai Nguyen help 216832c927dSTai Nguyen Say y if you want to use APM X-Gene SoC performance monitors. 217832c927dSTai Nguyen 218d5d9696bSWill Deaconconfig ARM_SPE_PMU 219d5d9696bSWill Deacon tristate "Enable support for the ARMv8.2 Statistical Profiling Extension" 220b89205bdSJohn Garry depends on ARM64 221d5d9696bSWill Deacon help 222d5d9696bSWill Deacon Enable perf support for the ARMv8.2 Statistical Profiling 223d5d9696bSWill Deacon Extension, which provides periodic sampling of operations in 224d5d9696bSWill Deacon the CPU pipeline and reports this via the perf AUX interface. 225d5d9696bSWill Deacon 22653c218daSTuan Phanconfig ARM_DMC620_PMU 22753c218daSTuan Phan tristate "Enable PMU support for the ARM DMC-620 memory controller" 22853c218daSTuan Phan depends on (ARM64 && ACPI) || COMPILE_TEST 22953c218daSTuan Phan help 23053c218daSTuan Phan Support for PMU events monitoring on the ARM DMC-620 memory 23153c218daSTuan Phan controller. 23253c218daSTuan Phan 233036a7584SBhaskara Budiredlaconfig MARVELL_CN10K_TAD_PMU 234036a7584SBhaskara Budiredla tristate "Marvell CN10K LLC-TAD PMU" 235e564518bSGeert Uytterhoeven depends on ARCH_THUNDER || (COMPILE_TEST && 64BIT) 236036a7584SBhaskara Budiredla help 237036a7584SBhaskara Budiredla Provides support for Last-Level cache Tag-and-data Units (LLC-TAD) 238036a7584SBhaskara Budiredla performance monitors on CN10K family silicons. 239036a7584SBhaskara Budiredla 240a639027aSMarc Zyngierconfig APPLE_M1_CPU_PMU 241a639027aSMarc Zyngier bool "Apple M1 CPU PMU support" 242a639027aSMarc Zyngier depends on ARM_PMU && ARCH_APPLE 243a639027aSMarc Zyngier help 244a639027aSMarc Zyngier Provides support for the non-architectural CPU PMUs present on 245a639027aSMarc Zyngier the Apple M1 SoCs and derivatives. 246a639027aSMarc Zyngier 247cf7b6107SShuai Xueconfig ALIBABA_UNCORE_DRW_PMU 248cf7b6107SShuai Xue tristate "Alibaba T-Head Yitian 710 DDR Sub-system Driveway PMU driver" 249e08d07ddSGeert Uytterhoeven depends on (ARM64 && ACPI) || COMPILE_TEST 250cf7b6107SShuai Xue help 251cf7b6107SShuai Xue Support for Driveway PMU events monitoring on Yitian 710 DDR 252cf7b6107SShuai Xue Sub-system. 253cf7b6107SShuai Xue 25497807325SZhou Wangsource "drivers/perf/hisilicon/Kconfig" 25597807325SZhou Wang 25668fa55f0SBharat Bhushanconfig MARVELL_CN10K_DDR_PMU 25768fa55f0SBharat Bhushan tristate "Enable MARVELL CN10K DRAM Subsystem(DSS) PMU Support" 2581d8e926aSGeert Uytterhoeven depends on ARCH_THUNDER || (COMPILE_TEST && 64BIT) 25968fa55f0SBharat Bhushan help 26068fa55f0SBharat Bhushan Enable perf support for Marvell DDR Performance monitoring 26168fa55f0SBharat Bhushan event on CN10K platform. 26268fa55f0SBharat Bhushan 263af9597adSShuai Xueconfig DWC_PCIE_PMU 264af9597adSShuai Xue tristate "Synopsys DesignWare PCIe PMU" 265af9597adSShuai Xue depends on PCI 266af9597adSShuai Xue help 267af9597adSShuai Xue Enable perf support for Synopsys DesignWare PCIe PMU Performance 268af9597adSShuai Xue monitoring event on platform including the Alibaba Yitian 710. 269af9597adSShuai Xue 270e37dfd65SBesar Wicaksonosource "drivers/perf/arm_cspmu/Kconfig" 271e37dfd65SBesar Wicaksono 2722016e211SJiucheng Xusource "drivers/perf/amlogic/Kconfig" 2732016e211SJiucheng Xu 2745d7107c7SJonathan Cameronconfig CXL_PMU 2755d7107c7SJonathan Cameron tristate "CXL Performance Monitoring Unit" 2765d7107c7SJonathan Cameron depends on CXL_BUS 2775d7107c7SJonathan Cameron help 2785d7107c7SJonathan Cameron Support performance monitoring as defined in CXL rev 3.0 2795d7107c7SJonathan Cameron section 13.2: Performance Monitoring. CXL components may have 2805d7107c7SJonathan Cameron one or more CXL Performance Monitoring Units (CPMUs). 2815d7107c7SJonathan Cameron 2825d7107c7SJonathan Cameron Say 'y/m' to enable a driver that will attach to performance 2835d7107c7SJonathan Cameron monitoring units and provide standard perf based interfaces. 2845d7107c7SJonathan Cameron 2855d7107c7SJonathan Cameron If unsure say 'm'. 2865d7107c7SJonathan Cameron 287fa8ad788SMark Rutlandconfig MARVELL_PEM_PMU 288 tristate "MARVELL PEM PMU Support" 289 depends on ARCH_THUNDER || (COMPILE_TEST && 64BIT) 290 help 291 Enable support for PCIe Interface performance monitoring 292 on Marvell platform. 293 294endmenu 295