1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0 OR MIT 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Copyright 2015 Endless Mobile, Inc. 4*724ba675SRob Herring * Author: Carlo Caione <carlo@endlessm.com> 5*724ba675SRob Herring */ 6*724ba675SRob Herring 7*724ba675SRob Herring#include <dt-bindings/clock/meson8-ddr-clkc.h> 8*724ba675SRob Herring#include <dt-bindings/clock/meson8b-clkc.h> 9*724ba675SRob Herring#include <dt-bindings/gpio/meson8b-gpio.h> 10*724ba675SRob Herring#include <dt-bindings/power/meson8-power.h> 11*724ba675SRob Herring#include <dt-bindings/reset/amlogic,meson8b-reset.h> 12*724ba675SRob Herring#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h> 13*724ba675SRob Herring#include <dt-bindings/thermal/thermal.h> 14*724ba675SRob Herring#include "meson.dtsi" 15*724ba675SRob Herring 16*724ba675SRob Herring/ { 17*724ba675SRob Herring cpus { 18*724ba675SRob Herring #address-cells = <1>; 19*724ba675SRob Herring #size-cells = <0>; 20*724ba675SRob Herring 21*724ba675SRob Herring cpu0: cpu@200 { 22*724ba675SRob Herring device_type = "cpu"; 23*724ba675SRob Herring compatible = "arm,cortex-a5"; 24*724ba675SRob Herring next-level-cache = <&L2>; 25*724ba675SRob Herring reg = <0x200>; 26*724ba675SRob Herring enable-method = "amlogic,meson8b-smp"; 27*724ba675SRob Herring resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>; 28*724ba675SRob Herring operating-points-v2 = <&cpu_opp_table>; 29*724ba675SRob Herring clocks = <&clkc CLKID_CPUCLK>; 30*724ba675SRob Herring #cooling-cells = <2>; /* min followed by max */ 31*724ba675SRob Herring }; 32*724ba675SRob Herring 33*724ba675SRob Herring cpu1: cpu@201 { 34*724ba675SRob Herring device_type = "cpu"; 35*724ba675SRob Herring compatible = "arm,cortex-a5"; 36*724ba675SRob Herring next-level-cache = <&L2>; 37*724ba675SRob Herring reg = <0x201>; 38*724ba675SRob Herring enable-method = "amlogic,meson8b-smp"; 39*724ba675SRob Herring resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>; 40*724ba675SRob Herring operating-points-v2 = <&cpu_opp_table>; 41*724ba675SRob Herring clocks = <&clkc CLKID_CPUCLK>; 42*724ba675SRob Herring #cooling-cells = <2>; /* min followed by max */ 43*724ba675SRob Herring }; 44*724ba675SRob Herring 45*724ba675SRob Herring cpu2: cpu@202 { 46*724ba675SRob Herring device_type = "cpu"; 47*724ba675SRob Herring compatible = "arm,cortex-a5"; 48*724ba675SRob Herring next-level-cache = <&L2>; 49*724ba675SRob Herring reg = <0x202>; 50*724ba675SRob Herring enable-method = "amlogic,meson8b-smp"; 51*724ba675SRob Herring resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>; 52*724ba675SRob Herring operating-points-v2 = <&cpu_opp_table>; 53*724ba675SRob Herring clocks = <&clkc CLKID_CPUCLK>; 54*724ba675SRob Herring #cooling-cells = <2>; /* min followed by max */ 55*724ba675SRob Herring }; 56*724ba675SRob Herring 57*724ba675SRob Herring cpu3: cpu@203 { 58*724ba675SRob Herring device_type = "cpu"; 59*724ba675SRob Herring compatible = "arm,cortex-a5"; 60*724ba675SRob Herring next-level-cache = <&L2>; 61*724ba675SRob Herring reg = <0x203>; 62*724ba675SRob Herring enable-method = "amlogic,meson8b-smp"; 63*724ba675SRob Herring resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>; 64*724ba675SRob Herring operating-points-v2 = <&cpu_opp_table>; 65*724ba675SRob Herring clocks = <&clkc CLKID_CPUCLK>; 66*724ba675SRob Herring #cooling-cells = <2>; /* min followed by max */ 67*724ba675SRob Herring }; 68*724ba675SRob Herring }; 69*724ba675SRob Herring 70*724ba675SRob Herring cpu_opp_table: opp-table { 71*724ba675SRob Herring compatible = "operating-points-v2"; 72*724ba675SRob Herring opp-shared; 73*724ba675SRob Herring 74*724ba675SRob Herring opp-96000000 { 75*724ba675SRob Herring opp-hz = /bits/ 64 <96000000>; 76*724ba675SRob Herring opp-microvolt = <860000>; 77*724ba675SRob Herring }; 78*724ba675SRob Herring opp-192000000 { 79*724ba675SRob Herring opp-hz = /bits/ 64 <192000000>; 80*724ba675SRob Herring opp-microvolt = <860000>; 81*724ba675SRob Herring }; 82*724ba675SRob Herring opp-312000000 { 83*724ba675SRob Herring opp-hz = /bits/ 64 <312000000>; 84*724ba675SRob Herring opp-microvolt = <860000>; 85*724ba675SRob Herring }; 86*724ba675SRob Herring opp-408000000 { 87*724ba675SRob Herring opp-hz = /bits/ 64 <408000000>; 88*724ba675SRob Herring opp-microvolt = <860000>; 89*724ba675SRob Herring }; 90*724ba675SRob Herring opp-504000000 { 91*724ba675SRob Herring opp-hz = /bits/ 64 <504000000>; 92*724ba675SRob Herring opp-microvolt = <860000>; 93*724ba675SRob Herring }; 94*724ba675SRob Herring opp-600000000 { 95*724ba675SRob Herring opp-hz = /bits/ 64 <600000000>; 96*724ba675SRob Herring opp-microvolt = <860000>; 97*724ba675SRob Herring }; 98*724ba675SRob Herring opp-720000000 { 99*724ba675SRob Herring opp-hz = /bits/ 64 <720000000>; 100*724ba675SRob Herring opp-microvolt = <860000>; 101*724ba675SRob Herring }; 102*724ba675SRob Herring opp-816000000 { 103*724ba675SRob Herring opp-hz = /bits/ 64 <816000000>; 104*724ba675SRob Herring opp-microvolt = <900000>; 105*724ba675SRob Herring }; 106*724ba675SRob Herring opp-1008000000 { 107*724ba675SRob Herring opp-hz = /bits/ 64 <1008000000>; 108*724ba675SRob Herring opp-microvolt = <1140000>; 109*724ba675SRob Herring }; 110*724ba675SRob Herring opp-1200000000 { 111*724ba675SRob Herring opp-hz = /bits/ 64 <1200000000>; 112*724ba675SRob Herring opp-microvolt = <1140000>; 113*724ba675SRob Herring }; 114*724ba675SRob Herring opp-1320000000 { 115*724ba675SRob Herring opp-hz = /bits/ 64 <1320000000>; 116*724ba675SRob Herring opp-microvolt = <1140000>; 117*724ba675SRob Herring }; 118*724ba675SRob Herring opp-1488000000 { 119*724ba675SRob Herring opp-hz = /bits/ 64 <1488000000>; 120*724ba675SRob Herring opp-microvolt = <1140000>; 121*724ba675SRob Herring }; 122*724ba675SRob Herring opp-1536000000 { 123*724ba675SRob Herring opp-hz = /bits/ 64 <1536000000>; 124*724ba675SRob Herring opp-microvolt = <1140000>; 125*724ba675SRob Herring }; 126*724ba675SRob Herring }; 127*724ba675SRob Herring 128*724ba675SRob Herring gpu_opp_table: opp-table-gpu { 129*724ba675SRob Herring compatible = "operating-points-v2"; 130*724ba675SRob Herring 131*724ba675SRob Herring opp-255000000 { 132*724ba675SRob Herring opp-hz = /bits/ 64 <255000000>; 133*724ba675SRob Herring opp-microvolt = <1100000>; 134*724ba675SRob Herring }; 135*724ba675SRob Herring opp-364285714 { 136*724ba675SRob Herring opp-hz = /bits/ 64 <364285714>; 137*724ba675SRob Herring opp-microvolt = <1100000>; 138*724ba675SRob Herring }; 139*724ba675SRob Herring opp-425000000 { 140*724ba675SRob Herring opp-hz = /bits/ 64 <425000000>; 141*724ba675SRob Herring opp-microvolt = <1100000>; 142*724ba675SRob Herring }; 143*724ba675SRob Herring opp-510000000 { 144*724ba675SRob Herring opp-hz = /bits/ 64 <510000000>; 145*724ba675SRob Herring opp-microvolt = <1100000>; 146*724ba675SRob Herring }; 147*724ba675SRob Herring opp-637500000 { 148*724ba675SRob Herring opp-hz = /bits/ 64 <637500000>; 149*724ba675SRob Herring opp-microvolt = <1100000>; 150*724ba675SRob Herring turbo-mode; 151*724ba675SRob Herring }; 152*724ba675SRob Herring }; 153*724ba675SRob Herring 154*724ba675SRob Herring pmu { 155*724ba675SRob Herring compatible = "arm,cortex-a5-pmu"; 156*724ba675SRob Herring interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 157*724ba675SRob Herring <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 158*724ba675SRob Herring <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 159*724ba675SRob Herring <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 160*724ba675SRob Herring interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 161*724ba675SRob Herring }; 162*724ba675SRob Herring 163*724ba675SRob Herring reserved-memory { 164*724ba675SRob Herring #address-cells = <1>; 165*724ba675SRob Herring #size-cells = <1>; 166*724ba675SRob Herring ranges; 167*724ba675SRob Herring 168*724ba675SRob Herring /* 2 MiB reserved for Hardware ROM Firmware? */ 169*724ba675SRob Herring hwrom@0 { 170*724ba675SRob Herring reg = <0x0 0x200000>; 171*724ba675SRob Herring no-map; 172*724ba675SRob Herring }; 173*724ba675SRob Herring }; 174*724ba675SRob Herring 175*724ba675SRob Herring thermal-zones { 176*724ba675SRob Herring soc { 177*724ba675SRob Herring polling-delay-passive = <250>; /* milliseconds */ 178*724ba675SRob Herring polling-delay = <1000>; /* milliseconds */ 179*724ba675SRob Herring thermal-sensors = <&thermal_sensor>; 180*724ba675SRob Herring 181*724ba675SRob Herring cooling-maps { 182*724ba675SRob Herring map0 { 183*724ba675SRob Herring trip = <&soc_passive>; 184*724ba675SRob Herring cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 185*724ba675SRob Herring <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 186*724ba675SRob Herring <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 187*724ba675SRob Herring <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 188*724ba675SRob Herring <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 189*724ba675SRob Herring }; 190*724ba675SRob Herring 191*724ba675SRob Herring map1 { 192*724ba675SRob Herring trip = <&soc_hot>; 193*724ba675SRob Herring cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 194*724ba675SRob Herring <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 195*724ba675SRob Herring <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 196*724ba675SRob Herring <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 197*724ba675SRob Herring <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 198*724ba675SRob Herring }; 199*724ba675SRob Herring }; 200*724ba675SRob Herring 201*724ba675SRob Herring trips { 202*724ba675SRob Herring soc_passive: soc-passive { 203*724ba675SRob Herring temperature = <80000>; /* millicelsius */ 204*724ba675SRob Herring hysteresis = <2000>; /* millicelsius */ 205*724ba675SRob Herring type = "passive"; 206*724ba675SRob Herring }; 207*724ba675SRob Herring 208*724ba675SRob Herring soc_hot: soc-hot { 209*724ba675SRob Herring temperature = <90000>; /* millicelsius */ 210*724ba675SRob Herring hysteresis = <2000>; /* millicelsius */ 211*724ba675SRob Herring type = "hot"; 212*724ba675SRob Herring }; 213*724ba675SRob Herring 214*724ba675SRob Herring soc_critical: soc-critical { 215*724ba675SRob Herring temperature = <110000>; /* millicelsius */ 216*724ba675SRob Herring hysteresis = <2000>; /* millicelsius */ 217*724ba675SRob Herring type = "critical"; 218*724ba675SRob Herring }; 219*724ba675SRob Herring }; 220*724ba675SRob Herring }; 221*724ba675SRob Herring }; 222*724ba675SRob Herring 223*724ba675SRob Herring mmcbus: bus@c8000000 { 224*724ba675SRob Herring compatible = "simple-bus"; 225*724ba675SRob Herring reg = <0xc8000000 0x8000>; 226*724ba675SRob Herring #address-cells = <1>; 227*724ba675SRob Herring #size-cells = <1>; 228*724ba675SRob Herring ranges = <0x0 0xc8000000 0x8000>; 229*724ba675SRob Herring 230*724ba675SRob Herring ddr_clkc: clock-controller@400 { 231*724ba675SRob Herring compatible = "amlogic,meson8b-ddr-clkc"; 232*724ba675SRob Herring reg = <0x400 0x20>; 233*724ba675SRob Herring clocks = <&xtal>; 234*724ba675SRob Herring clock-names = "xtal"; 235*724ba675SRob Herring #clock-cells = <1>; 236*724ba675SRob Herring }; 237*724ba675SRob Herring 238*724ba675SRob Herring dmcbus: bus@6000 { 239*724ba675SRob Herring compatible = "simple-bus"; 240*724ba675SRob Herring reg = <0x6000 0x400>; 241*724ba675SRob Herring #address-cells = <1>; 242*724ba675SRob Herring #size-cells = <1>; 243*724ba675SRob Herring ranges = <0x0 0x6000 0x400>; 244*724ba675SRob Herring 245*724ba675SRob Herring canvas: video-lut@48 { 246*724ba675SRob Herring compatible = "amlogic,meson8b-canvas", 247*724ba675SRob Herring "amlogic,canvas"; 248*724ba675SRob Herring reg = <0x48 0x14>; 249*724ba675SRob Herring }; 250*724ba675SRob Herring }; 251*724ba675SRob Herring }; 252*724ba675SRob Herring 253*724ba675SRob Herring apb: bus@d0000000 { 254*724ba675SRob Herring compatible = "simple-bus"; 255*724ba675SRob Herring reg = <0xd0000000 0x200000>; 256*724ba675SRob Herring #address-cells = <1>; 257*724ba675SRob Herring #size-cells = <1>; 258*724ba675SRob Herring ranges = <0x0 0xd0000000 0x200000>; 259*724ba675SRob Herring 260*724ba675SRob Herring mali: gpu@c0000 { 261*724ba675SRob Herring compatible = "amlogic,meson8b-mali", "arm,mali-450"; 262*724ba675SRob Herring reg = <0xc0000 0x40000>; 263*724ba675SRob Herring interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 264*724ba675SRob Herring <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 265*724ba675SRob Herring <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 266*724ba675SRob Herring <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 267*724ba675SRob Herring <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 268*724ba675SRob Herring <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 269*724ba675SRob Herring <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 270*724ba675SRob Herring <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 271*724ba675SRob Herring interrupt-names = "gp", "gpmmu", "pp", "pmu", 272*724ba675SRob Herring "pp0", "ppmmu0", "pp1", "ppmmu1"; 273*724ba675SRob Herring resets = <&reset RESET_MALI>; 274*724ba675SRob Herring clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; 275*724ba675SRob Herring clock-names = "bus", "core"; 276*724ba675SRob Herring operating-points-v2 = <&gpu_opp_table>; 277*724ba675SRob Herring #cooling-cells = <2>; /* min followed by max */ 278*724ba675SRob Herring }; 279*724ba675SRob Herring }; 280*724ba675SRob Herring}; /* end of / */ 281*724ba675SRob Herring 282*724ba675SRob Herring&aiu { 283*724ba675SRob Herring compatible = "amlogic,aiu-meson8b", "amlogic,aiu"; 284*724ba675SRob Herring clocks = <&clkc CLKID_AIU_GLUE>, 285*724ba675SRob Herring <&clkc CLKID_I2S_OUT>, 286*724ba675SRob Herring <&clkc CLKID_AOCLK_GATE>, 287*724ba675SRob Herring <&clkc CLKID_CTS_AMCLK>, 288*724ba675SRob Herring <&clkc CLKID_MIXER_IFACE>, 289*724ba675SRob Herring <&clkc CLKID_IEC958>, 290*724ba675SRob Herring <&clkc CLKID_IEC958_GATE>, 291*724ba675SRob Herring <&clkc CLKID_CTS_MCLK_I958>, 292*724ba675SRob Herring <&clkc CLKID_CTS_I958>; 293*724ba675SRob Herring clock-names = "pclk", 294*724ba675SRob Herring "i2s_pclk", 295*724ba675SRob Herring "i2s_aoclk", 296*724ba675SRob Herring "i2s_mclk", 297*724ba675SRob Herring "i2s_mixer", 298*724ba675SRob Herring "spdif_pclk", 299*724ba675SRob Herring "spdif_aoclk", 300*724ba675SRob Herring "spdif_mclk", 301*724ba675SRob Herring "spdif_mclk_sel"; 302*724ba675SRob Herring resets = <&reset RESET_AIU>; 303*724ba675SRob Herring}; 304*724ba675SRob Herring 305*724ba675SRob Herring&aobus { 306*724ba675SRob Herring pmu: pmu@e0 { 307*724ba675SRob Herring compatible = "amlogic,meson8b-pmu", "syscon"; 308*724ba675SRob Herring reg = <0xe0 0x18>; 309*724ba675SRob Herring }; 310*724ba675SRob Herring 311*724ba675SRob Herring pinctrl_aobus: pinctrl@84 { 312*724ba675SRob Herring compatible = "amlogic,meson8b-aobus-pinctrl"; 313*724ba675SRob Herring reg = <0x84 0xc>; 314*724ba675SRob Herring #address-cells = <1>; 315*724ba675SRob Herring #size-cells = <1>; 316*724ba675SRob Herring ranges; 317*724ba675SRob Herring 318*724ba675SRob Herring gpio_ao: ao-bank@14 { 319*724ba675SRob Herring reg = <0x14 0x4>, 320*724ba675SRob Herring <0x2c 0x4>, 321*724ba675SRob Herring <0x24 0x8>; 322*724ba675SRob Herring reg-names = "mux", "pull", "gpio"; 323*724ba675SRob Herring gpio-controller; 324*724ba675SRob Herring #gpio-cells = <2>; 325*724ba675SRob Herring gpio-ranges = <&pinctrl_aobus 0 0 16>; 326*724ba675SRob Herring }; 327*724ba675SRob Herring 328*724ba675SRob Herring i2s_am_clk_pins: i2s-am-clk-out { 329*724ba675SRob Herring mux { 330*724ba675SRob Herring groups = "i2s_am_clk_out"; 331*724ba675SRob Herring function = "i2s"; 332*724ba675SRob Herring bias-disable; 333*724ba675SRob Herring }; 334*724ba675SRob Herring }; 335*724ba675SRob Herring 336*724ba675SRob Herring i2s_out_ao_clk_pins: i2s-ao-clk-out { 337*724ba675SRob Herring mux { 338*724ba675SRob Herring groups = "i2s_ao_clk_out"; 339*724ba675SRob Herring function = "i2s"; 340*724ba675SRob Herring bias-disable; 341*724ba675SRob Herring }; 342*724ba675SRob Herring }; 343*724ba675SRob Herring 344*724ba675SRob Herring i2s_out_lr_clk_pins: i2s-lr-clk-out { 345*724ba675SRob Herring mux { 346*724ba675SRob Herring groups = "i2s_lr_clk_out"; 347*724ba675SRob Herring function = "i2s"; 348*724ba675SRob Herring bias-disable; 349*724ba675SRob Herring }; 350*724ba675SRob Herring }; 351*724ba675SRob Herring 352*724ba675SRob Herring i2s_out_ch01_ao_pins: i2s-out-ch01 { 353*724ba675SRob Herring mux { 354*724ba675SRob Herring groups = "i2s_out_01"; 355*724ba675SRob Herring function = "i2s"; 356*724ba675SRob Herring bias-disable; 357*724ba675SRob Herring }; 358*724ba675SRob Herring }; 359*724ba675SRob Herring 360*724ba675SRob Herring spdif_out_1_pins: spdif-out-1 { 361*724ba675SRob Herring mux { 362*724ba675SRob Herring groups = "spdif_out_1"; 363*724ba675SRob Herring function = "spdif_1"; 364*724ba675SRob Herring bias-disable; 365*724ba675SRob Herring }; 366*724ba675SRob Herring }; 367*724ba675SRob Herring 368*724ba675SRob Herring uart_ao_a_pins: uart_ao_a { 369*724ba675SRob Herring mux { 370*724ba675SRob Herring groups = "uart_tx_ao_a", "uart_rx_ao_a"; 371*724ba675SRob Herring function = "uart_ao"; 372*724ba675SRob Herring bias-disable; 373*724ba675SRob Herring }; 374*724ba675SRob Herring }; 375*724ba675SRob Herring 376*724ba675SRob Herring ir_recv_pins: remote { 377*724ba675SRob Herring mux { 378*724ba675SRob Herring groups = "remote_input"; 379*724ba675SRob Herring function = "remote"; 380*724ba675SRob Herring bias-disable; 381*724ba675SRob Herring }; 382*724ba675SRob Herring }; 383*724ba675SRob Herring }; 384*724ba675SRob Herring}; 385*724ba675SRob Herring 386*724ba675SRob Herring&ao_arc_rproc { 387*724ba675SRob Herring compatible = "amlogic,meson8b-ao-arc", "amlogic,meson-mx-ao-arc"; 388*724ba675SRob Herring amlogic,secbus2 = <&secbus2>; 389*724ba675SRob Herring sram = <&ao_arc_sram>; 390*724ba675SRob Herring resets = <&reset RESET_MEDIA_CPU>; 391*724ba675SRob Herring clocks = <&clkc CLKID_AO_MEDIA_CPU>; 392*724ba675SRob Herring}; 393*724ba675SRob Herring 394*724ba675SRob Herring&cbus { 395*724ba675SRob Herring reset: reset-controller@4404 { 396*724ba675SRob Herring compatible = "amlogic,meson8b-reset"; 397*724ba675SRob Herring reg = <0x4404 0x9c>; 398*724ba675SRob Herring #reset-cells = <1>; 399*724ba675SRob Herring }; 400*724ba675SRob Herring 401*724ba675SRob Herring analog_top: analog-top@81a8 { 402*724ba675SRob Herring compatible = "amlogic,meson8b-analog-top", "syscon"; 403*724ba675SRob Herring reg = <0x81a8 0x14>; 404*724ba675SRob Herring }; 405*724ba675SRob Herring 406*724ba675SRob Herring pwm_ef: pwm@86c0 { 407*724ba675SRob Herring compatible = "amlogic,meson8b-pwm"; 408*724ba675SRob Herring reg = <0x86c0 0x10>; 409*724ba675SRob Herring #pwm-cells = <3>; 410*724ba675SRob Herring status = "disabled"; 411*724ba675SRob Herring }; 412*724ba675SRob Herring 413*724ba675SRob Herring clock-measure@8758 { 414*724ba675SRob Herring compatible = "amlogic,meson8b-clk-measure"; 415*724ba675SRob Herring reg = <0x8758 0x1c>; 416*724ba675SRob Herring }; 417*724ba675SRob Herring 418*724ba675SRob Herring pinctrl_cbus: pinctrl@9880 { 419*724ba675SRob Herring compatible = "amlogic,meson8b-cbus-pinctrl"; 420*724ba675SRob Herring reg = <0x9880 0x10>; 421*724ba675SRob Herring #address-cells = <1>; 422*724ba675SRob Herring #size-cells = <1>; 423*724ba675SRob Herring ranges; 424*724ba675SRob Herring 425*724ba675SRob Herring gpio: banks@80b0 { 426*724ba675SRob Herring reg = <0x80b0 0x28>, 427*724ba675SRob Herring <0x80e8 0x18>, 428*724ba675SRob Herring <0x8120 0x18>, 429*724ba675SRob Herring <0x8030 0x38>; 430*724ba675SRob Herring reg-names = "mux", "pull", "pull-enable", "gpio"; 431*724ba675SRob Herring gpio-controller; 432*724ba675SRob Herring #gpio-cells = <2>; 433*724ba675SRob Herring gpio-ranges = <&pinctrl_cbus 0 0 83>; 434*724ba675SRob Herring }; 435*724ba675SRob Herring 436*724ba675SRob Herring eth_rgmii_pins: eth-rgmii { 437*724ba675SRob Herring mux { 438*724ba675SRob Herring groups = "eth_tx_clk", 439*724ba675SRob Herring "eth_tx_en", 440*724ba675SRob Herring "eth_txd1_0", 441*724ba675SRob Herring "eth_txd0_0", 442*724ba675SRob Herring "eth_rx_clk", 443*724ba675SRob Herring "eth_rx_dv", 444*724ba675SRob Herring "eth_rxd1", 445*724ba675SRob Herring "eth_rxd0", 446*724ba675SRob Herring "eth_mdio_en", 447*724ba675SRob Herring "eth_mdc", 448*724ba675SRob Herring "eth_ref_clk", 449*724ba675SRob Herring "eth_txd2", 450*724ba675SRob Herring "eth_txd3", 451*724ba675SRob Herring "eth_rxd3", 452*724ba675SRob Herring "eth_rxd2"; 453*724ba675SRob Herring function = "ethernet"; 454*724ba675SRob Herring bias-disable; 455*724ba675SRob Herring }; 456*724ba675SRob Herring }; 457*724ba675SRob Herring 458*724ba675SRob Herring eth_rmii_pins: eth-rmii { 459*724ba675SRob Herring mux { 460*724ba675SRob Herring groups = "eth_tx_en", 461*724ba675SRob Herring "eth_txd1_0", 462*724ba675SRob Herring "eth_txd0_0", 463*724ba675SRob Herring "eth_rx_clk", 464*724ba675SRob Herring "eth_rx_dv", 465*724ba675SRob Herring "eth_rxd1", 466*724ba675SRob Herring "eth_rxd0", 467*724ba675SRob Herring "eth_mdio_en", 468*724ba675SRob Herring "eth_mdc"; 469*724ba675SRob Herring function = "ethernet"; 470*724ba675SRob Herring bias-disable; 471*724ba675SRob Herring }; 472*724ba675SRob Herring }; 473*724ba675SRob Herring 474*724ba675SRob Herring i2c_a_pins: i2c-a { 475*724ba675SRob Herring mux { 476*724ba675SRob Herring groups = "i2c_sda_a", "i2c_sck_a"; 477*724ba675SRob Herring function = "i2c_a"; 478*724ba675SRob Herring bias-disable; 479*724ba675SRob Herring }; 480*724ba675SRob Herring }; 481*724ba675SRob Herring 482*724ba675SRob Herring sd_b_pins: sd-b { 483*724ba675SRob Herring mux { 484*724ba675SRob Herring groups = "sd_d0_b", "sd_d1_b", "sd_d2_b", 485*724ba675SRob Herring "sd_d3_b", "sd_clk_b", "sd_cmd_b"; 486*724ba675SRob Herring function = "sd_b"; 487*724ba675SRob Herring bias-disable; 488*724ba675SRob Herring }; 489*724ba675SRob Herring }; 490*724ba675SRob Herring 491*724ba675SRob Herring sdxc_c_pins: sdxc-c { 492*724ba675SRob Herring mux { 493*724ba675SRob Herring groups = "sdxc_d0_c", "sdxc_d13_c", 494*724ba675SRob Herring "sdxc_d47_c", "sdxc_clk_c", 495*724ba675SRob Herring "sdxc_cmd_c"; 496*724ba675SRob Herring function = "sdxc_c"; 497*724ba675SRob Herring bias-pull-up; 498*724ba675SRob Herring }; 499*724ba675SRob Herring }; 500*724ba675SRob Herring 501*724ba675SRob Herring pwm_c1_pins: pwm-c1 { 502*724ba675SRob Herring mux { 503*724ba675SRob Herring groups = "pwm_c1"; 504*724ba675SRob Herring function = "pwm_c"; 505*724ba675SRob Herring bias-disable; 506*724ba675SRob Herring }; 507*724ba675SRob Herring }; 508*724ba675SRob Herring 509*724ba675SRob Herring pwm_d_pins: pwm-d { 510*724ba675SRob Herring mux { 511*724ba675SRob Herring groups = "pwm_d"; 512*724ba675SRob Herring function = "pwm_d"; 513*724ba675SRob Herring bias-disable; 514*724ba675SRob Herring }; 515*724ba675SRob Herring }; 516*724ba675SRob Herring 517*724ba675SRob Herring uart_b0_pins: uart-b0 { 518*724ba675SRob Herring mux { 519*724ba675SRob Herring groups = "uart_tx_b0", 520*724ba675SRob Herring "uart_rx_b0"; 521*724ba675SRob Herring function = "uart_b"; 522*724ba675SRob Herring bias-disable; 523*724ba675SRob Herring }; 524*724ba675SRob Herring }; 525*724ba675SRob Herring 526*724ba675SRob Herring uart_b0_cts_rts_pins: uart-b0-cts-rts { 527*724ba675SRob Herring mux { 528*724ba675SRob Herring groups = "uart_cts_b0", 529*724ba675SRob Herring "uart_rts_b0"; 530*724ba675SRob Herring function = "uart_b"; 531*724ba675SRob Herring bias-disable; 532*724ba675SRob Herring }; 533*724ba675SRob Herring }; 534*724ba675SRob Herring }; 535*724ba675SRob Herring}; 536*724ba675SRob Herring 537*724ba675SRob Herring&ahb_sram { 538*724ba675SRob Herring ao_arc_sram: ao-arc-sram@0 { 539*724ba675SRob Herring compatible = "amlogic,meson8b-ao-arc-sram"; 540*724ba675SRob Herring reg = <0x0 0x8000>; 541*724ba675SRob Herring pool; 542*724ba675SRob Herring }; 543*724ba675SRob Herring 544*724ba675SRob Herring smp-sram@1ff80 { 545*724ba675SRob Herring compatible = "amlogic,meson8b-smp-sram"; 546*724ba675SRob Herring reg = <0x1ff80 0x8>; 547*724ba675SRob Herring }; 548*724ba675SRob Herring}; 549*724ba675SRob Herring 550*724ba675SRob Herring 551*724ba675SRob Herring&efuse { 552*724ba675SRob Herring compatible = "amlogic,meson8b-efuse"; 553*724ba675SRob Herring clocks = <&clkc CLKID_EFUSE>; 554*724ba675SRob Herring clock-names = "core"; 555*724ba675SRob Herring 556*724ba675SRob Herring temperature_calib: calib@1f4 { 557*724ba675SRob Herring /* only the upper two bytes are relevant */ 558*724ba675SRob Herring reg = <0x1f4 0x4>; 559*724ba675SRob Herring }; 560*724ba675SRob Herring}; 561*724ba675SRob Herring 562*724ba675SRob Herringðmac { 563*724ba675SRob Herring compatible = "amlogic,meson8b-dwmac", "snps,dwmac-3.70a", "snps,dwmac"; 564*724ba675SRob Herring 565*724ba675SRob Herring reg = <0xc9410000 0x10000 566*724ba675SRob Herring 0xc1108140 0x4>; 567*724ba675SRob Herring 568*724ba675SRob Herring clocks = <&clkc CLKID_ETH>, 569*724ba675SRob Herring <&clkc CLKID_MPLL2>, 570*724ba675SRob Herring <&clkc CLKID_MPLL2>, 571*724ba675SRob Herring <&clkc CLKID_FCLK_DIV2>; 572*724ba675SRob Herring clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment"; 573*724ba675SRob Herring rx-fifo-depth = <4096>; 574*724ba675SRob Herring tx-fifo-depth = <2048>; 575*724ba675SRob Herring 576*724ba675SRob Herring resets = <&reset RESET_ETHERNET>; 577*724ba675SRob Herring reset-names = "stmmaceth"; 578*724ba675SRob Herring 579*724ba675SRob Herring power-domains = <&pwrc PWRC_MESON8_ETHERNET_MEM_ID>; 580*724ba675SRob Herring}; 581*724ba675SRob Herring 582*724ba675SRob Herring&gpio_intc { 583*724ba675SRob Herring compatible = "amlogic,meson8b-gpio-intc", 584*724ba675SRob Herring "amlogic,meson-gpio-intc"; 585*724ba675SRob Herring status = "okay"; 586*724ba675SRob Herring}; 587*724ba675SRob Herring 588*724ba675SRob Herring&hhi { 589*724ba675SRob Herring clkc: clock-controller { 590*724ba675SRob Herring compatible = "amlogic,meson8b-clkc"; 591*724ba675SRob Herring clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>; 592*724ba675SRob Herring clock-names = "xtal", "ddr_pll"; 593*724ba675SRob Herring #clock-cells = <1>; 594*724ba675SRob Herring #reset-cells = <1>; 595*724ba675SRob Herring }; 596*724ba675SRob Herring 597*724ba675SRob Herring pwrc: power-controller { 598*724ba675SRob Herring compatible = "amlogic,meson8b-pwrc"; 599*724ba675SRob Herring #power-domain-cells = <1>; 600*724ba675SRob Herring amlogic,ao-sysctrl = <&pmu>; 601*724ba675SRob Herring resets = <&reset RESET_DBLK>, 602*724ba675SRob Herring <&reset RESET_PIC_DC>, 603*724ba675SRob Herring <&reset RESET_HDMI_APB>, 604*724ba675SRob Herring <&reset RESET_HDMI_SYSTEM_RESET>, 605*724ba675SRob Herring <&reset RESET_VENCI>, 606*724ba675SRob Herring <&reset RESET_VENCP>, 607*724ba675SRob Herring <&reset RESET_VDAC_4>, 608*724ba675SRob Herring <&reset RESET_VENCL>, 609*724ba675SRob Herring <&reset RESET_VIU>, 610*724ba675SRob Herring <&reset RESET_VENC>, 611*724ba675SRob Herring <&reset RESET_RDMA>; 612*724ba675SRob Herring reset-names = "dblk", "pic_dc", "hdmi_apb", "hdmi_system", 613*724ba675SRob Herring "venci", "vencp", "vdac", "vencl", "viu", 614*724ba675SRob Herring "venc", "rdma"; 615*724ba675SRob Herring clocks = <&clkc CLKID_VPU>; 616*724ba675SRob Herring clock-names = "vpu"; 617*724ba675SRob Herring assigned-clocks = <&clkc CLKID_VPU>; 618*724ba675SRob Herring assigned-clock-rates = <182142857>; 619*724ba675SRob Herring }; 620*724ba675SRob Herring}; 621*724ba675SRob Herring 622*724ba675SRob Herring&hwrng { 623*724ba675SRob Herring clocks = <&clkc CLKID_RNG0>; 624*724ba675SRob Herring clock-names = "core"; 625*724ba675SRob Herring}; 626*724ba675SRob Herring 627*724ba675SRob Herring&i2c_AO { 628*724ba675SRob Herring clocks = <&clkc CLKID_CLK81>; 629*724ba675SRob Herring}; 630*724ba675SRob Herring 631*724ba675SRob Herring&i2c_A { 632*724ba675SRob Herring clocks = <&clkc CLKID_I2C>; 633*724ba675SRob Herring}; 634*724ba675SRob Herring 635*724ba675SRob Herring&i2c_B { 636*724ba675SRob Herring clocks = <&clkc CLKID_I2C>; 637*724ba675SRob Herring}; 638*724ba675SRob Herring 639*724ba675SRob Herring&L2 { 640*724ba675SRob Herring arm,data-latency = <3 3 3>; 641*724ba675SRob Herring arm,tag-latency = <2 2 2>; 642*724ba675SRob Herring arm,filter-ranges = <0x100000 0xc0000000>; 643*724ba675SRob Herring prefetch-data = <1>; 644*724ba675SRob Herring prefetch-instr = <1>; 645*724ba675SRob Herring arm,prefetch-offset = <7>; 646*724ba675SRob Herring arm,double-linefill = <1>; 647*724ba675SRob Herring arm,prefetch-drop = <1>; 648*724ba675SRob Herring arm,shared-override; 649*724ba675SRob Herring}; 650*724ba675SRob Herring 651*724ba675SRob Herring&periph { 652*724ba675SRob Herring scu@0 { 653*724ba675SRob Herring compatible = "arm,cortex-a5-scu"; 654*724ba675SRob Herring reg = <0x0 0x100>; 655*724ba675SRob Herring }; 656*724ba675SRob Herring 657*724ba675SRob Herring timer@200 { 658*724ba675SRob Herring compatible = "arm,cortex-a5-global-timer"; 659*724ba675SRob Herring reg = <0x200 0x20>; 660*724ba675SRob Herring interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; 661*724ba675SRob Herring clocks = <&clkc CLKID_PERIPH>; 662*724ba675SRob Herring 663*724ba675SRob Herring /* 664*724ba675SRob Herring * the arm_global_timer driver currently does not handle clock 665*724ba675SRob Herring * rate changes. Keep it disabled for now. 666*724ba675SRob Herring */ 667*724ba675SRob Herring status = "disabled"; 668*724ba675SRob Herring }; 669*724ba675SRob Herring 670*724ba675SRob Herring timer@600 { 671*724ba675SRob Herring compatible = "arm,cortex-a5-twd-timer"; 672*724ba675SRob Herring reg = <0x600 0x20>; 673*724ba675SRob Herring interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; 674*724ba675SRob Herring clocks = <&clkc CLKID_PERIPH>; 675*724ba675SRob Herring }; 676*724ba675SRob Herring}; 677*724ba675SRob Herring 678*724ba675SRob Herring&pwm_ab { 679*724ba675SRob Herring compatible = "amlogic,meson8b-pwm"; 680*724ba675SRob Herring}; 681*724ba675SRob Herring 682*724ba675SRob Herring&pwm_cd { 683*724ba675SRob Herring compatible = "amlogic,meson8b-pwm"; 684*724ba675SRob Herring}; 685*724ba675SRob Herring 686*724ba675SRob Herring&rtc { 687*724ba675SRob Herring compatible = "amlogic,meson8b-rtc"; 688*724ba675SRob Herring resets = <&reset RESET_RTC>; 689*724ba675SRob Herring}; 690*724ba675SRob Herring 691*724ba675SRob Herring&saradc { 692*724ba675SRob Herring compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc"; 693*724ba675SRob Herring clocks = <&xtal>, <&clkc CLKID_SAR_ADC>; 694*724ba675SRob Herring clock-names = "clkin", "core"; 695*724ba675SRob Herring amlogic,hhi-sysctrl = <&hhi>; 696*724ba675SRob Herring nvmem-cells = <&temperature_calib>; 697*724ba675SRob Herring nvmem-cell-names = "temperature_calib"; 698*724ba675SRob Herring}; 699*724ba675SRob Herring 700*724ba675SRob Herring&sdhc { 701*724ba675SRob Herring compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc"; 702*724ba675SRob Herring clocks = <&xtal>, 703*724ba675SRob Herring <&clkc CLKID_FCLK_DIV4>, 704*724ba675SRob Herring <&clkc CLKID_FCLK_DIV3>, 705*724ba675SRob Herring <&clkc CLKID_FCLK_DIV5>, 706*724ba675SRob Herring <&clkc CLKID_SDHC>; 707*724ba675SRob Herring clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk"; 708*724ba675SRob Herring}; 709*724ba675SRob Herring 710*724ba675SRob Herring&secbus { 711*724ba675SRob Herring secbus2: system-controller@4000 { 712*724ba675SRob Herring compatible = "amlogic,meson8b-secbus2", "syscon"; 713*724ba675SRob Herring reg = <0x4000 0x2000>; 714*724ba675SRob Herring }; 715*724ba675SRob Herring}; 716*724ba675SRob Herring 717*724ba675SRob Herring&sdio { 718*724ba675SRob Herring compatible = "amlogic,meson8b-sdio", "amlogic,meson-mx-sdio"; 719*724ba675SRob Herring clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>; 720*724ba675SRob Herring clock-names = "core", "clkin"; 721*724ba675SRob Herring}; 722*724ba675SRob Herring 723*724ba675SRob Herring&timer_abcde { 724*724ba675SRob Herring clocks = <&xtal>, <&clkc CLKID_CLK81>; 725*724ba675SRob Herring clock-names = "xtal", "pclk"; 726*724ba675SRob Herring}; 727*724ba675SRob Herring 728*724ba675SRob Herring&uart_AO { 729*724ba675SRob Herring compatible = "amlogic,meson8b-uart", "amlogic,meson-ao-uart"; 730*724ba675SRob Herring clocks = <&xtal>, <&clkc CLKID_CLK81>, <&clkc CLKID_CLK81>; 731*724ba675SRob Herring clock-names = "xtal", "pclk", "baud"; 732*724ba675SRob Herring}; 733*724ba675SRob Herring 734*724ba675SRob Herring&uart_A { 735*724ba675SRob Herring compatible = "amlogic,meson8b-uart"; 736*724ba675SRob Herring clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>; 737*724ba675SRob Herring clock-names = "xtal", "pclk", "baud"; 738*724ba675SRob Herring}; 739*724ba675SRob Herring 740*724ba675SRob Herring&uart_B { 741*724ba675SRob Herring compatible = "amlogic,meson8b-uart"; 742*724ba675SRob Herring clocks = <&xtal>, <&clkc CLKID_UART1>, <&clkc CLKID_CLK81>; 743*724ba675SRob Herring clock-names = "xtal", "pclk", "baud"; 744*724ba675SRob Herring}; 745*724ba675SRob Herring 746*724ba675SRob Herring&uart_C { 747*724ba675SRob Herring compatible = "amlogic,meson8b-uart"; 748*724ba675SRob Herring clocks = <&xtal>, <&clkc CLKID_UART2>, <&clkc CLKID_CLK81>; 749*724ba675SRob Herring clock-names = "xtal", "pclk", "baud"; 750*724ba675SRob Herring}; 751*724ba675SRob Herring 752*724ba675SRob Herring&usb0 { 753*724ba675SRob Herring compatible = "amlogic,meson8b-usb", "snps,dwc2"; 754*724ba675SRob Herring clocks = <&clkc CLKID_USB0_DDR_BRIDGE>; 755*724ba675SRob Herring clock-names = "otg"; 756*724ba675SRob Herring}; 757*724ba675SRob Herring 758*724ba675SRob Herring&usb1 { 759*724ba675SRob Herring compatible = "amlogic,meson8b-usb", "snps,dwc2"; 760*724ba675SRob Herring clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; 761*724ba675SRob Herring clock-names = "otg"; 762*724ba675SRob Herring}; 763*724ba675SRob Herring 764*724ba675SRob Herring&usb0_phy { 765*724ba675SRob Herring compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy"; 766*724ba675SRob Herring clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>; 767*724ba675SRob Herring clock-names = "usb_general", "usb"; 768*724ba675SRob Herring resets = <&reset RESET_USB_OTG>; 769*724ba675SRob Herring}; 770*724ba675SRob Herring 771*724ba675SRob Herring&usb1_phy { 772*724ba675SRob Herring compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy"; 773*724ba675SRob Herring clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>; 774*724ba675SRob Herring clock-names = "usb_general", "usb"; 775*724ba675SRob Herring resets = <&reset RESET_USB_OTG>; 776*724ba675SRob Herring}; 777*724ba675SRob Herring 778*724ba675SRob Herring&wdt { 779*724ba675SRob Herring compatible = "amlogic,meson8b-wdt"; 780*724ba675SRob Herring}; 781