clk_main (full) in projects: linux - OpenGrok search results

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Searched full:clk_main (Results 1 – 22 of 22) sorted by relevance

/linux/drivers/pwm/
H A D	pwm-mtk-disp.c	46 struct clk *clk_main; member 84 clk_disable_unprepare(mdp->clk_main); in mtk_disp_pwm_apply() 91 err = clk_prepare_enable(mdp->clk_main); in mtk_disp_pwm_apply() 93 dev_err(pwmchip_parent(chip), "Can't enable mdp->clk_main: %pe\n", in mtk_disp_pwm_apply() 102 clk_disable_unprepare(mdp->clk_main); in mtk_disp_pwm_apply() 117 rate = clk_get_rate(mdp->clk_main); in mtk_disp_pwm_apply() 123 clk_disable_unprepare(mdp->clk_main); in mtk_disp_pwm_apply() 181 err = clk_prepare_enable(mdp->clk_main); in mtk_disp_pwm_get_state() 183 dev_err(pwmchip_parent(chip), "Can't enable mdp->clk_main: %pe\n", ERR_PTR(err)); in mtk_disp_pwm_get_state() 190 clk_disable_unprepare(mdp->clk_main); in mtk_disp_pwm_get_state() [all …]
/linux/drivers/clk/renesas/
H A D	r8a779f0-cpg-mssr.c	`32 CLK_MAIN, enumerator 60 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL), 61 DEF_GEN4_PLL_F9_24(".pll1", 1, CLK_PLL1, CLK_MAIN), 62 DEF_GEN4_PLL_V9_24(".pll2", 2, CLK_PLL2, CLK_MAIN), 63 DEF_GEN4_PLL_V9_24(".pll3", 3, CLK_PLL3, CLK_MAIN), 64 DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN), 65 DEF_GEN4_PLL_V9_24(".pll6", 6, CLK_PLL6, CLK_MAIN),`
H A D	r8a7792-cpg-mssr.c	`30 CLK_MAIN, enumerator 45 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL), 46 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN), 47 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN), 48 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),`
H A D	r8a77470-cpg-mssr.c	`27 CLK_MAIN, enumerator 43 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL), 44 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN), 45 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN), 46 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),`
H A D	r8a774e1-cpg-mssr.c	`31 CLK_MAIN, enumerator 57 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), 58 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN), 59 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), 60 DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN), 61 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN), 62 DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),`
H A D	r8a774a1-cpg-mssr.c	`31 CLK_MAIN, enumerator 57 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), 58 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN), 59 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), 60 DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN), 61 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN), 62 DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),`
H A D	r8a77995-cpg-mssr.c	`31 CLK_MAIN, enumerator 58 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), 59 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), 60 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN), 62 DEF_FIXED(".pll0", CLK_PLL0, CLK_MAIN, 4, 250),`
H A D	r8a7745-cpg-mssr.c	`27 CLK_MAIN, enumerator 43 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL), 44 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN), 45 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN), 46 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),`
H A D	r8a77980-cpg-mssr.c	`33 CLK_MAIN, enumerator 57 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), 58 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), 59 DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN), 60 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),`
H A D	r8a7794-cpg-mssr.c	`31 CLK_MAIN, enumerator 47 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL), 48 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN), 49 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN), 50 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),`
H A D	r8a7795-cpg-mssr.c	`33 CLK_MAIN, enumerator 60 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), 61 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN), 62 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), 63 DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN), 64 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN), 65 DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),`
H A D	r8a7796-cpg-mssr.c	`35 CLK_MAIN, enumerator 62 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), 63 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN), 64 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), 65 DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN), 66 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN), 67 DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),`
H A D	r8a774b1-cpg-mssr.c	`31 CLK_MAIN, enumerator 56 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), 57 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN), 58 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), 59 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN), 60 DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),`
H A D	r8a7791-cpg-mssr.c	`32 CLK_MAIN, enumerator 48 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL), 49 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN), 50 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN), 51 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),`
H A D	r8a7790-cpg-mssr.c	`31 CLK_MAIN, enumerator 47 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL), 48 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN), 49 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN), 50 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),`
H A D	r8a7742-cpg-mssr.c	`27 CLK_MAIN, enumerator 43 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL), 44 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN), 45 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN), 46 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),`
H A D	r8a774c0-cpg-mssr.c	`31 CLK_MAIN, enumerator 60 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), 61 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), 62 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN), 64 DEF_FIXED(".pll0", CLK_PLL0, CLK_MAIN, 1, 100),`
H A D	r8a7743-cpg-mssr.c	`28 CLK_MAIN, enumerator 44 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL), 45 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN), 46 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN), 47 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),`
H A D	r8a77965-cpg-mssr.c	`33 CLK_MAIN, enumerator 59 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), 60 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN), 61 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), 62 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN), 63 DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),`
H A D	r8a77990-cpg-mssr.c	`31 CLK_MAIN, enumerator 60 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), 61 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), 62 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN), 64 DEF_FIXED(".pll0", CLK_PLL0, CLK_MAIN, 1, 100),`
/linux/Documentation/devicetree/bindings/dma/xilinx/
H A D	xlnx,zynqmp-dma-1.0.yaml	`46 - const: clk_main 85 clock-names = "clk_main", "clk_apb";`
/linux/drivers/dma/xilinx/
H A D	zynqmp_dma.c	250 * @clk_main: Pointer to main clock 257 struct clk *clk_main; member 1023 clk_disable_unprepare(zdev->clk_main); in zynqmp_dma_runtime_suspend() 1041 err = clk_prepare_enable(zdev->clk_main); in zynqmp_dma_runtime_resume() 1050 clk_disable_unprepare(zdev->clk_main); in zynqmp_dma_runtime_resume() 1100 zdev->clk_main = devm_clk_get(&pdev->dev, "clk_main"); in zynqmp_dma_probe() 1101 if (IS_ERR(zdev->clk_main)) in zynqmp_dma_probe() 1102 return dev_err_probe(&pdev->dev, PTR_ERR(zdev->clk_main), in zynqmp_dma_probe()