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/freebsd/sys/contrib/device-tree/src/arm64/amazon/
H A D	alpine-v3.dtsi	`1 // SPDX-License-Identifier: GPL-2.0 6 /dts-v1/; 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 12 compatible = "amazon,al-alpine-v3"; 14 interrupt-paren [all...]`
/freebsd/sys/contrib/device-tree/src/arm64/amd/
H A D	amd-seattle-cpus.dtsi	`1 // SPDX-License-Identifier: GPL-2.0 5 #address-cells = <0x1>; 6 #size-cells = <0x0>; 8 cpu-map { 45 compatible = "arm,cortex-a57"; 47 enable-method = "psci"; 49 i-cache-size = <0xC000>; 50 i-cache-line-size = <64>; 51 i-cache-sets = <256>; 52 d-cache-size = <0x8000>; [all …]`
/freebsd/sys/contrib/device-tree/Bindings/powerpc/fsl/
H A D	l2cache.txt	`1 Freescale L2 Cache Controller 3 L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms. 4 The cache bindings explained below are Devicetree Specification compliant 8 - compatible : Should include one of the following: 9 "fsl,b4420-l2-cache-controller" 10 "fsl,b4860-l2-cache-controller" 11 "fsl,bsc9131-l2-cache-controller" 12 "fsl,bsc9132-l2-cache-controller" 13 "fsl,c293-l2-cache-controller" 14 "fsl,mpc8536-l2-cache-controller" [all …]`
/freebsd/sys/contrib/device-tree/Bindings/cache/
H A D	freescale-l2cache.txt	`1 Freescale L2 Cache Controller 3 L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms. 4 The cache bindings explained below are Devicetree Specification compliant 8 - compatible : Should include one of the following: 9 "fsl,b4420-l2-cache-controller" 10 "fsl,b4860-l2-cache-controller" 11 "fsl,bsc9131-l2-cache-controller" 12 "fsl,bsc9132-l2-cache-controller" 13 "fsl,c293-l2-cache-controller" 14 "fsl,mpc8536-l2-cache-controller" [all …]`
H A D	socionext,uniphier-system-cache.yaml	1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/cache/socionext,uniphier-system-cache.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: UniPhier outer cache controller 10 UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache 11 controller system. All of them have a level 2 cache controller, and some 12 have a level 3 cache controller as well. 15 - Masahiro Yamada <yamada.masahiro@socionext.com> 19 const: socionext,uniphier-system-cache [all …]
/freebsd/lib/libpmc/pmu-events/arch/s390/cf_z13/
H A D	extended.json	5 "BriefDescription": "L1D Read-only Exclusive Writes", 6 …-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated… 12 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi… 18 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB… 23 "BriefDescription": "DTLB1 One-Megabyte Page Writes", 24 …": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a on… 29 "BriefDescription": "DTLB1 Two-Gigabyte Page Writes", 30 …": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a tw… 36 …A directory write to the Level-1 Data cache directory where the returned cache line was sourced fr… 42 …"PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation … [all …]
/freebsd/lib/libpmc/pmu-events/arch/s390/cf_z14/
H A D	extended.json	5 "BriefDescription": "L1D Read-only Exclusive Writes", 6 …-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated… 12 … written into The Translation Lookaside Buffer 2 (TLB2) and the request was made by the data cache" 18 …ss for a request made by the data cache. Incremented by one for every TLB2 miss in progress for th… 23 "BriefDescription": "DTLB2 One-Megabyte Page Writes", 24 … into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page… 29 "BriefDescription": "DTLB2 Two-Gigabyte Page Writes", 30 …"PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB" 36 …A directory write to the Level-1 Data cache directory where the returned cache line was sourced fr… 42 …n into the Translation Lookaside Buffer 2 (TLB2) and the request was made by the instruction cache" [all …]
/freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a65/
H A D	cache.json	111 …"Level 1 data cache refill started due to prefetch. Counts any linefills from the prefetcher which… 114 …"Level 1 data cache refill started due to prefetch. Counts any linefills from the prefetcher which… 117 …cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: This event … 120 …cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: This event … 123 …cache refill due to prefetch. This event counts any linefills from the hardware prefetcher which c… 126 …cache refill due to prefetch. This event counts any linefills from the hardware prefetcher which c… 141 … 2 cache write streaming mode. This event counts for each cycle where the core is in write-streami… 144 … 2 cache write streaming mode. This event counts for each cycle where the core is in write-streami… 147 … 3 cache write streaming mode. This event counts for each cycle where the core is in write-streami… 150 … 3 cache write streaming mode. This event counts for each cycle where the core is in write-streami… [all …]
/freebsd/sys/contrib/device-tree/Bindings/arm/socionext/
H A D	socionext,uniphier-system-cache.yaml	1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/arm/socionext/socionext,uniphier-system-cache.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: UniPhier outer cache controller 10 UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache 11 controller system. All of them have a level 2 cache controller, and some 12 have a level 3 cache controller as well. 15 - Masahiro Yamada <yamada.masahiro@socionext.com> 19 const: socionext,uniphier-system-cache [all …]
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A D	k3-am654.dtsi	`1 // SPDX-License-Identifier: GPL-2.0 5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ 8 #include "k3-am65.dtsi" 12 #address-cells = <1>; 13 #size-cells = <0>; 14 cpu-map { 37 compatible = "arm,cortex-a53"; 40 enable-method = "psci"; 41 i-cache-size = <0x8000>; 42 i-cache-line-size = <64>; [all …]`
H A D	k3-j784s4.dtsi	`1 // SPDX-License-Identifier: GPL-2.0 7 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ 11 #include <dt-bindings/interrupt-controller/irq.h> 12 #include <dt-bindings/interrupt-controller/arm-gic.h> 13 #include <dt-binding [all...]`
H A D	k3-am62a7.dtsi	`1 // SPDX-License-Identifier: GPL-2.0 7 * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ 10 /dts-v1/; 12 #include "k3-am62a.dtsi" 16 #address-cells = <1>; 17 #size-cells = <0>; 19 cpu-map { 40 compatible = "arm,cortex-a53"; 43 enable-method = "psci"; 44 i-cache-size = <0x8000>; [all …]`
/freebsd/lib/libpmc/pmu-events/arch/s390/cf_zec12/
H A D	extended.json	6 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB… 12 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle… 18 …rectory write to the Level-1 Data cache directory where the returned cache line was sourced from t… 24 …tory write to the Level-1 Instruction cache directory where the returned cache line was sourced fr… 30 …A directory write to the Level-1 Data cache directory where the returned cache line was sourced fr… 36 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi… 42 …ite to the Level-1 Data cache where the installed cache line was sourced from memory that is attac… 48 …the Level-1 Instruction cache where the installed cache line was sourced from memory that is attac… 53 "BriefDescription": "L1D Read-only Exclusive Writes", 54 …-1 D-Cache where the line was originally in a Read-Only state in the cache but has been updated to… [all …]
/freebsd/sys/contrib/device-tree/src/arm64/marvell/
H A D	armada-ap806-quad.dtsi	`1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8 #include "armada-ap806.dtsi" 12 compatible = "marvell,armada-ap806-quad", "marvell,armada-ap806"; 15 #address-cells = <1>; 16 #size-cells = <0>; 20 compatible = "arm,cortex-a72"; 22 enable-method = "psci"; 23 #cooling-cells = <2>; 25 i-cache-size = <0xc000>; 26 i-cache-line-size = <64>; [all …]`
H A D	armada-ap807-quad.dtsi	`1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8 #include "armada-ap807.dtsi" 12 compatible = "marvell,armada-ap807-quad", "marvell,armada-ap807"; 15 #address-cells = <1>; 16 #size-cells = <0>; 20 compatible = "arm,cortex-a72"; 22 enable-method = "psci"; 23 #cooling-cells = <2>; 25 i-cache-size = <0xc000>; 26 i-cache-line-size = <64>; [all …]`
/freebsd/contrib/libarchive/libarchive/
H A D	archive_read_disk_set_standard_lookup.c	1 /- 2 Copyright (c) 2003-2007 Tim Kientzle 53 archive_set_error(a, -1, "Standard lookups not available on Windows"); in archive_read_disk_set_standard_lookup() 71 } cache[name_cache_size]; 81 * Installs functions that use getpwuid()/getgrgid()---along with 82 * a simple cache to accelerate such lookups-- 72 } cache[name_cache_size]; global() member 124 struct name_cache cache = (struct name_cache )data; cleanup() local 142 lookup_name(struct name_cache * cache,const char * (* lookup_fn)(struct name_cache ,id_t),id_t id) lookup_name() argument 187 lookup_uname_helper(struct name_cache cache,id_t id) lookup_uname_helper() argument 232 lookup_uname_helper(struct name_cache * cache,id_t id) lookup_uname_helper() argument 256 lookup_gname_helper(struct name_cache * cache,id_t id) lookup_gname_helper() argument 299 lookup_gname_helper(struct name_cache * cache,id_t id) lookup_gname_helper() argument [all...]
/freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a55/
H A D	cache.json	105 …cache refill due to prefetch. This event counts any linefills from the hardware prefetcher which c… 108 …cache refill due to prefetch. This event counts any linefills from the hardware prefetcher which c… 111 …cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: This event … 114 …cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: This event … 117 …Level 1 data cache refill due to prefetch. This event counts any linefills from the prefetcher whi… 120 …Level 1 data cache refill due to prefetch. This event counts any linefills from the prefetcher whi… 123 … 2 cache write streaming mode. This event counts for each cycle where the core is in write-streami… 126 … 2 cache write streaming mode. This event counts for each cycle where the core is in write-streami… 129 …"PublicDescription": "Level 1 data cache entering write streaming mode.This event counts for each … 132 …"BriefDescription": "Level 1 data cache entering write streaming mode.This event counts for each e… [all …]
/freebsd/lib/libpmc/pmu-events/arch/s390/cf_z196/
H A D	extended.json	6 …": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced f… 12 …": "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced f… 18 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB… 24 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle… 30 "PublicDescription": "Incremented by one for every store sent to Level-2 cache" 35 "BriefDescription": "L1D Off-Book L3 Sourced Writes", 36 …A directory write to the Level-1 D-Cache directory where the returned cache line was sourced from … 41 "BriefDescription": "L1D On-Book L4 Sourced Writes", 42 …A directory write to the Level-1 D-Cache directory where the returned cache line was sourced from … 47 "BriefDescription": "L1I On-Book L4 Sourced Writes", [all …]
/freebsd/sys/powerpc/mpc85xx/
H A D	mpc85xx_cache.c	`1 /- 2 SPDX-License-Identifier: BSD-2-Clause 41 * - mbar 42 * - isync 43 * - write 44 * - read 45 * - mbar 55 {"fsl,8540-l2-cache-controller", 1}, 56 {"fsl,8541-l2-cache-controller", 1}, 57 {"fsl,8544-l2-cache-controller", 1}, [all …]`
/freebsd/sys/contrib/device-tree/src/arm64/arm/
H A D	fvp-base-revc.dts	`1 // SPDX-License-Identifier: GPL-2.0 5 * Architecture Envelope Model (AEM) ARMv8-A 11 /dts-v1/; 13 #include <dt-bindings/interrupt-controller/arm-gic.h> 17 #include "rtsm_ve-motherboard.dtsi" 18 #include "rtsm_ve-motherboard-rs2.dtsi" 22 compatible = "arm,fvp-base-revc", "arm,vexpress"; 23 interrupt-parent = <&gic>; 24 #address-cells = <2>; 25 #size-cells = <2>; [all …]`
H A D	juno-r2.dts	`9 /dts-v1/; 11 #include <dt-bindings/interrupt-controller/arm-gic.h> 12 #include <dt-bindings/arm/coresight-cti-dt.h> 13 #include "juno-base.dtsi" 14 #include "juno-cs-r1r2.dtsi" 18 compatible = "arm,juno-r2", "arm,juno", "arm,vexpress"; 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 28 stdout-path = "serial0:115200n8"; [all …]`
H A D	juno.dts	`4 * Copyright (c) 2013-2014 ARM Ltd. 9 /dts-v1/; 11 #include <dt-bindings/interrupt-controller/arm-gic.h> 12 #include <dt-bindings/arm/coresight-cti-dt.h> 13 #include "juno-base.dtsi" 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 27 stdout-path = "serial0:115200n8"; 31 compatible = "arm,psci-0.2"; [all …]`
/freebsd/lib/libpmc/pmu-events/arch/s390/cf_z10/
H A D	extended.json	6 …A directory write to the Level-1 I-Cache directory where the returned cache line was sourced from … 12 …A directory write to the Level-1 D-Cache directory where the installed cache line was sourced from… 18 …-1 I-Cache directory where the installed cache line was sourced from the Level-3 cache that is on … 24 …vel-1 D-Cache directory where the installtion cache line was source from the Level-3 cache that is… 30 …-1 I-Cache directory where the installed cache line was sourced from a Level-3 cache that is not o… 36 …el-1 D-Cache directory where the installed cache line was sourced from a Level-3 cache that is not… 42 … to the Level-1 D-Cache directory where the installed cache line was sourced from memory that is a… 48 …e to the Level-1 I-Cache where the installed cache line was sourced from memory that is attached t… 53 "BriefDescription": "L1D Read-only Exclusive Writes", 54 …-1 D-Cache where the line was originally in a Read-Only state in the cache but has been updated to… [all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A D	imx8qm.dtsi	`1 // SPDX-License-Identifier: GPL-2.0+ 3 * Copyright 2018-2019 NXP 7 #include <dt-bindings/clock/imx8-lpcg.h> 8 #include <dt-bindings/firmware/imx/rsrc.h> 9 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/interrupt-controlle [all...]`
/freebsd/sys/contrib/device-tree/Bindings/cpufreq/
H A D	cpufreq-qcom-hw.yaml	`1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/cpufreq/cpufreq-qco [all...]`

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