1*01950c46SEmmanuel Vadot// SPDX-License-Identifier: GPL-2.0-only OR MIT 2aa1a8ff2SEmmanuel Vadot/* 3aa1a8ff2SEmmanuel Vadot * Device Tree file for the AM62P5 SoC family (quad core) 4*01950c46SEmmanuel Vadot * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ 5aa1a8ff2SEmmanuel Vadot * 6aa1a8ff2SEmmanuel Vadot * TRM: https://www.ti.com/lit/pdf/spruj83 7aa1a8ff2SEmmanuel Vadot */ 8aa1a8ff2SEmmanuel Vadot 9aa1a8ff2SEmmanuel Vadot/dts-v1/; 10aa1a8ff2SEmmanuel Vadot 11aa1a8ff2SEmmanuel Vadot#include "k3-am62p.dtsi" 12aa1a8ff2SEmmanuel Vadot 13aa1a8ff2SEmmanuel Vadot/ { 14aa1a8ff2SEmmanuel Vadot cpus { 15aa1a8ff2SEmmanuel Vadot #address-cells = <1>; 16aa1a8ff2SEmmanuel Vadot #size-cells = <0>; 17aa1a8ff2SEmmanuel Vadot 18aa1a8ff2SEmmanuel Vadot cpu-map { 19aa1a8ff2SEmmanuel Vadot cluster0: cluster0 { 20aa1a8ff2SEmmanuel Vadot core0 { 21aa1a8ff2SEmmanuel Vadot cpu = <&cpu0>; 22aa1a8ff2SEmmanuel Vadot }; 23aa1a8ff2SEmmanuel Vadot 24aa1a8ff2SEmmanuel Vadot core1 { 25aa1a8ff2SEmmanuel Vadot cpu = <&cpu1>; 26aa1a8ff2SEmmanuel Vadot }; 27aa1a8ff2SEmmanuel Vadot 28aa1a8ff2SEmmanuel Vadot core2 { 29aa1a8ff2SEmmanuel Vadot cpu = <&cpu2>; 30aa1a8ff2SEmmanuel Vadot }; 31aa1a8ff2SEmmanuel Vadot 32aa1a8ff2SEmmanuel Vadot core3 { 33aa1a8ff2SEmmanuel Vadot cpu = <&cpu3>; 34aa1a8ff2SEmmanuel Vadot }; 35aa1a8ff2SEmmanuel Vadot }; 36aa1a8ff2SEmmanuel Vadot }; 37aa1a8ff2SEmmanuel Vadot 38aa1a8ff2SEmmanuel Vadot cpu0: cpu@0 { 39aa1a8ff2SEmmanuel Vadot compatible = "arm,cortex-a53"; 40aa1a8ff2SEmmanuel Vadot reg = <0x000>; 41aa1a8ff2SEmmanuel Vadot device_type = "cpu"; 42aa1a8ff2SEmmanuel Vadot enable-method = "psci"; 43aa1a8ff2SEmmanuel Vadot i-cache-size = <0x8000>; 44aa1a8ff2SEmmanuel Vadot i-cache-line-size = <64>; 45aa1a8ff2SEmmanuel Vadot i-cache-sets = <256>; 46aa1a8ff2SEmmanuel Vadot d-cache-size = <0x8000>; 47aa1a8ff2SEmmanuel Vadot d-cache-line-size = <64>; 48aa1a8ff2SEmmanuel Vadot d-cache-sets = <128>; 49aa1a8ff2SEmmanuel Vadot next-level-cache = <&l2_0>; 50aa1a8ff2SEmmanuel Vadot clocks = <&k3_clks 135 0>; 51aa1a8ff2SEmmanuel Vadot }; 52aa1a8ff2SEmmanuel Vadot 53aa1a8ff2SEmmanuel Vadot cpu1: cpu@1 { 54aa1a8ff2SEmmanuel Vadot compatible = "arm,cortex-a53"; 55aa1a8ff2SEmmanuel Vadot reg = <0x001>; 56aa1a8ff2SEmmanuel Vadot device_type = "cpu"; 57aa1a8ff2SEmmanuel Vadot enable-method = "psci"; 58aa1a8ff2SEmmanuel Vadot i-cache-size = <0x8000>; 59aa1a8ff2SEmmanuel Vadot i-cache-line-size = <64>; 60aa1a8ff2SEmmanuel Vadot i-cache-sets = <256>; 61aa1a8ff2SEmmanuel Vadot d-cache-size = <0x8000>; 62aa1a8ff2SEmmanuel Vadot d-cache-line-size = <64>; 63aa1a8ff2SEmmanuel Vadot d-cache-sets = <128>; 64aa1a8ff2SEmmanuel Vadot next-level-cache = <&l2_0>; 65aa1a8ff2SEmmanuel Vadot clocks = <&k3_clks 136 0>; 66aa1a8ff2SEmmanuel Vadot }; 67aa1a8ff2SEmmanuel Vadot 68aa1a8ff2SEmmanuel Vadot cpu2: cpu@2 { 69aa1a8ff2SEmmanuel Vadot compatible = "arm,cortex-a53"; 70aa1a8ff2SEmmanuel Vadot reg = <0x002>; 71aa1a8ff2SEmmanuel Vadot device_type = "cpu"; 72aa1a8ff2SEmmanuel Vadot enable-method = "psci"; 73aa1a8ff2SEmmanuel Vadot i-cache-size = <0x8000>; 74aa1a8ff2SEmmanuel Vadot i-cache-line-size = <64>; 75aa1a8ff2SEmmanuel Vadot i-cache-sets = <256>; 76aa1a8ff2SEmmanuel Vadot d-cache-size = <0x8000>; 77aa1a8ff2SEmmanuel Vadot d-cache-line-size = <64>; 78aa1a8ff2SEmmanuel Vadot d-cache-sets = <128>; 79aa1a8ff2SEmmanuel Vadot next-level-cache = <&l2_0>; 80aa1a8ff2SEmmanuel Vadot clocks = <&k3_clks 137 0>; 81aa1a8ff2SEmmanuel Vadot }; 82aa1a8ff2SEmmanuel Vadot 83aa1a8ff2SEmmanuel Vadot cpu3: cpu@3 { 84aa1a8ff2SEmmanuel Vadot compatible = "arm,cortex-a53"; 85aa1a8ff2SEmmanuel Vadot reg = <0x003>; 86aa1a8ff2SEmmanuel Vadot device_type = "cpu"; 87aa1a8ff2SEmmanuel Vadot enable-method = "psci"; 88aa1a8ff2SEmmanuel Vadot i-cache-size = <0x8000>; 89aa1a8ff2SEmmanuel Vadot i-cache-line-size = <64>; 90aa1a8ff2SEmmanuel Vadot i-cache-sets = <256>; 91aa1a8ff2SEmmanuel Vadot d-cache-size = <0x8000>; 92aa1a8ff2SEmmanuel Vadot d-cache-line-size = <64>; 93aa1a8ff2SEmmanuel Vadot d-cache-sets = <128>; 94aa1a8ff2SEmmanuel Vadot next-level-cache = <&l2_0>; 95aa1a8ff2SEmmanuel Vadot clocks = <&k3_clks 138 0>; 96aa1a8ff2SEmmanuel Vadot }; 97aa1a8ff2SEmmanuel Vadot }; 98aa1a8ff2SEmmanuel Vadot 99aa1a8ff2SEmmanuel Vadot l2_0: l2-cache0 { 100aa1a8ff2SEmmanuel Vadot compatible = "cache"; 101aa1a8ff2SEmmanuel Vadot cache-unified; 102aa1a8ff2SEmmanuel Vadot cache-level = <2>; 103aa1a8ff2SEmmanuel Vadot cache-size = <0x80000>; 104aa1a8ff2SEmmanuel Vadot cache-line-size = <64>; 105aa1a8ff2SEmmanuel Vadot cache-sets = <512>; 106aa1a8ff2SEmmanuel Vadot }; 107aa1a8ff2SEmmanuel Vadot}; 108