Lines Matching +full:cache +full:-
1 // SPDX-License-Identifier: GPL-2.0
5 * Architecture Envelope Model (AEM) ARMv8-A
11 /dts-v1/;
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include "rtsm_ve-motherboard.dtsi"
18 #include "rtsm_ve-motherboard-rs2.dtsi"
22 compatible = "arm,fvp-base-revc", "arm,vexpress";
23 interrupt-parent = <&gic>;
24 #address-cells = <2>;
25 #size-cells = <2>;
37 compatible = "arm,psci-0.2";
42 #address-cells = <2>;
43 #size-cells = <0>;
49 enable-method = "psci";
50 i-cache-size = <0x8000>;
51 i-cache-line-size = <64>;
52 i-cache-sets = <256>;
53 d-cache-size = <0x8000>;
54 d-cache-line-size = <64>;
55 d-cache-sets = <256>;
56 next-level-cache = <&C0_L2>;
62 enable-method = "psci";
63 i-cache-size = <0x8000>;
64 i-cache-line-size = <64>;
65 i-cache-sets = <256>;
66 d-cache-size = <0x8000>;
67 d-cache-line-size = <64>;
68 d-cache-sets = <256>;
69 next-level-cache = <&C0_L2>;
75 enable-method = "psci";
76 i-cache-size = <0x8000>;
77 i-cache-line-size = <64>;
78 i-cache-sets = <256>;
79 d-cache-size = <0x8000>;
80 d-cache-line-size = <64>;
81 d-cache-sets = <256>;
82 next-level-cache = <&C0_L2>;
88 enable-method = "psci";
89 i-cache-size = <0x8000>;
90 i-cache-line-size = <64>;
91 i-cache-sets = <256>;
92 d-cache-size = <0x8000>;
93 d-cache-line-size = <64>;
94 d-cache-sets = <256>;
95 next-level-cache = <&C0_L2>;
101 enable-method = "psci";
102 i-cache-size = <0x8000>;
103 i-cache-line-size = <64>;
104 i-cache-sets = <256>;
105 d-cache-size = <0x8000>;
106 d-cache-line-size = <64>;
107 d-cache-sets = <256>;
108 next-level-cache = <&C1_L2>;
114 enable-method = "psci";
115 i-cache-size = <0x8000>;
116 i-cache-line-size = <64>;
117 i-cache-sets = <256>;
118 d-cache-size = <0x8000>;
119 d-cache-line-size = <64>;
120 d-cache-sets = <256>;
121 next-level-cache = <&C1_L2>;
127 enable-method = "psci";
128 i-cache-size = <0x8000>;
129 i-cache-line-size = <64>;
130 i-cache-sets = <256>;
131 d-cache-size = <0x8000>;
132 d-cache-line-size = <64>;
133 d-cache-sets = <256>;
134 next-level-cache = <&C1_L2>;
140 enable-method = "psci";
141 i-cache-size = <0x8000>;
142 i-cache-line-size = <64>;
143 i-cache-sets = <256>;
144 d-cache-size = <0x8000>;
145 d-cache-line-size = <64>;
146 d-cache-sets = <256>;
147 next-level-cache = <&C1_L2>;
149 C0_L2: l2-cache0 {
150 compatible = "cache";
151 cache-size = <0x80000>;
152 cache-line-size = <64>;
153 cache-sets = <512>;
154 cache-level = <2>;
155 cache-unified;
158 C1_L2: l2-cache1 {
159 compatible = "cache";
160 cache-size = <0x80000>;
161 cache-line-size = <64>;
162 cache-sets = <512>;
163 cache-level = <2>;
164 cache-unified;
174 reserved-memory {
175 #address-cells = <2>;
176 #size-cells = <2>;
182 compatible = "shared-dma-pool";
184 no-map;
188 gic: interrupt-controller@2f000000 {
189 compatible = "arm,gic-v3";
190 #interrupt-cells = <3>;
191 #address-cells = <2>;
192 #size-cells = <2>;
194 interrupt-controller;
202 its: msi-controller@2f020000 {
203 #msi-cells = <1>;
204 compatible = "arm,gic-v3-its";
206 msi-controller;
211 compatible = "arm,armv8-timer";
219 compatible = "arm,armv8-pmuv3";
223 spe-pmu {
224 compatible = "arm,statistical-profiling-extension-v1";
229 #address-cells = <0x3>;
230 #size-cells = <0x2>;
231 #interrupt-cells = <0x1>;
232 compatible = "pci-host-ecam-generic";
234 bus-range = <0x0 0x1>;
237 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
241 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
242 msi-map = <0x0 &its 0x0 0x10000>;
243 iommu-map = <0x0 &smmu 0x0 0x10000>;
245 dma-coherent;
249 compatible = "arm,smmu-v3";
255 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
256 dma-coherent;
257 #iommu-cells = <1>;
258 msi-parent = <&its 0x10000>;
262 compatible = "arm,rtsm-display";
265 remote-endpoint = <&clcd_pads>;
271 #interrupt-cells = <1>;
272 interrupt-map-mask = <0 0 63>;
273 interrupt-map = <0 0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,