Lines Matching +full:cache +full:-
1 // SPDX-License-Identifier: GPL-2.0
7 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/soc/ti,sci_pm_domain.h>
15 #include "k3-pinctrl.h"
20 interrupt-parent = <&gic500>;
21 #address-cells = <2>;
22 #size-cells = <2>;
25 #address-cells = <1>;
26 #size-cells = <0>;
27 cpu-map {
66 compatible = "arm,cortex-a72";
69 enable-method = "psci";
70 i-cache-size = <0xc000>;
71 i-cache-line-size = <64>;
72 i-cache-sets = <256>;
73 d-cache-size = <0x8000>;
74 d-cache-line-size = <64>;
75 d-cache-sets = <256>;
76 next-level-cache = <&L2_0>;
80 compatible = "arm,cortex-a72";
83 enable-method = "psci";
84 i-cache-size = <0xc000>;
85 i-cache-line-size = <64>;
86 i-cache-sets = <256>;
87 d-cache-size = <0x8000>;
88 d-cache-line-size = <64>;
89 d-cache-sets = <256>;
90 next-level-cache = <&L2_0>;
94 compatible = "arm,cortex-a72";
97 enable-method = "psci";
98 i-cache-size = <0xc000>;
99 i-cache-line-size = <64>;
100 i-cache-sets = <256>;
101 d-cache-size = <0x8000>;
102 d-cache-line-size = <64>;
103 d-cache-sets = <256>;
104 next-level-cache = <&L2_0>;
108 compatible = "arm,cortex-a72";
111 enable-method = "psci";
112 i-cache-size = <0xc000>;
113 i-cache-line-size = <64>;
114 i-cache-sets = <256>;
115 d-cache-size = <0x8000>;
116 d-cache-line-size = <64>;
117 d-cache-sets = <256>;
118 next-level-cache = <&L2_0>;
122 compatible = "arm,cortex-a72";
125 enable-method = "psci";
126 i-cache-size = <0xc000>;
127 i-cache-line-size = <64>;
128 i-cache-sets = <256>;
129 d-cache-size = <0x8000>;
130 d-cache-line-size = <64>;
131 d-cache-sets = <256>;
132 next-level-cache = <&L2_1>;
136 compatible = "arm,cortex-a72";
139 enable-method = "psci";
140 i-cache-size = <0xc000>;
141 i-cache-line-size = <64>;
142 i-cache-sets = <256>;
143 d-cache-size = <0x8000>;
144 d-cache-line-size = <64>;
145 d-cache-sets = <256>;
146 next-level-cache = <&L2_1>;
150 compatible = "arm,cortex-a72";
153 enable-method = "psci";
154 i-cache-size = <0xc000>;
155 i-cache-line-size = <64>;
156 i-cache-sets = <256>;
157 d-cache-size = <0x8000>;
158 d-cache-line-size = <64>;
159 d-cache-sets = <256>;
160 next-level-cache = <&L2_1>;
164 compatible = "arm,cortex-a72";
167 enable-method = "psci";
168 i-cache-size = <0xc000>;
169 i-cache-line-size = <64>;
170 i-cache-sets = <256>;
171 d-cache-size = <0x8000>;
172 d-cache-line-size = <64>;
173 d-cache-sets = <256>;
174 next-level-cache = <&L2_1>;
178 L2_0: l2-cache0 {
179 compatible = "cache";
180 cache-level = <2>;
181 cache-unified;
182 cache-size = <0x200000>;
183 cache-line-size = <64>;
184 cache-sets = <1024>;
185 next-level-cache = <&msmc_l3>;
188 L2_1: l2-cache1 {
189 compatible = "cache";
190 cache-level = <2>;
191 cache-unified;
192 cache-size = <0x200000>;
193 cache-line-size = <64>;
194 cache-sets = <1024>;
195 next-level-cache = <&msmc_l3>;
198 msmc_l3: l3-cache0 {
199 compatible = "cache";
200 cache-level = <3>;
201 cache-unified;
206 compatible = "linaro,optee-tz";
211 compatible = "arm,psci-1.0";
216 a72_timer0: timer-cl0-cpu0 {
217 compatible = "arm,armv8-timer";
225 compatible = "arm,cortex-a72-pmu";
231 bootph-all;
232 compatible = "simple-bus";
233 #address-cells = <2>;
234 #size-cells = <2>;
267 bootph-all;
268 compatible = "simple-bus";
269 #address-cells = <2>;
270 #size-cells = <2>;
287 thermal_zones: thermal-zones {
288 #include "k3-j784s4-thermal.dtsi"
293 #include "k3-j784s4-main.dtsi"
294 #include "k3-j784s4-mcu-wakeup.dtsi"