xref: /freebsd/sys/contrib/device-tree/src/arm64/broadcom/bcm2712.dtsi (revision b2d2a78ad80ec68d4a17f5aef97d21686cb1e29b)

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "brcm,bcm2712";

	#address-cells = <2>;
	#size-cells = <2>;

	interrupt-parent = <&gicv2>;

	clocks {
		/* The oscillator is the root of the clock tree. */
		clk_osc: clk-osc {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-output-names = "osc";
			clock-frequency = <54000000>;
		};

		clk_vpu: clk-vpu {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <750000000>;
			clock-output-names = "vpu-clock";
		};

		clk_uart: clk-uart {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <9216000>;
			clock-output-names = "uart-clock";
		};

		clk_emmc2: clk-emmc2 {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <200000000>;
			clock-output-names = "emmc2-clock";
		};
	};

	cpus: cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		/* Source for L1 d/i cache-line-size, cache-sets, cache-size
		 * https://developer.arm.com/documentation/100798/0401/L1-memory-system/About-the-L1-memory-system?lang=en
		 * Source for L2 cache-line-size and cache-sets:
		 * https://developer.arm.com/documentation/100798/0401/L2-memory-system/About-the-L2-memory-system?lang=en
		 * and for cache-size:
		 * https://www.raspberrypi.com/documentation/computers/processors.html#bcm2712
		 */
		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a76";
			reg = <0x000>;
			enable-method = "psci";
			d-cache-size = <0x10000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
			i-cache-size = <0x10000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
			next-level-cache = <&l2_cache_l0>;

			l2_cache_l0: l2-cache-l0 {
				compatible = "cache";
				cache-size = <0x80000>;
				cache-line-size = <128>;
				cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
				cache-level = <2>;
				cache-unified;
				next-level-cache = <&l3_cache>;
			};
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a76";
			reg = <0x100>;
			enable-method = "psci";
			d-cache-size = <0x10000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
			i-cache-size = <0x10000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
			next-level-cache = <&l2_cache_l1>;

			l2_cache_l1: l2-cache-l1 {
				compatible = "cache";
				cache-size = <0x80000>;
				cache-line-size = <128>;
				cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
				cache-level = <2>;
				cache-unified;
				next-level-cache = <&l3_cache>;
			};
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a76";
			reg = <0x200>;
			enable-method = "psci";
			d-cache-size = <0x10000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
			i-cache-size = <0x10000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
			next-level-cache = <&l2_cache_l2>;

			l2_cache_l2: l2-cache-l2 {
				compatible = "cache";
				cache-size = <0x80000>;
				cache-line-size = <128>;
				cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
				cache-level = <2>;
				cache-unified;
				next-level-cache = <&l3_cache>;
			};
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a76";
			reg = <0x300>;
			enable-method = "psci";
			d-cache-size = <0x10000>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
			i-cache-size = <0x10000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
			next-level-cache = <&l2_cache_l3>;

			l2_cache_l3: l2-cache-l3 {
				compatible = "cache";
				cache-size = <0x80000>;
				cache-line-size = <128>;
				cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
				cache-level = <2>;
				cache-unified;
				next-level-cache = <&l3_cache>;
			};
		};

		/* Source for cache-line-size and cache-sets:
		 * https://developer.arm.com/documentation/100453/0401/L3-cache?lang=en
		 * Source for cache-size:
		 * https://www.raspberrypi.com/documentation/computers/processors.html#bcm2712
		 */
		l3_cache: l3-cache {
			compatible = "cache";
			cache-size = <0x200000>;
			cache-line-size = <64>;
			cache-sets = <2048>; // 2MiB(size)/64(line-size)=32768ways/16-way set
			cache-level = <3>;
			cache-unified;
		};
	};

	psci {
		method = "smc";
		compatible = "arm,psci-1.0", "arm,psci-0.2";
	};

	rmem: reserved-memory {
		ranges;
		#address-cells = <2>;
		#size-cells = <2>;

		atf@0 {
			reg = <0x0 0x0 0x0 0x80000>;
			no-map;
		};

		cma: linux,cma {
			compatible = "shared-dma-pool";
			size = <0x0 0x4000000>; /* 64MB */
			reusable;
			linux,cma-default;
			alloc-ranges = <0x0 0x00000000 0x0 0x40000000>;
		};
	};

	soc: soc@107c000000 {
		compatible = "simple-bus";
		ranges = <0x00000000  0x10 0x00000000  0x80000000>;
		#address-cells = <1>;
		#size-cells = <1>;

		sdio1: mmc@fff000 {
			compatible = "brcm,bcm2712-sdhci",
				     "brcm,sdhci-brcmstb";
			reg = <0x00fff000 0x260>,
			      <0x00fff400 0x200>;
			reg-names = "host", "cfg";
			interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_emmc2>;
			clock-names = "sw_sdio";
			mmc-ddr-3_3v;
		};

		system_timer: timer@7c003000 {
			compatible = "brcm,bcm2835-system-timer";
			reg = <0x7c003000 0x1000>;
			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <1000000>;
		};

		mailbox: mailbox@7c013880 {
			compatible = "brcm,bcm2835-mbox";
			reg = <0x7c013880 0x40>;
			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
			#mbox-cells = <0>;
		};

		local_intc: interrupt-controller@7cd00000 {
			compatible = "brcm,bcm2836-l1-intc";
			reg = <0x7cd00000 0x100>;
		};

		uart10: serial@7d001000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x7d001000 0x200>;
			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_uart>, <&clk_vpu>;
			clock-names = "uartclk", "apb_pclk";
			arm,primecell-periphid = <0x00241011>;
			status = "disabled";
		};

		interrupt-controller@7d517000 {
			compatible = "brcm,bcm7271-l2-intc";
			reg = <0x7d517000 0x10>;
			interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gio_aon: gpio@7d517c00 {
			compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
			reg = <0x7d517c00 0x40>;
			gpio-controller;
			#gpio-cells = <2>;
			brcm,gpio-bank-widths = <17 6>;
			/* The lack of 'interrupt-controller' property here is intended:
			 * don't use GIO_AON as an interrupt controller because it will
			 * clash with the firmware monitoring the PMIC interrupt via the VPU.
			 */
		};

		gicv2: interrupt-controller@7fff9000 {
			compatible = "arm,gic-400";
			reg = <0x7fff9000 0x1000>,
			      <0x7fffa000 0x2000>,
			      <0x7fffc000 0x2000>,
			      <0x7fffe000 0x2000>;
			interrupt-controller;
			#interrupt-cells = <3>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
					  IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
					  IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
					  IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
					  IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(4) |
					  IRQ_TYPE_LEVEL_LOW)>;
	};
};