Lines Matching +full:cache +full:-
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "armada-ap806.dtsi"
12 compatible = "marvell,armada-ap806-quad", "marvell,armada-ap806";
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "arm,cortex-a72";
22 enable-method = "psci";
23 #cooling-cells = <2>;
25 i-cache-size = <0xc000>;
26 i-cache-line-size = <64>;
27 i-cache-sets = <256>;
28 d-cache-size = <0x8000>;
29 d-cache-line-size = <64>;
30 d-cache-sets = <256>;
31 next-level-cache = <&l2_0>;
35 compatible = "arm,cortex-a72";
37 enable-method = "psci";
38 #cooling-cells = <2>;
40 i-cache-size = <0xc000>;
41 i-cache-line-size = <64>;
42 i-cache-sets = <256>;
43 d-cache-size = <0x8000>;
44 d-cache-line-size = <64>;
45 d-cache-sets = <256>;
46 next-level-cache = <&l2_0>;
50 compatible = "arm,cortex-a72";
52 enable-method = "psci";
53 #cooling-cells = <2>;
55 i-cache-size = <0xc000>;
56 i-cache-line-size = <64>;
57 i-cache-sets = <256>;
58 d-cache-size = <0x8000>;
59 d-cache-line-size = <64>;
60 d-cache-sets = <256>;
61 next-level-cache = <&l2_1>;
65 compatible = "arm,cortex-a72";
67 enable-method = "psci";
68 #cooling-cells = <2>;
70 i-cache-size = <0xc000>;
71 i-cache-line-size = <64>;
72 i-cache-sets = <256>;
73 d-cache-size = <0x8000>;
74 d-cache-line-size = <64>;
75 d-cache-sets = <256>;
76 next-level-cache = <&l2_1>;
79 l2_0: l2-cache0 {
80 compatible = "cache";
81 cache-size = <0x80000>;
82 cache-line-size = <64>;
83 cache-sets = <512>;
84 cache-level = <2>;
85 cache-unified;
88 l2_1: l2-cache1 {
89 compatible = "cache";
90 cache-size = <0x80000>;
91 cache-line-size = <64>;
92 cache-sets = <512>;
93 cache-level = <2>;
94 cache-unified;