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Searched +full:5 +full:b110000 (Results 1 – 11 of 11) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/usb/
H A Dfsl,imx8qm-cdns3.yaml72 usb@5b110000 {
88 usb@5b120000 {
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8dxl-ss-conn.dtsi26 eqos: ethernet@5b050000 {
45 usbotg2: usb@5b0e0000 {
65 usbmisc2: usbmisc@5b0e0200 {
71 usbphy2: usbphy@5b110000 {
79 eqos_lpcg: clock-controller@5b240000 {
99 usb2_2_lpcg: clock-controller@5b280000 {
H A Dimx8-ss-conn.dtsi31 conn_subsys: bus@5b000000 {
37 usbotg1: usb@5b0d0000 {
52 usbmisc1: usbmisc@5b0d0200 {
58 usbphy1: usbphy@5b100000 {
66 usdhc1: mmc@5b010000 {
77 usdhc2: mmc@5b020000 {
90 usdhc3: mmc@5b030000 {
101 fec1: ethernet@5b040000 {
121 fec2: ethernet@5b050000 {
141 usbotg3: usb@5b11000
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsDSPInstrFormats.td65 class ADDU_QB_FMT<bits<5> op> : DSPInst {
66 bits<5> rd;
67 bits<5> rs;
68 bits<5> rt;
76 let Inst{5-0} = 0b010000;
79 class RADDU_W_QB_FMT<bits<5> op> : DSPInst {
80 bits<5> rd;
81 bits<5> rs;
89 let Inst{5-0} = 0b010000;
93 class CMP_EQ_QB_R2_FMT<bits<5> op> : DSPInst {
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/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.td128 let ParserMatchClass = ShiftAmtImmAsmOperand<5>;
353 def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned
637 defm LDFA : LoadASI<"ld", 0b110000, FPRegs>;
645 defm LDC : Load<"ld", 0b110000, load, CoprocRegs, i32>;
688 // Section B.5 - Store Floating-point Instructions, p. 97
1135 let isBarrier = 1, isTerminator = 1, rd = 0b01000, rs1 = 0, simm13 = 5 in
1136 def TA5 : F3_2<0b10, 0b111010, (outs), (ins), "ta 5", [(trap)]>;
1166 def WRASRrr : F3_1<2, 0b110000,
1169 def WRASRri : F3_2<2, 0b110000,
1697 def SIR: F3_2<2, 0b110000, (outs),
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoV.td60 def simm5 : RISCVSImmLeafOp<5> {
64 return isInt<5>(Imm);
76 [{return (isInt<5>(Imm) && Imm != -16) || Imm == 16;}]> {
82 return (isInt<5>(Imm) && Imm != -16) || Imm == 16;
88 [{return Imm != 0 && ((isInt<5>(Imm) && Imm != -16) || Imm == 16);}]>;
530 class VALUVs2<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, string opcodestr>
618 multiclass VALU_MV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
723 multiclass VSQR_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
728 multiclass VRCP_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
758 multiclass VCLS_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.td208 multiclass F3R_2RUS<bits<5> opc1, bits<5> opc2, string OpcStr, SDNode OpNode> {
217 multiclass F3R_2RUS_np<bits<5> opc1, bits<5> opc2, string OpcStr> {
224 multiclass F3R_2RBITP<bits<5> opc1, bits<5> opc2, string OpcStr,
234 class F3R<bits<5> opc, string OpcStr, SDNode OpNode> :
239 class F3R_np<bits<5> opc, string OpcStr> :
839 def SETPSC_2r : _FR2R<0b110000, (outs), (ins GRRegs:$src1, GRRegs:$src2),
1273 def : Pat<(mul GRRegs:$src, 5),
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DSVEInstrFormats.td363 bits<5> pattern;
370 let Inst{9-5} = pattern;
741 let Inst{23-22} = opc{5-4};
772 let Inst{23-22} = opc{5-4};
778 let Inst{8-5} = Pn;
797 class sve_int_pfirst_next<bits<2> sz8_64, bits<5> opc, string asm,
811 let Inst{8-5} = Pg;
822 multiclass sve_int_pfirst<bits<5> opc, string asm, SDPatternOperator op> {
828 multiclass sve_int_pnext<bits<5> opc, string asm, SDPatternOperator op> {
844 class sve_int_count_r<bits<2> sz8_64, bits<5> opc, string asm,
[all …]
H A DAArch64SVEInstrInfo.td117 def SDT_AArch64_SCATTER_SV : SDTypeProfile<0, 5, [
122 def SDT_AArch64_SCATTER_VS : SDTypeProfile<0, 5, [
1847 def : Pat<(nxv1i1 (extract_subvector nxv8i1:$Ps, (i64 5))),
1880 def : Pat<(nxv1i1 (extract_subvector nxv16i1:$Ps, (i64 5))),
2559 let AddedComplexity = 5 in {
2590 let AddedComplexity = 5 in {
2606 let Predicates = [HasSVEorSME, UseScalarIncVL], AddedComplexity = 5 in {
3590 defm SQADD_ZPmZ : sve2_int_arith_pred<0b110000, "sqadd", int_aarch64_sve_sqadd>;
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonDepInstrInfo.td16 let Inst{13-5} = 0b000000100;
27 let Inst{13-5} = 0b000000110;
36 let Inst{13-5} = 0b000000101;
48 let Inst{7-5} = 0b000;
64 let Inst{7-5} = 0b011;
76 let Inst{7-5} = 0b010;
88 let Inst{7-5} = 0b001;
100 let Inst{7-5} = 0b000;
112 let Inst{7-5} = 0b111;
125 let Inst{7-5}
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrMVE.td464 bits<5> imm;
470 let Inst{5-4} = op5_4{1-0};
490 let Inst{5-4} = op5_4{1-0};
518 bits<5> imm;
524 let Inst{5-4} = op5_4{1-0};
539 let Inst{5} = op5;
624 let Inst{5} = Qm{3};
674 let Inst{5} = A;
773 let Inst{5} = A;
791 SDTCisVec<4>, SDTCisVec<5>
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