Lines Matching +full:5 +full:b110000

65 class ADDU_QB_FMT<bits<5> op> : DSPInst {
66   bits<5> rd;
67   bits<5> rs;
68   bits<5> rt;
76   let Inst{5-0}   = 0b010000;
79 class RADDU_W_QB_FMT<bits<5> op> : DSPInst {
80   bits<5> rd;
81   bits<5> rs;
89   let Inst{5-0}   = 0b010000;
93 class CMP_EQ_QB_R2_FMT<bits<5> op> : DSPInst {
94   bits<5> rs;
95   bits<5> rt;
103   let Inst{5-0}   = 0b010001;
106 class CMP_EQ_QB_R3_FMT<bits<5> op> : DSPInst {
107   bits<5> rs;
108   bits<5> rt;
109   bits<5> rd;
117   let Inst{5-0}   = 0b010001;
120 class PRECR_SRA_PH_W_FMT<bits<5> op> : DSPInst {
121   bits<5> rs;
122   bits<5> rt;
123   bits<5> sa;
131   let Inst{5-0}   = 0b010001;
135 class ABSQ_S_PH_R2_FMT<bits<5> op> : DSPInst {
136   bits<5> rd;
137   bits<5> rt;
145   let Inst{5-0}   = 0b010010;
149 class REPL_FMT<bits<5> op> : DSPInst {
150   bits<5> rd;
158   let Inst{5-0}   = 0b010010;
162 class SHLL_QB_FMT<bits<5> op> : DSPInst {
163   bits<5> rd;
164   bits<5> rt;
165   bits<5> rs_sa;
173   let Inst{5-0}   = 0b010011;
177 class LX_FMT<bits<5> op> : DSPInst {
178   bits<5> rd;
179   bits<5> base;
180   bits<5> index;
188   let Inst{5-0} = 0b001010;
192 class ADDUH_QB_FMT<bits<5> op> : DSPInst {
193   bits<5> rd;
194   bits<5> rs;
195   bits<5> rt;
203   let Inst{5-0} = 0b011000;
207 class APPEND_FMT<bits<5> op> : DSPInst {
208   bits<5> rt;
209   bits<5> rs;
210   bits<5> sa;
218   let Inst{5-0} = 0b110001;
222 class DPA_W_PH_FMT<bits<5> op> : DSPInst {
224   bits<5> rs;
225   bits<5> rt;
234   let Inst{5-0} = 0b110000;
240   bits<5> rs;
241   bits<5> rt;
250   let Inst{5-0} = funct;
255   bits<5> rd;
264   let Inst{5-0} = funct;
269   bits<5> rs;
277   let Inst{5-0} = funct;
281 class EXTR_W_TY1_FMT<bits<5> op> : DSPInst {
282   bits<5> rt;
284   bits<5> shift_rs;
293   let Inst{5-0} = 0b111000;
297 class SHILO_R1_FMT<bits<5> op> : DSPInst {
307   let Inst{5-0} = 0b111000;
310 class SHILO_R2_FMT<bits<5> op> : DSPInst {
312   bits<5> rs;
320   let Inst{5-0} = 0b111000;
323 class RDDSP_FMT<bits<5> op> : DSPInst {
324   bits<5> rd;
332   let Inst{5-0} = 0b111000;
335 class WRDSP_FMT<bits<5> op> : DSPInst {
336   bits<5> rs;
344   let Inst{5-0} = 0b111000;
347 class BPOSGE32_FMT<bits<5> op> : DSPInst {
359   bits<5> rt;
360   bits<5> rs;
367   let Inst{5-0} = op;