1//===-- RISCVInstrInfoV.td - RISC-V 'V' instructions -------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8/// 9/// This file describes the RISC-V instructions from the standard 'V' Vector 10/// extension, version 1.0. 11/// 12//===----------------------------------------------------------------------===// 13 14include "RISCVInstrFormatsV.td" 15 16//===----------------------------------------------------------------------===// 17// Operand and SDNode transformation definitions. 18//===----------------------------------------------------------------------===// 19 20class VTypeIAsmOperand<int VTypeINum> : AsmOperandClass { 21 let Name = "VTypeI" # VTypeINum; 22 let ParserMethod = "parseVTypeI"; 23 let DiagnosticType = "InvalidVTypeI"; 24 let RenderMethod = "addVTypeIOperands"; 25} 26 27class VTypeIOp<int VTypeINum> : RISCVOp { 28 let ParserMatchClass = VTypeIAsmOperand<VTypeINum>; 29 let PrintMethod = "printVTypeI"; 30 let DecoderMethod = "decodeUImmOperand<"#VTypeINum#">"; 31 let OperandType = "OPERAND_VTYPEI" # VTypeINum; 32 let MCOperandPredicate = [{ 33 int64_t Imm; 34 if (MCOp.evaluateAsConstantImm(Imm)) 35 return isUInt<VTypeINum>(Imm); 36 return MCOp.isBareSymbolRef(); 37 }]; 38} 39 40def VTypeIOp10 : VTypeIOp<10>; 41def VTypeIOp11 : VTypeIOp<11>; 42 43def VMaskAsmOperand : AsmOperandClass { 44 let Name = "RVVMaskRegOpOperand"; 45 let RenderMethod = "addRegOperands"; 46 let PredicateMethod = "isV0Reg"; 47 let ParserMethod = "parseMaskReg"; 48 let IsOptional = 1; 49 let DefaultMethod = "defaultMaskRegOp"; 50 let DiagnosticType = "InvalidVMaskRegister"; 51} 52 53def VMaskOp : RegisterOperand<VMV0> { 54 let ParserMatchClass = VMaskAsmOperand; 55 let PrintMethod = "printVMaskReg"; 56 let EncoderMethod = "getVMaskReg"; 57 let DecoderMethod = "decodeVMaskReg"; 58} 59 60def simm5 : RISCVSImmLeafOp<5> { 61 let MCOperandPredicate = [{ 62 int64_t Imm; 63 if (MCOp.evaluateAsConstantImm(Imm)) 64 return isInt<5>(Imm); 65 return MCOp.isBareSymbolRef(); 66 }]; 67} 68 69def SImm5Plus1AsmOperand : AsmOperandClass { 70 let Name = "SImm5Plus1"; 71 let RenderMethod = "addImmOperands"; 72 let DiagnosticType = "InvalidSImm5Plus1"; 73} 74 75def simm5_plus1 : RISCVOp, ImmLeaf<XLenVT, 76 [{return (isInt<5>(Imm) && Imm != -16) || Imm == 16;}]> { 77 let ParserMatchClass = SImm5Plus1AsmOperand; 78 let OperandType = "OPERAND_SIMM5_PLUS1"; 79 let MCOperandPredicate = [{ 80 int64_t Imm; 81 if (MCOp.evaluateAsConstantImm(Imm)) 82 return (isInt<5>(Imm) && Imm != -16) || Imm == 16; 83 return MCOp.isBareSymbolRef(); 84 }]; 85} 86 87def simm5_plus1_nonzero : ImmLeaf<XLenVT, 88 [{return Imm != 0 && ((isInt<5>(Imm) && Imm != -16) || Imm == 16);}]>; 89 90//===----------------------------------------------------------------------===// 91// Scheduling definitions. 92//===----------------------------------------------------------------------===// 93 94// Common class of scheduling definitions. 95// `ReadVMergeOp` will be prepended to reads if instruction is masked. 96// `ReadVMask` will be appended to reads if instruction is masked. 97// Operands: 98// `writes` SchedWrites that are listed for each explicit def operand 99// in order. 100// `reads` SchedReads that are listed for each explicit use operand. 101// `forceMasked` Forced to be masked (e.g. Add-with-Carry Instructions). 102// `forceMergeOpRead` Force to have read for merge operand. 103class SchedCommon<list<SchedWrite> writes, list<SchedRead> reads, 104 string mx = "WorstCase", int sew = 0, bit forceMasked = 0, 105 bit forceMergeOpRead = 0> : Sched<[]> { 106 defvar isMasked = !ne(!find(NAME, "_MASK"), -1); 107 defvar isMaskedOrForceMasked = !or(forceMasked, isMasked); 108 defvar mergeRead = !if(!or(!eq(mx, "WorstCase"), !eq(sew, 0)), 109 !cast<SchedRead>("ReadVMergeOp_" # mx), 110 !cast<SchedRead>("ReadVMergeOp_" # mx # "_E" #sew)); 111 defvar needsMergeRead = !or(isMaskedOrForceMasked, forceMergeOpRead); 112 defvar readsWithMask = 113 !if(isMaskedOrForceMasked, !listconcat(reads, [ReadVMask]), reads); 114 defvar allReads = 115 !if(needsMergeRead, !listconcat([mergeRead], readsWithMask), reads); 116 let SchedRW = !listconcat(writes, allReads); 117} 118 119// Common class of scheduling definitions for n-ary instructions. 120// The scheudling resources are relevant to LMUL and may be relevant to SEW. 121class SchedNary<string write, list<string> reads, string mx, int sew = 0, 122 bit forceMasked = 0, bit forceMergeOpRead = 0> 123 : SchedCommon<[!cast<SchedWrite>( 124 !if(sew, 125 write # "_" # mx # "_E" # sew, 126 write # "_" # mx))], 127 !foreach(read, reads, 128 !cast<SchedRead>(!if(sew, read #"_" #mx #"_E" #sew, 129 read #"_" #mx))), 130 mx, sew, forceMasked, forceMergeOpRead>; 131 132// Classes with postfix "MC" are only used in MC layer. 133// For these classes, we assume that they are with the worst case costs and 134// `ReadVMask` is always needed (with some exceptions). 135 136// For instructions with no operand. 137class SchedNullary<string write, string mx, int sew = 0, bit forceMasked = 0, 138 bit forceMergeOpRead = 0>: 139 SchedNary<write, [], mx, sew, forceMasked, forceMergeOpRead>; 140class SchedNullaryMC<string write, bit forceMasked = 1>: 141 SchedNullary<write, "WorstCase", forceMasked=forceMasked>; 142 143// For instructions with one operand. 144class SchedUnary<string write, string read0, string mx, int sew = 0, 145 bit forceMasked = 0, bit forceMergeOpRead = 0>: 146 SchedNary<write, [read0], mx, sew, forceMasked, forceMergeOpRead>; 147class SchedUnaryMC<string write, string read0, bit forceMasked = 1>: 148 SchedUnary<write, read0, "WorstCase", forceMasked=forceMasked>; 149 150// For instructions with two operands. 151class SchedBinary<string write, string read0, string read1, string mx, 152 int sew = 0, bit forceMasked = 0, bit forceMergeOpRead = 0> 153 : SchedNary<write, [read0, read1], mx, sew, forceMasked, forceMergeOpRead>; 154class SchedBinaryMC<string write, string read0, string read1, 155 bit forceMasked = 1>: 156 SchedBinary<write, read0, read1, "WorstCase", forceMasked=forceMasked>; 157 158// For instructions with three operands. 159class SchedTernary<string write, string read0, string read1, string read2, 160 string mx, int sew = 0, bit forceMasked = 0> 161 : SchedNary<write, [read0, read1, read2], mx, sew, forceMasked>; 162class SchedTernaryMC<string write, string read0, string read1, string read2, 163 int sew = 0, bit forceMasked = 1>: 164 SchedNary<write, [read0, read1, read2], "WorstCase", sew, forceMasked>; 165 166// For reduction instructions. 167class SchedReduction<string write, string read, string mx, int sew, 168 bit forceMergeOpRead = 0> 169 : SchedCommon<[!cast<SchedWrite>(write #"_" #mx #"_E" #sew)], 170 !listsplat(!cast<SchedRead>(read), 3), mx, sew, forceMergeOpRead>; 171class SchedReductionMC<string write, string readV, string readV0>: 172 SchedCommon<[!cast<SchedWrite>(write # "_WorstCase")], 173 [!cast<SchedRead>(readV), !cast<SchedRead>(readV0)], 174 forceMasked=1>; 175 176// Whole Vector Register Move 177class VMVRSched<int n> : SchedCommon< 178 [!cast<SchedWrite>("WriteVMov" # n # "V")], 179 [!cast<SchedRead>("ReadVMov" # n # "V")] 180>; 181 182// Vector Unit-Stride Loads and Stores 183class VLESched<string lmul, bit forceMasked = 0> : SchedCommon< 184 [!cast<SchedWrite>("WriteVLDE_" # lmul)], 185 [ReadVLDX], mx=lmul, forceMasked=forceMasked 186>; 187class VLESchedMC : VLESched<"WorstCase", forceMasked=1>; 188 189class VSESched<string lmul, bit forceMasked = 0> : SchedCommon< 190 [!cast<SchedWrite>("WriteVSTE_" # lmul)], 191 [!cast<SchedRead>("ReadVSTEV_" # lmul), ReadVSTX], mx=lmul, 192 forceMasked=forceMasked 193>; 194class VSESchedMC : VSESched<"WorstCase", forceMasked=1>; 195 196// Vector Strided Loads and Stores 197class VLSSched<int eew, string emul, bit forceMasked = 0> : SchedCommon< 198 [!cast<SchedWrite>("WriteVLDS" # eew # "_" # emul)], 199 [ReadVLDX, ReadVLDSX], emul, eew, forceMasked 200>; 201class VLSSchedMC<int eew> : VLSSched<eew, "WorstCase", forceMasked=1>; 202 203class VSSSched<int eew, string emul, bit forceMasked = 0> : SchedCommon< 204 [!cast<SchedWrite>("WriteVSTS" # eew # "_" # emul)], 205 [!cast<SchedRead>("ReadVSTS" # eew # "V_" # emul), ReadVSTX, ReadVSTSX], 206 emul, eew, forceMasked 207>; 208class VSSSchedMC<int eew> : VSSSched<eew, "WorstCase", forceMasked=1>; 209 210// Vector Indexed Loads and Stores 211class VLXSched<int dataEEW, bit isOrdered, string dataEMUL, string idxEMUL, 212 bit forceMasked = 0> : SchedCommon< 213 [!cast<SchedWrite>("WriteVLD" # !if(isOrdered, "O", "U") # "X" # dataEEW # "_" # dataEMUL)], 214 [ReadVLDX, !cast<SchedRead>("ReadVLD" # !if(isOrdered, "O", "U") # "XV_" # idxEMUL)], 215 dataEMUL, dataEEW, forceMasked 216>; 217class VLXSchedMC<int dataEEW, bit isOrdered>: 218 VLXSched<dataEEW, isOrdered, "WorstCase", "WorstCase", forceMasked=1>; 219 220class VSXSched<int dataEEW, bit isOrdered, string dataEMUL, string idxEMUL, 221 bit forceMasked = 0> : SchedCommon< 222 [!cast<SchedWrite>("WriteVST" # !if(isOrdered, "O", "U") # "X" # dataEEW # "_" # dataEMUL)], 223 [!cast<SchedRead>("ReadVST" # !if(isOrdered, "O", "U") #"X" # dataEEW # "_" # dataEMUL), 224 ReadVSTX, !cast<SchedRead>("ReadVST" # !if(isOrdered, "O", "U") # "XV_" # idxEMUL)], 225 dataEMUL, dataEEW, forceMasked 226>; 227class VSXSchedMC<int dataEEW, bit isOrdered>: 228 VSXSched<dataEEW, isOrdered, "WorstCase", "WorstCase", forceMasked=1>; 229 230// Unit-stride Fault-Only-First Loads 231class VLFSched<string lmul, bit forceMasked = 0> : SchedCommon< 232 [!cast<SchedWrite>("WriteVLDFF_" # lmul)], 233 [ReadVLDX], mx=lmul, forceMasked=forceMasked 234>; 235class VLFSchedMC: VLFSched<"WorstCase", forceMasked=1>; 236 237// Unit-Stride Segment Loads and Stores 238class VLSEGSched<int nf, int eew, string emul, bit forceMasked = 0> : SchedCommon< 239 [!cast<SchedWrite>("WriteVLSEG" #nf #"e" #eew #"_" #emul)], 240 [ReadVLDX], emul, eew, forceMasked 241>; 242class VLSEGSchedMC<int nf, int eew> : VLSEGSched<nf, eew, "WorstCase", 243 forceMasked=1>; 244 245class VSSEGSched<int nf, int eew, string emul, bit forceMasked = 0> : SchedCommon< 246 [!cast<SchedWrite>("WriteVSSEG" # nf # "e" # eew # "_" # emul)], 247 [!cast<SchedRead>("ReadVSTEV_" #emul), ReadVSTX], emul, eew, forceMasked 248>; 249class VSSEGSchedMC<int nf, int eew> : VSSEGSched<nf, eew, "WorstCase", 250 forceMasked=1>; 251 252class VLSEGFFSched<int nf, int eew, string emul, bit forceMasked = 0> : SchedCommon< 253 [!cast<SchedWrite>("WriteVLSEGFF" # nf # "e" # eew # "_" # emul)], 254 [ReadVLDX], emul, eew, forceMasked 255>; 256class VLSEGFFSchedMC<int nf, int eew> : VLSEGFFSched<nf, eew, "WorstCase", 257 forceMasked=1>; 258 259// Strided Segment Loads and Stores 260class VLSSEGSched<int nf, int eew, string emul, bit forceMasked = 0> : SchedCommon< 261 [!cast<SchedWrite>("WriteVLSSEG" #nf #"e" #eew #"_" #emul)], 262 [ReadVLDX, ReadVLDSX], emul, eew, forceMasked 263>; 264class VLSSEGSchedMC<int nf, int eew> : VLSSEGSched<nf, eew, "WorstCase", 265 forceMasked=1>; 266 267class VSSSEGSched<int nf, int eew, string emul, bit forceMasked = 0> : SchedCommon< 268 [!cast<SchedWrite>("WriteVSSSEG" #nf #"e" #eew #"_" #emul)], 269 [!cast<SchedRead>("ReadVSTS" #eew #"V_" #emul), 270 ReadVSTX, ReadVSTSX], emul, eew, forceMasked 271>; 272class VSSSEGSchedMC<int nf, int eew> : VSSSEGSched<nf, eew, "WorstCase", 273 forceMasked=1>; 274 275// Indexed Segment Loads and Stores 276class VLXSEGSched<int nf, int eew, bit isOrdered, string emul, 277 bit forceMasked = 0> : SchedCommon< 278 [!cast<SchedWrite>("WriteVL" #!if(isOrdered, "O", "U") #"XSEG" #nf #"e" #eew #"_" #emul)], 279 [ReadVLDX, !cast<SchedRead>("ReadVLD" #!if(isOrdered, "O", "U") #"XV_" #emul)], 280 emul, eew, forceMasked 281>; 282class VLXSEGSchedMC<int nf, int eew, bit isOrdered>: 283 VLXSEGSched<nf, eew, isOrdered, "WorstCase", forceMasked=1>; 284 285// Passes sew=0 instead of eew=0 since this pseudo does not follow MX_E form. 286class VSXSEGSched<int nf, int eew, bit isOrdered, string emul, 287 bit forceMasked = 0> : SchedCommon< 288 [!cast<SchedWrite>("WriteVS" #!if(isOrdered, "O", "U") #"XSEG" #nf #"e" #eew #"_" #emul)], 289 [!cast<SchedRead>("ReadVST" #!if(isOrdered, "O", "U") #"X" #eew #"_" #emul), 290 ReadVSTX, !cast<SchedRead>("ReadVST" #!if(isOrdered, "O", "U") #"XV_" #emul)], 291 emul, sew=0, forceMasked=forceMasked 292>; 293class VSXSEGSchedMC<int nf, int eew, bit isOrdered>: 294 VSXSEGSched<nf, eew, isOrdered, "WorstCase", forceMasked=1>; 295 296//===----------------------------------------------------------------------===// 297// Instruction class templates 298//===----------------------------------------------------------------------===// 299 300let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in { 301// unit-stride load vd, (rs1), vm 302class VUnitStrideLoad<RISCVWidth width, string opcodestr> 303 : RVInstVLU<0b000, width.Value{3}, LUMOPUnitStride, width.Value{2-0}, 304 (outs VR:$vd), 305 (ins GPRMemZeroOffset:$rs1, VMaskOp:$vm), opcodestr, "$vd, ${rs1}$vm">; 306 307let vm = 1, RVVConstraint = NoConstraint in { 308// unit-stride whole register load vl<nf>r.v vd, (rs1) 309class VWholeLoad<bits<3> nf, RISCVWidth width, string opcodestr, RegisterClass VRC> 310 : RVInstVLU<nf, width.Value{3}, LUMOPUnitStrideWholeReg, 311 width.Value{2-0}, (outs VRC:$vd), (ins GPRMemZeroOffset:$rs1), 312 opcodestr, "$vd, $rs1"> { 313 let Uses = []; 314} 315 316// unit-stride mask load vd, (rs1) 317class VUnitStrideLoadMask<string opcodestr> 318 : RVInstVLU<0b000, LSWidth8.Value{3}, LUMOPUnitStrideMask, LSWidth8.Value{2-0}, 319 (outs VR:$vd), 320 (ins GPRMemZeroOffset:$rs1), opcodestr, "$vd, $rs1">; 321} // vm = 1, RVVConstraint = NoConstraint 322 323// unit-stride fault-only-first load vd, (rs1), vm 324class VUnitStrideLoadFF<RISCVWidth width, string opcodestr> 325 : RVInstVLU<0b000, width.Value{3}, LUMOPUnitStrideFF, width.Value{2-0}, 326 (outs VR:$vd), 327 (ins GPRMemZeroOffset:$rs1, VMaskOp:$vm), opcodestr, "$vd, ${rs1}$vm">; 328 329// strided load vd, (rs1), rs2, vm 330class VStridedLoad<RISCVWidth width, string opcodestr> 331 : RVInstVLS<0b000, width.Value{3}, width.Value{2-0}, 332 (outs VR:$vd), 333 (ins GPRMemZeroOffset:$rs1, GPR:$rs2, VMaskOp:$vm), opcodestr, 334 "$vd, $rs1, $rs2$vm">; 335 336// indexed load vd, (rs1), vs2, vm 337class VIndexedLoad<RISCVMOP mop, RISCVWidth width, string opcodestr> 338 : RVInstVLX<0b000, width.Value{3}, mop, width.Value{2-0}, 339 (outs VR:$vd), 340 (ins GPRMemZeroOffset:$rs1, VR:$vs2, VMaskOp:$vm), opcodestr, 341 "$vd, $rs1, $vs2$vm">; 342 343// unit-stride segment load vd, (rs1), vm 344class VUnitStrideSegmentLoad<bits<3> nf, RISCVWidth width, string opcodestr> 345 : RVInstVLU<nf, width.Value{3}, LUMOPUnitStride, width.Value{2-0}, 346 (outs VR:$vd), 347 (ins GPRMemZeroOffset:$rs1, VMaskOp:$vm), opcodestr, "$vd, ${rs1}$vm">; 348 349// segment fault-only-first load vd, (rs1), vm 350class VUnitStrideSegmentLoadFF<bits<3> nf, RISCVWidth width, string opcodestr> 351 : RVInstVLU<nf, width.Value{3}, LUMOPUnitStrideFF, width.Value{2-0}, 352 (outs VR:$vd), 353 (ins GPRMemZeroOffset:$rs1, VMaskOp:$vm), opcodestr, "$vd, ${rs1}$vm">; 354 355// strided segment load vd, (rs1), rs2, vm 356class VStridedSegmentLoad<bits<3> nf, RISCVWidth width, string opcodestr> 357 : RVInstVLS<nf, width.Value{3}, width.Value{2-0}, 358 (outs VR:$vd), 359 (ins GPRMemZeroOffset:$rs1, GPR:$rs2, VMaskOp:$vm), opcodestr, 360 "$vd, $rs1, $rs2$vm">; 361 362// indexed segment load vd, (rs1), vs2, vm 363class VIndexedSegmentLoad<bits<3> nf, RISCVMOP mop, RISCVWidth width, 364 string opcodestr> 365 : RVInstVLX<nf, width.Value{3}, mop, width.Value{2-0}, 366 (outs VR:$vd), 367 (ins GPRMemZeroOffset:$rs1, VR:$vs2, VMaskOp:$vm), opcodestr, 368 "$vd, $rs1, $vs2$vm">; 369} // hasSideEffects = 0, mayLoad = 1, mayStore = 0 370 371let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in { 372// unit-stride store vd, vs3, (rs1), vm 373class VUnitStrideStore<RISCVWidth width, string opcodestr> 374 : RVInstVSU<0b000, width.Value{3}, SUMOPUnitStride, width.Value{2-0}, 375 (outs), (ins VR:$vs3, GPRMemZeroOffset:$rs1, VMaskOp:$vm), opcodestr, 376 "$vs3, ${rs1}$vm">; 377 378let vm = 1 in { 379// vs<nf>r.v vd, (rs1) 380class VWholeStore<bits<3> nf, string opcodestr, RegisterClass VRC> 381 : RVInstVSU<nf, 0, SUMOPUnitStrideWholeReg, 382 0b000, (outs), (ins VRC:$vs3, GPRMemZeroOffset:$rs1), 383 opcodestr, "$vs3, $rs1"> { 384 let Uses = []; 385} 386 387// unit-stride mask store vd, vs3, (rs1) 388class VUnitStrideStoreMask<string opcodestr> 389 : RVInstVSU<0b000, LSWidth8.Value{3}, SUMOPUnitStrideMask, LSWidth8.Value{2-0}, 390 (outs), (ins VR:$vs3, GPRMemZeroOffset:$rs1), opcodestr, 391 "$vs3, $rs1">; 392} // vm = 1 393 394// strided store vd, vs3, (rs1), rs2, vm 395class VStridedStore<RISCVWidth width, string opcodestr> 396 : RVInstVSS<0b000, width.Value{3}, width.Value{2-0}, (outs), 397 (ins VR:$vs3, GPRMemZeroOffset:$rs1, GPR:$rs2, VMaskOp:$vm), 398 opcodestr, "$vs3, $rs1, $rs2$vm">; 399 400// indexed store vd, vs3, (rs1), vs2, vm 401class VIndexedStore<RISCVMOP mop, RISCVWidth width, string opcodestr> 402 : RVInstVSX<0b000, width.Value{3}, mop, width.Value{2-0}, (outs), 403 (ins VR:$vs3, GPRMemZeroOffset:$rs1, VR:$vs2, VMaskOp:$vm), 404 opcodestr, "$vs3, $rs1, $vs2$vm">; 405 406// segment store vd, vs3, (rs1), vm 407class VUnitStrideSegmentStore<bits<3> nf, RISCVWidth width, string opcodestr> 408 : RVInstVSU<nf, width.Value{3}, SUMOPUnitStride, width.Value{2-0}, 409 (outs), (ins VR:$vs3, GPRMemZeroOffset:$rs1, VMaskOp:$vm), opcodestr, 410 "$vs3, ${rs1}$vm">; 411 412// segment store vd, vs3, (rs1), rs2, vm 413class VStridedSegmentStore<bits<3> nf, RISCVWidth width, string opcodestr> 414 : RVInstVSS<nf, width.Value{3}, width.Value{2-0}, (outs), 415 (ins VR:$vs3, GPRMemZeroOffset:$rs1, GPR:$rs2, VMaskOp:$vm), 416 opcodestr, "$vs3, $rs1, $rs2$vm">; 417 418// segment store vd, vs3, (rs1), vs2, vm 419class VIndexedSegmentStore<bits<3> nf, RISCVMOP mop, RISCVWidth width, 420 string opcodestr> 421 : RVInstVSX<nf, width.Value{3}, mop, width.Value{2-0}, (outs), 422 (ins VR:$vs3, GPRMemZeroOffset:$rs1, VR:$vs2, VMaskOp:$vm), 423 opcodestr, "$vs3, $rs1, $vs2$vm">; 424} // hasSideEffects = 0, mayLoad = 0, mayStore = 1 425 426let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { 427// op vd, vs2, vs1, vm 428class VALUVV<bits<6> funct6, RISCVVFormat opv, string opcodestr> 429 : RVInstVV<funct6, opv, (outs VR:$vd), 430 (ins VR:$vs2, VR:$vs1, VMaskOp:$vm), 431 opcodestr, "$vd, $vs2, $vs1$vm">; 432 433// op vd, vs2, vs1, v0 (without mask, use v0 as carry input) 434class VALUmVV<bits<6> funct6, RISCVVFormat opv, string opcodestr> 435 : RVInstVV<funct6, opv, (outs VR:$vd), 436 (ins VR:$vs2, VR:$vs1, VMV0:$v0), 437 opcodestr, "$vd, $vs2, $vs1, v0"> { 438 let vm = 0; 439} 440 441// op vd, vs1, vs2, vm (reverse the order of vs1 and vs2) 442class VALUrVV<bits<6> funct6, RISCVVFormat opv, string opcodestr, 443 bit EarlyClobber = 0> 444 : RVInstVV<funct6, opv, (outs VR:$vd_wb), 445 (ins VR:$vd, VR:$vs1, VR:$vs2, VMaskOp:$vm), 446 opcodestr, "$vd, $vs1, $vs2$vm"> { 447 let Constraints = !if(EarlyClobber, "@earlyclobber $vd_wb, $vd = $vd_wb", 448 "$vd = $vd_wb"); 449} 450 451// op vd, vs2, vs1 452class VALUVVNoVm<bits<6> funct6, RISCVVFormat opv, string opcodestr> 453 : RVInstVV<funct6, opv, (outs VR:$vd), 454 (ins VR:$vs2, VR:$vs1), 455 opcodestr, "$vd, $vs2, $vs1"> { 456 let vm = 1; 457} 458 459// op vd, vs2, rs1, vm 460class VALUVX<bits<6> funct6, RISCVVFormat opv, string opcodestr> 461 : RVInstVX<funct6, opv, (outs VR:$vd), 462 (ins VR:$vs2, GPR:$rs1, VMaskOp:$vm), 463 opcodestr, "$vd, $vs2, $rs1$vm">; 464 465// op vd, vs2, rs1, v0 (without mask, use v0 as carry input) 466class VALUmVX<bits<6> funct6, RISCVVFormat opv, string opcodestr> 467 : RVInstVX<funct6, opv, (outs VR:$vd), 468 (ins VR:$vs2, GPR:$rs1, VMV0:$v0), 469 opcodestr, "$vd, $vs2, $rs1, v0"> { 470 let vm = 0; 471} 472 473// op vd, rs1, vs2, vm (reverse the order of rs1 and vs2) 474class VALUrVX<bits<6> funct6, RISCVVFormat opv, string opcodestr, 475 bit EarlyClobber = 0> 476 : RVInstVX<funct6, opv, (outs VR:$vd_wb), 477 (ins VR:$vd, GPR:$rs1, VR:$vs2, VMaskOp:$vm), 478 opcodestr, "$vd, $rs1, $vs2$vm"> { 479 let Constraints = !if(EarlyClobber, "@earlyclobber $vd_wb, $vd = $vd_wb", 480 "$vd = $vd_wb"); 481} 482 483// op vd, vs1, vs2 484class VALUVXNoVm<bits<6> funct6, RISCVVFormat opv, string opcodestr> 485 : RVInstVX<funct6, opv, (outs VR:$vd), 486 (ins VR:$vs2, GPR:$rs1), 487 opcodestr, "$vd, $vs2, $rs1"> { 488 let vm = 1; 489} 490 491// op vd, vs2, imm, vm 492class VALUVI<bits<6> funct6, string opcodestr, Operand optype = simm5> 493 : RVInstIVI<funct6, (outs VR:$vd), 494 (ins VR:$vs2, optype:$imm, VMaskOp:$vm), 495 opcodestr, "$vd, $vs2, $imm$vm">; 496 497// op vd, vs2, imm, v0 (without mask, use v0 as carry input) 498class VALUmVI<bits<6> funct6, string opcodestr, Operand optype = simm5> 499 : RVInstIVI<funct6, (outs VR:$vd), 500 (ins VR:$vs2, optype:$imm, VMV0:$v0), 501 opcodestr, "$vd, $vs2, $imm, v0"> { 502 let vm = 0; 503} 504 505// op vd, vs2, imm, vm 506class VALUVINoVm<bits<6> funct6, string opcodestr, Operand optype = simm5> 507 : RVInstIVI<funct6, (outs VR:$vd), 508 (ins VR:$vs2, optype:$imm), 509 opcodestr, "$vd, $vs2, $imm"> { 510 let vm = 1; 511} 512 513// op vd, vs2, rs1, vm (Float) 514class VALUVF<bits<6> funct6, RISCVVFormat opv, string opcodestr> 515 : RVInstVX<funct6, opv, (outs VR:$vd), 516 (ins VR:$vs2, FPR32:$rs1, VMaskOp:$vm), 517 opcodestr, "$vd, $vs2, $rs1$vm">; 518 519// op vd, rs1, vs2, vm (Float) (with mask, reverse the order of rs1 and vs2) 520class VALUrVF<bits<6> funct6, RISCVVFormat opv, string opcodestr, 521 bit EarlyClobber = 0> 522 : RVInstVX<funct6, opv, (outs VR:$vd_wb), 523 (ins VR:$vd, FPR32:$rs1, VR:$vs2, VMaskOp:$vm), 524 opcodestr, "$vd, $rs1, $vs2$vm"> { 525 let Constraints = !if(EarlyClobber, "@earlyclobber $vd_wb, $vd = $vd_wb", 526 "$vd = $vd_wb"); 527} 528 529// op vd, vs2, vm (use vs1 as instruction encoding) 530class VALUVs2<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, string opcodestr> 531 : RVInstV<funct6, vs1, opv, (outs VR:$vd), 532 (ins VR:$vs2, VMaskOp:$vm), 533 opcodestr, "$vd, $vs2$vm">; 534} // hasSideEffects = 0, mayLoad = 0, mayStore = 0 535 536//===----------------------------------------------------------------------===// 537// Combination of instruction classes. 538// Use these multiclasses to define instructions more easily. 539//===----------------------------------------------------------------------===// 540 541multiclass VIndexLoadStore<int eew> { 542 defvar w = !cast<RISCVWidth>("LSWidth" # eew); 543 544 def VLUXEI # eew # _V : 545 VIndexedLoad<MOPLDIndexedUnord, w, "vluxei" # eew # ".v">, 546 VLXSchedMC<eew, isOrdered=0>; 547 def VLOXEI # eew # _V : 548 VIndexedLoad<MOPLDIndexedOrder, w, "vloxei" # eew # ".v">, 549 VLXSchedMC<eew, isOrdered=1>; 550 551 def VSUXEI # eew # _V : 552 VIndexedStore<MOPSTIndexedUnord, w, "vsuxei" # eew # ".v">, 553 VSXSchedMC<eew, isOrdered=0>; 554 def VSOXEI # eew # _V : 555 VIndexedStore<MOPSTIndexedOrder, w, "vsoxei" # eew # ".v">, 556 VSXSchedMC<eew, isOrdered=1>; 557} 558 559multiclass VALU_IV_V<string opcodestr, bits<6> funct6> { 560 def V : VALUVV<funct6, OPIVV, opcodestr # ".vv">, 561 SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV">; 562} 563 564multiclass VALU_IV_X<string opcodestr, bits<6> funct6> { 565 def X : VALUVX<funct6, OPIVX, opcodestr # ".vx">, 566 SchedBinaryMC<"WriteVIALUX", "ReadVIALUV", "ReadVIALUX">; 567} 568 569multiclass VALU_IV_I<string opcodestr, bits<6> funct6> { 570 def I : VALUVI<funct6, opcodestr # ".vi">, 571 SchedUnaryMC<"WriteVIALUI", "ReadVIALUV">; 572} 573 574multiclass VALU_IV_V_X_I<string opcodestr, bits<6> funct6> 575 : VALU_IV_V<opcodestr, funct6>, 576 VALU_IV_X<opcodestr, funct6>, 577 VALU_IV_I<opcodestr, funct6>; 578 579multiclass VALU_IV_V_X<string opcodestr, bits<6> funct6> 580 : VALU_IV_V<opcodestr, funct6>, 581 VALU_IV_X<opcodestr, funct6>; 582 583multiclass VALU_IV_X_I<string opcodestr, bits<6> funct6> 584 : VALU_IV_X<opcodestr, funct6>, 585 VALU_IV_I<opcodestr, funct6>; 586 587multiclass VALU_MV_V_X<string opcodestr, bits<6> funct6, string vw> { 588 def V : VALUVV<funct6, OPMVV, opcodestr # "." # vw # "v">, 589 SchedBinaryMC<"WriteVIWALUV", "ReadVIWALUV", "ReadVIWALUV">; 590 def X : VALUVX<funct6, OPMVX, opcodestr # "." # vw # "x">, 591 SchedBinaryMC<"WriteVIWALUX", "ReadVIWALUV", "ReadVIWALUX">; 592} 593 594multiclass VMAC_MV_V_X<string opcodestr, bits<6> funct6> { 595 def V : VALUrVV<funct6, OPMVV, opcodestr # ".vv">, 596 SchedTernaryMC<"WriteVIMulAddV", "ReadVIMulAddV", "ReadVIMulAddV", 597 "ReadVIMulAddV">; 598 def X : VALUrVX<funct6, OPMVX, opcodestr # ".vx">, 599 SchedTernaryMC<"WriteVIMulAddX", "ReadVIMulAddV", "ReadVIMulAddX", 600 "ReadVIMulAddV">; 601} 602 603multiclass VWMAC_MV_X<string opcodestr, bits<6> funct6> { 604 let RVVConstraint = WidenV in 605 def X : VALUrVX<funct6, OPMVX, opcodestr # ".vx">, 606 SchedTernaryMC<"WriteVIWMulAddX", "ReadVIWMulAddV", "ReadVIWMulAddX", 607 "ReadVIWMulAddV">; 608} 609 610multiclass VWMAC_MV_V_X<string opcodestr, bits<6> funct6> 611 : VWMAC_MV_X<opcodestr, funct6> { 612 let RVVConstraint = WidenV in 613 def V : VALUrVV<funct6, OPMVV, opcodestr # ".vv", EarlyClobber=1>, 614 SchedTernaryMC<"WriteVIWMulAddV", "ReadVIWMulAddV", "ReadVIWMulAddV", 615 "ReadVIWMulAddV">; 616} 617 618multiclass VALU_MV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> { 619 def "" : VALUVs2<funct6, vs1, OPMVV, opcodestr>, 620 SchedUnaryMC<"WriteVExtV", "ReadVExtV">; 621} 622 623multiclass VMRG_IV_V_X_I<string opcodestr, bits<6> funct6> { 624 def VM : VALUmVV<funct6, OPIVV, opcodestr # ".vvm">, 625 SchedBinaryMC<"WriteVIMergeV", "ReadVIMergeV", "ReadVIMergeV">; 626 def XM : VALUmVX<funct6, OPIVX, opcodestr # ".vxm">, 627 SchedBinaryMC<"WriteVIMergeX", "ReadVIMergeV", "ReadVIMergeX">; 628 def IM : VALUmVI<funct6, opcodestr # ".vim">, 629 SchedUnaryMC<"WriteVIMergeI", "ReadVIMergeV">; 630} 631 632multiclass VALUm_IV_V_X<string opcodestr, bits<6> funct6> { 633 def VM : VALUmVV<funct6, OPIVV, opcodestr # ".vvm">, 634 SchedBinaryMC<"WriteVICALUV", "ReadVICALUV", "ReadVICALUV">; 635 def XM : VALUmVX<funct6, OPIVX, opcodestr # ".vxm">, 636 SchedBinaryMC<"WriteVICALUX", "ReadVICALUV", "ReadVICALUX">; 637} 638 639multiclass VALUm_IV_V_X_I<string opcodestr, bits<6> funct6> 640 : VALUm_IV_V_X<opcodestr, funct6> { 641 def IM : VALUmVI<funct6, opcodestr # ".vim">, 642 SchedUnaryMC<"WriteVICALUI", "ReadVICALUV">; 643} 644 645multiclass VALUNoVm_IV_V_X<string opcodestr, bits<6> funct6> { 646 def V : VALUVVNoVm<funct6, OPIVV, opcodestr # ".vv">, 647 SchedBinaryMC<"WriteVICALUV", "ReadVICALUV", "ReadVICALUV", 648 forceMasked=0>; 649 def X : VALUVXNoVm<funct6, OPIVX, opcodestr # ".vx">, 650 SchedBinaryMC<"WriteVICALUX", "ReadVICALUV", "ReadVICALUX", 651 forceMasked=0>; 652} 653 654multiclass VALUNoVm_IV_V_X_I<string opcodestr, bits<6> funct6> 655 : VALUNoVm_IV_V_X<opcodestr, funct6> { 656 def I : VALUVINoVm<funct6, opcodestr # ".vi">, 657 SchedUnaryMC<"WriteVICALUI", "ReadVICALUV", forceMasked=0>; 658} 659 660multiclass VALU_FV_F<string opcodestr, bits<6> funct6> { 661 def F : VALUVF<funct6, OPFVF, opcodestr # ".vf">, 662 SchedBinaryMC<"WriteVFALUF", "ReadVFALUV", "ReadVFALUF">; 663} 664 665multiclass VALU_FV_V_F<string opcodestr, bits<6> funct6> 666 : VALU_FV_F<opcodestr, funct6> { 667 def V : VALUVV<funct6, OPFVV, opcodestr # ".vv">, 668 SchedBinaryMC<"WriteVFALUV", "ReadVFALUV", "ReadVFALUV">; 669} 670 671multiclass VWALU_FV_V_F<string opcodestr, bits<6> funct6, string vw> { 672 def V : VALUVV<funct6, OPFVV, opcodestr # "." # vw # "v">, 673 SchedBinaryMC<"WriteVFWALUV", "ReadVFWALUV", "ReadVFWALUV">; 674 def F : VALUVF<funct6, OPFVF, opcodestr # "." # vw # "f">, 675 SchedBinaryMC<"WriteVFWALUF", "ReadVFWALUV", "ReadVFWALUF">; 676} 677 678multiclass VMUL_FV_V_F<string opcodestr, bits<6> funct6> { 679 def V : VALUVV<funct6, OPFVV, opcodestr # ".vv">, 680 SchedBinaryMC<"WriteVFMulV", "ReadVFMulV", "ReadVFMulV">; 681 def F : VALUVF<funct6, OPFVF, opcodestr # ".vf">, 682 SchedBinaryMC<"WriteVFMulF", "ReadVFMulV", "ReadVFMulF">; 683} 684 685multiclass VDIV_FV_F<string opcodestr, bits<6> funct6> { 686 def F : VALUVF<funct6, OPFVF, opcodestr # ".vf">, 687 SchedBinaryMC<"WriteVFDivF", "ReadVFDivV", "ReadVFDivF">; 688} 689 690multiclass VDIV_FV_V_F<string opcodestr, bits<6> funct6> 691 : VDIV_FV_F<opcodestr, funct6> { 692 def V : VALUVV<funct6, OPFVV, opcodestr # ".vv">, 693 SchedBinaryMC<"WriteVFDivV", "ReadVFDivV", "ReadVFDivV">; 694} 695 696multiclass VWMUL_FV_V_F<string opcodestr, bits<6> funct6> { 697 def V : VALUVV<funct6, OPFVV, opcodestr # ".vv">, 698 SchedBinaryMC<"WriteVFWMulV", "ReadVFWMulV", "ReadVFWMulV">; 699 def F : VALUVF<funct6, OPFVF, opcodestr # ".vf">, 700 SchedBinaryMC<"WriteVFWMulF", "ReadVFWMulV", "ReadVFWMulF">; 701} 702 703multiclass VMAC_FV_V_F<string opcodestr, bits<6> funct6> { 704 def V : VALUrVV<funct6, OPFVV, opcodestr # ".vv">, 705 SchedTernaryMC<"WriteVFMulAddV", "ReadVFMulAddV", "ReadVFMulAddV", 706 "ReadVFMulAddV">; 707 def F : VALUrVF<funct6, OPFVF, opcodestr # ".vf">, 708 SchedTernaryMC<"WriteVFMulAddF", "ReadVFMulAddV", "ReadVFMulAddF", 709 "ReadVFMulAddV">; 710} 711 712multiclass VWMAC_FV_V_F<string opcodestr, bits<6> funct6> { 713 let RVVConstraint = WidenV in { 714 def V : VALUrVV<funct6, OPFVV, opcodestr # ".vv", EarlyClobber=1>, 715 SchedTernaryMC<"WriteVFWMulAddV", "ReadVFWMulAddV", "ReadVFWMulAddV", 716 "ReadVFWMulAddV">; 717 def F : VALUrVF<funct6, OPFVF, opcodestr # ".vf", EarlyClobber=1>, 718 SchedTernaryMC<"WriteVFWMulAddF", "ReadVFWMulAddV", "ReadVFWMulAddF", 719 "ReadVFWMulAddV">; 720 } 721} 722 723multiclass VSQR_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> { 724 def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>, 725 SchedUnaryMC<"WriteVFSqrtV", "ReadVFSqrtV">; 726} 727 728multiclass VRCP_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> { 729 def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>, 730 SchedUnaryMC<"WriteVFRecpV", "ReadVFRecpV">; 731} 732 733multiclass VMINMAX_FV_V_F<string opcodestr, bits<6> funct6> { 734 def V : VALUVV<funct6, OPFVV, opcodestr # ".vv">, 735 SchedBinaryMC<"WriteVFMinMaxV", "ReadVFMinMaxV", "ReadVFMinMaxV">; 736 def F : VALUVF<funct6, OPFVF, opcodestr # ".vf">, 737 SchedBinaryMC<"WriteVFMinMaxF", "ReadVFMinMaxV", "ReadVFMinMaxF">; 738} 739 740multiclass VCMP_FV_F<string opcodestr, bits<6> funct6> { 741 def F : VALUVF<funct6, OPFVF, opcodestr # ".vf">, 742 SchedBinaryMC<"WriteVFCmpF", "ReadVFCmpV", "ReadVFCmpF">; 743} 744 745multiclass VCMP_FV_V_F<string opcodestr, bits<6> funct6> 746 : VCMP_FV_F<opcodestr, funct6> { 747 def V : VALUVV<funct6, OPFVV, opcodestr # ".vv">, 748 SchedBinaryMC<"WriteVFCmpV", "ReadVFCmpV", "ReadVFCmpV">; 749} 750 751multiclass VSGNJ_FV_V_F<string opcodestr, bits<6> funct6> { 752 def V : VALUVV<funct6, OPFVV, opcodestr # ".vv">, 753 SchedBinaryMC<"WriteVFSgnjV", "ReadVFSgnjV", "ReadVFSgnjV">; 754 def F : VALUVF<funct6, OPFVF, opcodestr # ".vf">, 755 SchedBinaryMC<"WriteVFSgnjF", "ReadVFSgnjV", "ReadVFSgnjF">; 756} 757 758multiclass VCLS_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> { 759 def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>, 760 SchedUnaryMC<"WriteVFClassV", "ReadVFClassV">; 761} 762 763multiclass VCVTF_IV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> { 764 def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>, 765 SchedUnaryMC<"WriteVFCvtIToFV", "ReadVFCvtIToFV">; 766} 767 768multiclass VCVTI_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> { 769 def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>, 770 SchedUnaryMC<"WriteVFCvtFToIV", "ReadVFCvtFToIV">; 771} 772 773multiclass VWCVTF_IV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> { 774 def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>, 775 SchedUnaryMC<"WriteVFWCvtIToFV", "ReadVFWCvtIToFV">; 776} 777 778multiclass VWCVTI_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> { 779 def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>, 780 SchedUnaryMC<"WriteVFWCvtFToIV", "ReadVFWCvtFToIV">; 781} 782 783multiclass VWCVTF_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> { 784 def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>, 785 SchedUnaryMC<"WriteVFWCvtFToFV", "ReadVFWCvtFToFV">; 786} 787 788multiclass VNCVTF_IV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> { 789 def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>, 790 SchedUnaryMC<"WriteVFNCvtIToFV", "ReadVFNCvtIToFV">; 791} 792 793multiclass VNCVTI_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> { 794 def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>, 795 SchedUnaryMC<"WriteVFNCvtFToIV", "ReadVFNCvtFToIV">; 796} 797 798multiclass VNCVTF_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> { 799 def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>, 800 SchedUnaryMC<"WriteVFNCvtFToFV", "ReadVFNCvtFToFV">; 801} 802 803multiclass VRED_MV_V<string opcodestr, bits<6> funct6> { 804 def _VS : VALUVV<funct6, OPMVV, opcodestr # ".vs">, 805 SchedReductionMC<"WriteVIRedV_From", "ReadVIRedV", "ReadVIRedV0">; 806} 807 808multiclass VREDMINMAX_MV_V<string opcodestr, bits<6> funct6> { 809 def _VS : VALUVV<funct6, OPMVV, opcodestr # ".vs">, 810 SchedReductionMC<"WriteVIRedMinMaxV_From", "ReadVIRedV", "ReadVIRedV0">; 811} 812 813multiclass VWRED_IV_V<string opcodestr, bits<6> funct6> { 814 def _VS : VALUVV<funct6, OPIVV, opcodestr # ".vs">, 815 SchedReductionMC<"WriteVIWRedV_From", "ReadVIWRedV", "ReadVIWRedV0">; 816} 817 818multiclass VRED_FV_V<string opcodestr, bits<6> funct6> { 819 def _VS : VALUVV<funct6, OPFVV, opcodestr # ".vs">, 820 SchedReductionMC<"WriteVFRedV_From", "ReadVFRedV", "ReadVFRedV0">; 821} 822 823multiclass VREDMINMAX_FV_V<string opcodestr, bits<6> funct6> { 824 def _VS : VALUVV<funct6, OPFVV, opcodestr # ".vs">, 825 SchedReductionMC<"WriteVFRedMinMaxV_From", "ReadVFRedV", "ReadVFRedV0">; 826} 827 828multiclass VREDO_FV_V<string opcodestr, bits<6> funct6> { 829 def _VS : VALUVV<funct6, OPFVV, opcodestr # ".vs">, 830 SchedReductionMC<"WriteVFRedOV_From", "ReadVFRedOV", "ReadVFRedOV0">; 831} 832 833multiclass VWRED_FV_V<string opcodestr, bits<6> funct6> { 834 def _VS : VALUVV<funct6, OPFVV, opcodestr # ".vs">, 835 SchedReductionMC<"WriteVFWRedV_From", "ReadVFWRedV", "ReadVFWRedV0">; 836} 837 838multiclass VWREDO_FV_V<string opcodestr, bits<6> funct6> { 839 def _VS : VALUVV<funct6, OPFVV, opcodestr # ".vs">, 840 SchedReductionMC<"WriteVFWRedOV_From", "ReadVFWRedOV", "ReadVFWRedOV0">; 841} 842 843multiclass VMALU_MV_Mask<string opcodestr, bits<6> funct6, string vm = "v"> { 844 def M : VALUVVNoVm<funct6, OPMVV, opcodestr #"." #vm #"m">, 845 SchedBinaryMC<"WriteVMALUV", "ReadVMALUV", "ReadVMALUV", 846 forceMasked=0>; 847} 848 849multiclass VMSFS_MV_V<string opcodestr, bits<6> funct6, bits<5> vs1> { 850 def "" : VALUVs2<funct6, vs1, OPMVV, opcodestr>, 851 SchedUnaryMC<"WriteVMSFSV", "ReadVMSFSV">; 852} 853 854multiclass VIOTA_MV_V<string opcodestr, bits<6> funct6, bits<5> vs1> { 855 def "" : VALUVs2<funct6, vs1, OPMVV, opcodestr>, 856 SchedUnaryMC<"WriteVIotaV", "ReadVIotaV">; 857} 858 859multiclass VSHT_IV_V_X_I<string opcodestr, bits<6> funct6> { 860 def V : VALUVV<funct6, OPIVV, opcodestr # ".vv">, 861 SchedBinaryMC<"WriteVShiftV", "ReadVShiftV", "ReadVShiftV">; 862 def X : VALUVX<funct6, OPIVX, opcodestr # ".vx">, 863 SchedBinaryMC<"WriteVShiftX", "ReadVShiftV", "ReadVShiftX">; 864 def I : VALUVI<funct6, opcodestr # ".vi", uimm5>, 865 SchedUnaryMC<"WriteVShiftI", "ReadVShiftV">; 866} 867 868multiclass VNSHT_IV_V_X_I<string opcodestr, bits<6> funct6> { 869 def V : VALUVV<funct6, OPIVV, opcodestr # ".wv">, 870 SchedBinaryMC<"WriteVNShiftV", "ReadVNShiftV", "ReadVNShiftV">; 871 def X : VALUVX<funct6, OPIVX, opcodestr # ".wx">, 872 SchedBinaryMC<"WriteVNShiftX", "ReadVNShiftV", "ReadVNShiftX">; 873 def I : VALUVI<funct6, opcodestr # ".wi", uimm5>, 874 SchedUnaryMC<"WriteVNShiftI", "ReadVNShiftV">; 875} 876 877multiclass VMINMAX_IV_V_X<string opcodestr, bits<6> funct6> { 878 def V : VALUVV<funct6, OPIVV, opcodestr # ".vv">, 879 SchedBinaryMC<"WriteVIMinMaxV", "ReadVIMinMaxV", "ReadVIMinMaxV">; 880 def X : VALUVX<funct6, OPIVX, opcodestr # ".vx">, 881 SchedBinaryMC<"WriteVIMinMaxX", "ReadVIMinMaxV", "ReadVIMinMaxX">; 882} 883 884multiclass VCMP_IV_V<string opcodestr, bits<6> funct6> { 885 def V : VALUVV<funct6, OPIVV, opcodestr # ".vv">, 886 SchedBinaryMC<"WriteVICmpV", "ReadVICmpV", "ReadVICmpV">; 887} 888 889multiclass VCMP_IV_X<string opcodestr, bits<6> funct6> { 890 def X : VALUVX<funct6, OPIVX, opcodestr # ".vx">, 891 SchedBinaryMC<"WriteVICmpX", "ReadVICmpV", "ReadVICmpX">; 892} 893 894multiclass VCMP_IV_I<string opcodestr, bits<6> funct6> { 895 def I : VALUVI<funct6, opcodestr # ".vi">, 896 SchedUnaryMC<"WriteVICmpI", "ReadVICmpV">; 897} 898 899multiclass VCMP_IV_V_X_I<string opcodestr, bits<6> funct6> 900 : VCMP_IV_V<opcodestr, funct6>, 901 VCMP_IV_X<opcodestr, funct6>, 902 VCMP_IV_I<opcodestr, funct6>; 903 904multiclass VCMP_IV_X_I<string opcodestr, bits<6> funct6> 905 : VCMP_IV_X<opcodestr, funct6>, 906 VCMP_IV_I<opcodestr, funct6>; 907 908multiclass VCMP_IV_V_X<string opcodestr, bits<6> funct6> 909 : VCMP_IV_V<opcodestr, funct6>, 910 VCMP_IV_X<opcodestr, funct6>; 911 912multiclass VMUL_MV_V_X<string opcodestr, bits<6> funct6> { 913 def V : VALUVV<funct6, OPMVV, opcodestr # ".vv">, 914 SchedBinaryMC<"WriteVIMulV", "ReadVIMulV", "ReadVIMulV">; 915 def X : VALUVX<funct6, OPMVX, opcodestr # ".vx">, 916 SchedBinaryMC<"WriteVIMulX", "ReadVIMulV", "ReadVIMulX">; 917} 918 919multiclass VWMUL_MV_V_X<string opcodestr, bits<6> funct6> { 920 def V : VALUVV<funct6, OPMVV, opcodestr # ".vv">, 921 SchedBinaryMC<"WriteVIWMulV", "ReadVIWMulV", "ReadVIWMulV">; 922 def X : VALUVX<funct6, OPMVX, opcodestr # ".vx">, 923 SchedBinaryMC<"WriteVIWMulX", "ReadVIWMulV", "ReadVIWMulX">; 924} 925 926multiclass VDIV_MV_V_X<string opcodestr, bits<6> funct6> { 927 def V : VALUVV<funct6, OPMVV, opcodestr # ".vv">, 928 SchedBinaryMC<"WriteVIDivV", "ReadVIDivV", "ReadVIDivV">; 929 def X : VALUVX<funct6, OPMVX, opcodestr # ".vx">, 930 SchedBinaryMC<"WriteVIDivX", "ReadVIDivV", "ReadVIDivX">; 931} 932 933multiclass VSALU_IV_V_X<string opcodestr, bits<6> funct6> { 934 def V : VALUVV<funct6, OPIVV, opcodestr # ".vv">, 935 SchedBinaryMC<"WriteVSALUV", "ReadVSALUV", "ReadVSALUV">; 936 def X : VALUVX<funct6, OPIVX, opcodestr # ".vx">, 937 SchedBinaryMC<"WriteVSALUX", "ReadVSALUV", "ReadVSALUX">; 938} 939 940multiclass VSALU_IV_V_X_I<string opcodestr, bits<6> funct6> 941 : VSALU_IV_V_X<opcodestr, funct6> { 942 def I : VALUVI<funct6, opcodestr # ".vi">, 943 SchedUnaryMC<"WriteVSALUI", "ReadVSALUV">; 944} 945 946multiclass VAALU_MV_V_X<string opcodestr, bits<6> funct6> { 947 def V : VALUVV<funct6, OPMVV, opcodestr # ".vv">, 948 SchedBinaryMC<"WriteVAALUV", "ReadVAALUV", "ReadVAALUV">; 949 def X : VALUVX<funct6, OPMVX, opcodestr # ".vx">, 950 SchedBinaryMC<"WriteVAALUX", "ReadVAALUV", "ReadVAALUX">; 951} 952 953multiclass VSMUL_IV_V_X<string opcodestr, bits<6> funct6> { 954 def V : VALUVV<funct6, OPIVV, opcodestr # ".vv">, 955 SchedBinaryMC<"WriteVSMulV", "ReadVSMulV", "ReadVSMulV">; 956 def X : VALUVX<funct6, OPIVX, opcodestr # ".vx">, 957 SchedBinaryMC<"WriteVSMulX", "ReadVSMulV", "ReadVSMulX">; 958} 959 960multiclass VSSHF_IV_V_X_I<string opcodestr, bits<6> funct6> { 961 def V : VALUVV<funct6, OPIVV, opcodestr # ".vv">, 962 SchedBinaryMC<"WriteVSShiftV", "ReadVSShiftV", "ReadVSShiftV">; 963 def X : VALUVX<funct6, OPIVX, opcodestr # ".vx">, 964 SchedBinaryMC<"WriteVSShiftX", "ReadVSShiftV", "ReadVSShiftX">; 965 def I : VALUVI<funct6, opcodestr # ".vi", uimm5>, 966 SchedUnaryMC<"WriteVSShiftI", "ReadVSShiftV">; 967} 968 969multiclass VNCLP_IV_V_X_I<string opcodestr, bits<6> funct6> { 970 def V : VALUVV<funct6, OPIVV, opcodestr # ".wv">, 971 SchedBinaryMC<"WriteVNClipV", "ReadVNClipV", "ReadVNClipV">; 972 def X : VALUVX<funct6, OPIVX, opcodestr # ".wx">, 973 SchedBinaryMC<"WriteVNClipX", "ReadVNClipV", "ReadVNClipX">; 974 def I : VALUVI<funct6, opcodestr # ".wi", uimm5>, 975 SchedUnaryMC<"WriteVNClipI", "ReadVNClipV">; 976} 977 978multiclass VSLD_IV_X_I<string opcodestr, bits<6> funct6, bit slidesUp> { 979 // Note: In the future, if VISlideI is also split into VSlideUpI and 980 // VSlideDownI, it'll probably better to use two separate multiclasses. 981 defvar WriteSlideX = !if(slidesUp, "WriteVSlideUpX", "WriteVSlideDownX"); 982 def X : VALUVX<funct6, OPIVX, opcodestr # ".vx">, 983 SchedBinaryMC<WriteSlideX, "ReadVISlideV", "ReadVISlideX">; 984 def I : VALUVI<funct6, opcodestr # ".vi", uimm5>, 985 SchedUnaryMC<"WriteVSlideI", "ReadVISlideV">; 986} 987 988multiclass VSLD1_MV_X<string opcodestr, bits<6> funct6> { 989 def X : VALUVX<funct6, OPMVX, opcodestr # ".vx">, 990 SchedBinaryMC<"WriteVISlide1X", "ReadVISlideV", "ReadVISlideX">; 991} 992 993multiclass VSLD1_FV_F<string opcodestr, bits<6> funct6> { 994 def F : VALUVF<funct6, OPFVF, opcodestr # ".vf">, 995 SchedBinaryMC<"WriteVFSlide1F", "ReadVFSlideV", "ReadVFSlideF">; 996} 997 998multiclass VGTR_IV_V_X_I<string opcodestr, bits<6> funct6> { 999 def V : VALUVV<funct6, OPIVV, opcodestr # ".vv">, 1000 SchedBinaryMC<"WriteVRGatherVV", "ReadVRGatherVV_data", 1001 "ReadVRGatherVV_index">; 1002 def X : VALUVX<funct6, OPIVX, opcodestr # ".vx">, 1003 SchedBinaryMC<"WriteVRGatherVX", "ReadVRGatherVX_data", 1004 "ReadVRGatherVX_index">; 1005 def I : VALUVI<funct6, opcodestr # ".vi", uimm5>, 1006 SchedUnaryMC<"WriteVRGatherVI", "ReadVRGatherVI_data">; 1007} 1008 1009multiclass VCPR_MV_Mask<string opcodestr, bits<6> funct6, string vm = "v"> { 1010 def M : VALUVVNoVm<funct6, OPMVV, opcodestr # "." # vm # "m">, 1011 SchedBinaryMC<"WriteVCompressV", "ReadVCompressV", "ReadVCompressV">; 1012} 1013 1014multiclass VWholeLoadN<int l, bits<3> nf, string opcodestr, RegisterClass VRC> { 1015 defvar w = !cast<RISCVWidth>("LSWidth" # l); 1016 defvar s = !cast<SchedWrite>("WriteVLD" # !add(nf, 1) # "R"); 1017 1018 def E # l # _V : VWholeLoad<nf, w, opcodestr # "e" # l # ".v", VRC>, 1019 Sched<[s, ReadVLDX]>; 1020} 1021 1022//===----------------------------------------------------------------------===// 1023// Instructions 1024//===----------------------------------------------------------------------===// 1025 1026let Predicates = [HasVInstructions] in { 1027let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in { 1028def VSETVLI : RVInstSetVLi<(outs GPR:$rd), (ins GPR:$rs1, VTypeIOp11:$vtypei), 1029 "vsetvli", "$rd, $rs1, $vtypei">, 1030 Sched<[WriteVSETVLI, ReadVSETVLI]>; 1031def VSETIVLI : RVInstSetiVLi<(outs GPR:$rd), (ins uimm5:$uimm, VTypeIOp10:$vtypei), 1032 "vsetivli", "$rd, $uimm, $vtypei">, 1033 Sched<[WriteVSETIVLI]>; 1034 1035def VSETVL : RVInstSetVL<(outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2), 1036 "vsetvl", "$rd, $rs1, $rs2">, 1037 Sched<[WriteVSETVL, ReadVSETVL, ReadVSETVL]>; 1038} // hasSideEffects = 1, mayLoad = 0, mayStore = 0 1039} // Predicates = [HasVInstructions] 1040 1041foreach eew = [8, 16, 32, 64] in { 1042 defvar w = !cast<RISCVWidth>("LSWidth" # eew); 1043 1044 let Predicates = !if(!eq(eew, 64), [HasVInstructionsI64], 1045 [HasVInstructions]) in { 1046 // Vector Unit-Stride Instructions 1047 def VLE#eew#_V : VUnitStrideLoad<w, "vle"#eew#".v">, VLESchedMC; 1048 def VSE#eew#_V : VUnitStrideStore<w, "vse"#eew#".v">, VSESchedMC; 1049 1050 // Vector Unit-Stride Fault-only-First Loads 1051 def VLE#eew#FF_V : VUnitStrideLoadFF<w, "vle"#eew#"ff.v">, VLFSchedMC; 1052 1053 // Vector Strided Instructions 1054 def VLSE#eew#_V : VStridedLoad<w, "vlse"#eew#".v">, VLSSchedMC<eew>; 1055 def VSSE#eew#_V : VStridedStore<w, "vsse"#eew#".v">, VSSSchedMC<eew>; 1056 1057 defm VL1R : VWholeLoadN<eew, 0, "vl1r", VR>; 1058 defm VL2R : VWholeLoadN<eew, 1, "vl2r", VRM2>; 1059 defm VL4R : VWholeLoadN<eew, 3, "vl4r", VRM4>; 1060 defm VL8R : VWholeLoadN<eew, 7, "vl8r", VRM8>; 1061 } 1062 1063 let Predicates = !if(!eq(eew, 64), [IsRV64, HasVInstructionsI64], 1064 [HasVInstructions]) in 1065 defm "" : VIndexLoadStore<eew>; 1066} 1067 1068let Predicates = [HasVInstructions] in { 1069def VLM_V : VUnitStrideLoadMask<"vlm.v">, 1070 Sched<[WriteVLDM_WorstCase, ReadVLDX]>; 1071def VSM_V : VUnitStrideStoreMask<"vsm.v">, 1072 Sched<[WriteVSTM_WorstCase, ReadVSTM_WorstCase, ReadVSTX]>; 1073def : InstAlias<"vle1.v $vd, (${rs1})", 1074 (VLM_V VR:$vd, GPR:$rs1), 0>; 1075def : InstAlias<"vse1.v $vs3, (${rs1})", 1076 (VSM_V VR:$vs3, GPR:$rs1), 0>; 1077 1078def VS1R_V : VWholeStore<0, "vs1r.v", VR>, 1079 Sched<[WriteVST1R, ReadVST1R, ReadVSTX]>; 1080def VS2R_V : VWholeStore<1, "vs2r.v", VRM2>, 1081 Sched<[WriteVST2R, ReadVST2R, ReadVSTX]>; 1082def VS4R_V : VWholeStore<3, "vs4r.v", VRM4>, 1083 Sched<[WriteVST4R, ReadVST4R, ReadVSTX]>; 1084def VS8R_V : VWholeStore<7, "vs8r.v", VRM8>, 1085 Sched<[WriteVST8R, ReadVST8R, ReadVSTX]>; 1086 1087def : InstAlias<"vl1r.v $vd, (${rs1})", (VL1RE8_V VR:$vd, GPR:$rs1)>; 1088def : InstAlias<"vl2r.v $vd, (${rs1})", (VL2RE8_V VRM2:$vd, GPR:$rs1)>; 1089def : InstAlias<"vl4r.v $vd, (${rs1})", (VL4RE8_V VRM4:$vd, GPR:$rs1)>; 1090def : InstAlias<"vl8r.v $vd, (${rs1})", (VL8RE8_V VRM8:$vd, GPR:$rs1)>; 1091} // Predicates = [HasVInstructions] 1092 1093let Predicates = [HasVInstructions] in { 1094// Vector Single-Width Integer Add and Subtract 1095defm VADD_V : VALU_IV_V_X_I<"vadd", 0b000000>; 1096defm VSUB_V : VALU_IV_V_X<"vsub", 0b000010>; 1097defm VRSUB_V : VALU_IV_X_I<"vrsub", 0b000011>; 1098 1099def : InstAlias<"vneg.v $vd, $vs$vm", (VRSUB_VX VR:$vd, VR:$vs, X0, VMaskOp:$vm)>; 1100def : InstAlias<"vneg.v $vd, $vs", (VRSUB_VX VR:$vd, VR:$vs, X0, zero_reg)>; 1101 1102// Vector Widening Integer Add/Subtract 1103// Refer to 11.2 Widening Vector Arithmetic Instructions 1104// The destination vector register group cannot overlap a source vector 1105// register group of a different element width (including the mask register 1106// if masked), otherwise an illegal instruction exception is raised. 1107let Constraints = "@earlyclobber $vd" in { 1108let RVVConstraint = WidenV in { 1109defm VWADDU_V : VALU_MV_V_X<"vwaddu", 0b110000, "v">; 1110defm VWSUBU_V : VALU_MV_V_X<"vwsubu", 0b110010, "v">; 1111defm VWADD_V : VALU_MV_V_X<"vwadd", 0b110001, "v">; 1112defm VWSUB_V : VALU_MV_V_X<"vwsub", 0b110011, "v">; 1113} // RVVConstraint = WidenV 1114// Set earlyclobber for following instructions for second and mask operands. 1115// This has the downside that the earlyclobber constraint is too coarse and 1116// will impose unnecessary restrictions by not allowing the destination to 1117// overlap with the first (wide) operand. 1118let RVVConstraint = WidenW in { 1119defm VWADDU_W : VALU_MV_V_X<"vwaddu", 0b110100, "w">; 1120defm VWSUBU_W : VALU_MV_V_X<"vwsubu", 0b110110, "w">; 1121defm VWADD_W : VALU_MV_V_X<"vwadd", 0b110101, "w">; 1122defm VWSUB_W : VALU_MV_V_X<"vwsub", 0b110111, "w">; 1123} // RVVConstraint = WidenW 1124} // Constraints = "@earlyclobber $vd" 1125 1126def : InstAlias<"vwcvt.x.x.v $vd, $vs$vm", 1127 (VWADD_VX VR:$vd, VR:$vs, X0, VMaskOp:$vm)>; 1128def : InstAlias<"vwcvt.x.x.v $vd, $vs", 1129 (VWADD_VX VR:$vd, VR:$vs, X0, zero_reg)>; 1130def : InstAlias<"vwcvtu.x.x.v $vd, $vs$vm", 1131 (VWADDU_VX VR:$vd, VR:$vs, X0, VMaskOp:$vm)>; 1132def : InstAlias<"vwcvtu.x.x.v $vd, $vs", 1133 (VWADDU_VX VR:$vd, VR:$vs, X0, zero_reg)>; 1134 1135// Vector Integer Extension 1136defm VZEXT_VF8 : VALU_MV_VS2<"vzext.vf8", 0b010010, 0b00010>; 1137defm VSEXT_VF8 : VALU_MV_VS2<"vsext.vf8", 0b010010, 0b00011>; 1138defm VZEXT_VF4 : VALU_MV_VS2<"vzext.vf4", 0b010010, 0b00100>; 1139defm VSEXT_VF4 : VALU_MV_VS2<"vsext.vf4", 0b010010, 0b00101>; 1140defm VZEXT_VF2 : VALU_MV_VS2<"vzext.vf2", 0b010010, 0b00110>; 1141defm VSEXT_VF2 : VALU_MV_VS2<"vsext.vf2", 0b010010, 0b00111>; 1142 1143// Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions 1144defm VADC_V : VALUm_IV_V_X_I<"vadc", 0b010000>; 1145let Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint in { 1146defm VMADC_V : VALUm_IV_V_X_I<"vmadc", 0b010001>; 1147defm VMADC_V : VALUNoVm_IV_V_X_I<"vmadc", 0b010001>; 1148} // Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint 1149defm VSBC_V : VALUm_IV_V_X<"vsbc", 0b010010>; 1150let Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint in { 1151defm VMSBC_V : VALUm_IV_V_X<"vmsbc", 0b010011>; 1152defm VMSBC_V : VALUNoVm_IV_V_X<"vmsbc", 0b010011>; 1153} // Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint 1154 1155// Vector Bitwise Logical Instructions 1156defm VAND_V : VALU_IV_V_X_I<"vand", 0b001001>; 1157defm VOR_V : VALU_IV_V_X_I<"vor", 0b001010>; 1158defm VXOR_V : VALU_IV_V_X_I<"vxor", 0b001011>; 1159 1160def : InstAlias<"vnot.v $vd, $vs$vm", 1161 (VXOR_VI VR:$vd, VR:$vs, -1, VMaskOp:$vm)>; 1162def : InstAlias<"vnot.v $vd, $vs", 1163 (VXOR_VI VR:$vd, VR:$vs, -1, zero_reg)>; 1164 1165// Vector Single-Width Bit Shift Instructions 1166defm VSLL_V : VSHT_IV_V_X_I<"vsll", 0b100101>; 1167defm VSRL_V : VSHT_IV_V_X_I<"vsrl", 0b101000>; 1168defm VSRA_V : VSHT_IV_V_X_I<"vsra", 0b101001>; 1169 1170// Vector Narrowing Integer Right Shift Instructions 1171// Refer to 11.3. Narrowing Vector Arithmetic Instructions 1172// The destination vector register group cannot overlap the first source 1173// vector register group (specified by vs2). The destination vector register 1174// group cannot overlap the mask register if used, unless LMUL=1. 1175let Constraints = "@earlyclobber $vd" in { 1176defm VNSRL_W : VNSHT_IV_V_X_I<"vnsrl", 0b101100>; 1177defm VNSRA_W : VNSHT_IV_V_X_I<"vnsra", 0b101101>; 1178} // Constraints = "@earlyclobber $vd" 1179 1180def : InstAlias<"vncvt.x.x.w $vd, $vs$vm", 1181 (VNSRL_WX VR:$vd, VR:$vs, X0, VMaskOp:$vm)>; 1182def : InstAlias<"vncvt.x.x.w $vd, $vs", 1183 (VNSRL_WX VR:$vd, VR:$vs, X0, zero_reg)>; 1184 1185// Vector Integer Comparison Instructions 1186let RVVConstraint = NoConstraint in { 1187defm VMSEQ_V : VCMP_IV_V_X_I<"vmseq", 0b011000>; 1188defm VMSNE_V : VCMP_IV_V_X_I<"vmsne", 0b011001>; 1189defm VMSLTU_V : VCMP_IV_V_X<"vmsltu", 0b011010>; 1190defm VMSLT_V : VCMP_IV_V_X<"vmslt", 0b011011>; 1191defm VMSLEU_V : VCMP_IV_V_X_I<"vmsleu", 0b011100>; 1192defm VMSLE_V : VCMP_IV_V_X_I<"vmsle", 0b011101>; 1193defm VMSGTU_V : VCMP_IV_X_I<"vmsgtu", 0b011110>; 1194defm VMSGT_V : VCMP_IV_X_I<"vmsgt", 0b011111>; 1195} // RVVConstraint = NoConstraint 1196 1197def : InstAlias<"vmsgtu.vv $vd, $va, $vb$vm", 1198 (VMSLTU_VV VR:$vd, VR:$vb, VR:$va, VMaskOp:$vm), 0>; 1199def : InstAlias<"vmsgt.vv $vd, $va, $vb$vm", 1200 (VMSLT_VV VR:$vd, VR:$vb, VR:$va, VMaskOp:$vm), 0>; 1201def : InstAlias<"vmsgeu.vv $vd, $va, $vb$vm", 1202 (VMSLEU_VV VR:$vd, VR:$vb, VR:$va, VMaskOp:$vm), 0>; 1203def : InstAlias<"vmsge.vv $vd, $va, $vb$vm", 1204 (VMSLE_VV VR:$vd, VR:$vb, VR:$va, VMaskOp:$vm), 0>; 1205 1206let isCodeGenOnly = 0, isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 0, 1207 mayStore = 0 in { 1208// For unsigned comparisons we need to special case 0 immediate to maintain 1209// the always true/false semantics we would invert if we just decremented the 1210// immediate like we do for signed. To match the GNU assembler we will use 1211// vmseq/vmsne.vv with the same register for both operands which we can't do 1212// from an InstAlias. 1213def PseudoVMSGEU_VI : Pseudo<(outs VR:$vd), 1214 (ins VR:$vs2, simm5_plus1:$imm, VMaskOp:$vm), 1215 [], "vmsgeu.vi", "$vd, $vs2, $imm$vm">; 1216def PseudoVMSLTU_VI : Pseudo<(outs VR:$vd), 1217 (ins VR:$vs2, simm5_plus1:$imm, VMaskOp:$vm), 1218 [], "vmsltu.vi", "$vd, $vs2, $imm$vm">; 1219// Handle signed with pseudos as well for more consistency in the 1220// implementation. 1221def PseudoVMSGE_VI : Pseudo<(outs VR:$vd), 1222 (ins VR:$vs2, simm5_plus1:$imm, VMaskOp:$vm), 1223 [], "vmsge.vi", "$vd, $vs2, $imm$vm">; 1224def PseudoVMSLT_VI : Pseudo<(outs VR:$vd), 1225 (ins VR:$vs2, simm5_plus1:$imm, VMaskOp:$vm), 1226 [], "vmslt.vi", "$vd, $vs2, $imm$vm">; 1227} 1228 1229let isCodeGenOnly = 0, isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 0, 1230 mayStore = 0 in { 1231def PseudoVMSGEU_VX : Pseudo<(outs VR:$vd), 1232 (ins VR:$vs2, GPR:$rs1), 1233 [], "vmsgeu.vx", "$vd, $vs2, $rs1">; 1234def PseudoVMSGE_VX : Pseudo<(outs VR:$vd), 1235 (ins VR:$vs2, GPR:$rs1), 1236 [], "vmsge.vx", "$vd, $vs2, $rs1">; 1237def PseudoVMSGEU_VX_M : Pseudo<(outs VRNoV0:$vd), 1238 (ins VR:$vs2, GPR:$rs1, VMaskOp:$vm), 1239 [], "vmsgeu.vx", "$vd, $vs2, $rs1$vm">; 1240def PseudoVMSGE_VX_M : Pseudo<(outs VRNoV0:$vd), 1241 (ins VR:$vs2, GPR:$rs1, VMaskOp:$vm), 1242 [], "vmsge.vx", "$vd, $vs2, $rs1$vm">; 1243def PseudoVMSGEU_VX_M_T : Pseudo<(outs VR:$vd, VRNoV0:$scratch), 1244 (ins VR:$vs2, GPR:$rs1, VMaskOp:$vm), 1245 [], "vmsgeu.vx", "$vd, $vs2, $rs1$vm, $scratch">; 1246def PseudoVMSGE_VX_M_T : Pseudo<(outs VR:$vd, VRNoV0:$scratch), 1247 (ins VR:$vs2, GPR:$rs1, VMaskOp:$vm), 1248 [], "vmsge.vx", "$vd, $vs2, $rs1$vm, $scratch">; 1249} 1250 1251// Vector Integer Min/Max Instructions 1252defm VMINU_V : VMINMAX_IV_V_X<"vminu", 0b000100>; 1253defm VMIN_V : VMINMAX_IV_V_X<"vmin", 0b000101>; 1254defm VMAXU_V : VMINMAX_IV_V_X<"vmaxu", 0b000110>; 1255defm VMAX_V : VMINMAX_IV_V_X<"vmax", 0b000111>; 1256 1257// Vector Single-Width Integer Multiply Instructions 1258defm VMUL_V : VMUL_MV_V_X<"vmul", 0b100101>; 1259defm VMULH_V : VMUL_MV_V_X<"vmulh", 0b100111>; 1260defm VMULHU_V : VMUL_MV_V_X<"vmulhu", 0b100100>; 1261defm VMULHSU_V : VMUL_MV_V_X<"vmulhsu", 0b100110>; 1262 1263// Vector Integer Divide Instructions 1264defm VDIVU_V : VDIV_MV_V_X<"vdivu", 0b100000>; 1265defm VDIV_V : VDIV_MV_V_X<"vdiv", 0b100001>; 1266defm VREMU_V : VDIV_MV_V_X<"vremu", 0b100010>; 1267defm VREM_V : VDIV_MV_V_X<"vrem", 0b100011>; 1268 1269// Vector Widening Integer Multiply Instructions 1270let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in { 1271defm VWMUL_V : VWMUL_MV_V_X<"vwmul", 0b111011>; 1272defm VWMULU_V : VWMUL_MV_V_X<"vwmulu", 0b111000>; 1273defm VWMULSU_V : VWMUL_MV_V_X<"vwmulsu", 0b111010>; 1274} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV 1275 1276// Vector Single-Width Integer Multiply-Add Instructions 1277defm VMACC_V : VMAC_MV_V_X<"vmacc", 0b101101>; 1278defm VNMSAC_V : VMAC_MV_V_X<"vnmsac", 0b101111>; 1279defm VMADD_V : VMAC_MV_V_X<"vmadd", 0b101001>; 1280defm VNMSUB_V : VMAC_MV_V_X<"vnmsub", 0b101011>; 1281 1282// Vector Widening Integer Multiply-Add Instructions 1283defm VWMACCU_V : VWMAC_MV_V_X<"vwmaccu", 0b111100>; 1284defm VWMACC_V : VWMAC_MV_V_X<"vwmacc", 0b111101>; 1285defm VWMACCSU_V : VWMAC_MV_V_X<"vwmaccsu", 0b111111>; 1286defm VWMACCUS_V : VWMAC_MV_X<"vwmaccus", 0b111110>; 1287 1288// Vector Integer Merge Instructions 1289defm VMERGE_V : VMRG_IV_V_X_I<"vmerge", 0b010111>; 1290 1291// Vector Integer Move Instructions 1292let hasSideEffects = 0, mayLoad = 0, mayStore = 0, vs2 = 0, vm = 1, 1293 RVVConstraint = NoConstraint in { 1294// op vd, vs1 1295def VMV_V_V : RVInstVV<0b010111, OPIVV, (outs VR:$vd), 1296 (ins VR:$vs1), "vmv.v.v", "$vd, $vs1">, 1297 SchedUnaryMC<"WriteVIMovV", "ReadVIMovV", forceMasked=0>; 1298// op vd, rs1 1299def VMV_V_X : RVInstVX<0b010111, OPIVX, (outs VR:$vd), 1300 (ins GPR:$rs1), "vmv.v.x", "$vd, $rs1">, 1301 SchedUnaryMC<"WriteVIMovX", "ReadVIMovX", forceMasked=0>; 1302// op vd, imm 1303def VMV_V_I : RVInstIVI<0b010111, (outs VR:$vd), 1304 (ins simm5:$imm), "vmv.v.i", "$vd, $imm">, 1305 SchedNullaryMC<"WriteVIMovI", forceMasked=0>; 1306} // hasSideEffects = 0, mayLoad = 0, mayStore = 0 1307 1308// Vector Fixed-Point Arithmetic Instructions 1309defm VSADDU_V : VSALU_IV_V_X_I<"vsaddu", 0b100000>; 1310defm VSADD_V : VSALU_IV_V_X_I<"vsadd", 0b100001>; 1311defm VSSUBU_V : VSALU_IV_V_X<"vssubu", 0b100010>; 1312defm VSSUB_V : VSALU_IV_V_X<"vssub", 0b100011>; 1313 1314// Vector Single-Width Averaging Add and Subtract 1315defm VAADDU_V : VAALU_MV_V_X<"vaaddu", 0b001000>; 1316defm VAADD_V : VAALU_MV_V_X<"vaadd", 0b001001>; 1317defm VASUBU_V : VAALU_MV_V_X<"vasubu", 0b001010>; 1318defm VASUB_V : VAALU_MV_V_X<"vasub", 0b001011>; 1319 1320// Vector Single-Width Fractional Multiply with Rounding and Saturation 1321defm VSMUL_V : VSMUL_IV_V_X<"vsmul", 0b100111>; 1322 1323// Vector Single-Width Scaling Shift Instructions 1324defm VSSRL_V : VSSHF_IV_V_X_I<"vssrl", 0b101010>; 1325defm VSSRA_V : VSSHF_IV_V_X_I<"vssra", 0b101011>; 1326 1327// Vector Narrowing Fixed-Point Clip Instructions 1328let Constraints = "@earlyclobber $vd" in { 1329defm VNCLIPU_W : VNCLP_IV_V_X_I<"vnclipu", 0b101110>; 1330defm VNCLIP_W : VNCLP_IV_V_X_I<"vnclip", 0b101111>; 1331} // Constraints = "@earlyclobber $vd" 1332} // Predicates = [HasVInstructions] 1333 1334let Predicates = [HasVInstructionsAnyF] in { 1335// Vector Single-Width Floating-Point Add/Subtract Instructions 1336let Uses = [FRM], mayRaiseFPException = true in { 1337defm VFADD_V : VALU_FV_V_F<"vfadd", 0b000000>; 1338defm VFSUB_V : VALU_FV_V_F<"vfsub", 0b000010>; 1339defm VFRSUB_V : VALU_FV_F<"vfrsub", 0b100111>; 1340} 1341 1342// Vector Widening Floating-Point Add/Subtract Instructions 1343let Constraints = "@earlyclobber $vd", 1344 Uses = [FRM], 1345 mayRaiseFPException = true in { 1346let RVVConstraint = WidenV in { 1347defm VFWADD_V : VWALU_FV_V_F<"vfwadd", 0b110000, "v">; 1348defm VFWSUB_V : VWALU_FV_V_F<"vfwsub", 0b110010, "v">; 1349} // RVVConstraint = WidenV 1350// Set earlyclobber for following instructions for second and mask operands. 1351// This has the downside that the earlyclobber constraint is too coarse and 1352// will impose unnecessary restrictions by not allowing the destination to 1353// overlap with the first (wide) operand. 1354let RVVConstraint = WidenW in { 1355defm VFWADD_W : VWALU_FV_V_F<"vfwadd", 0b110100, "w">; 1356defm VFWSUB_W : VWALU_FV_V_F<"vfwsub", 0b110110, "w">; 1357} // RVVConstraint = WidenW 1358} // Constraints = "@earlyclobber $vd", Uses = [FRM], mayRaiseFPException = true 1359 1360// Vector Single-Width Floating-Point Multiply/Divide Instructions 1361let Uses = [FRM], mayRaiseFPException = true in { 1362defm VFMUL_V : VMUL_FV_V_F<"vfmul", 0b100100>; 1363defm VFDIV_V : VDIV_FV_V_F<"vfdiv", 0b100000>; 1364defm VFRDIV_V : VDIV_FV_F<"vfrdiv", 0b100001>; 1365} 1366 1367// Vector Widening Floating-Point Multiply 1368let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV, 1369 Uses = [FRM], mayRaiseFPException = true in { 1370defm VFWMUL_V : VWMUL_FV_V_F<"vfwmul", 0b111000>; 1371} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV, Uses = [FRM], mayRaiseFPException = true 1372 1373// Vector Single-Width Floating-Point Fused Multiply-Add Instructions 1374let Uses = [FRM], mayRaiseFPException = true in { 1375defm VFMACC_V : VMAC_FV_V_F<"vfmacc", 0b101100>; 1376defm VFNMACC_V : VMAC_FV_V_F<"vfnmacc", 0b101101>; 1377defm VFMSAC_V : VMAC_FV_V_F<"vfmsac", 0b101110>; 1378defm VFNMSAC_V : VMAC_FV_V_F<"vfnmsac", 0b101111>; 1379defm VFMADD_V : VMAC_FV_V_F<"vfmadd", 0b101000>; 1380defm VFNMADD_V : VMAC_FV_V_F<"vfnmadd", 0b101001>; 1381defm VFMSUB_V : VMAC_FV_V_F<"vfmsub", 0b101010>; 1382defm VFNMSUB_V : VMAC_FV_V_F<"vfnmsub", 0b101011>; 1383} 1384 1385// Vector Widening Floating-Point Fused Multiply-Add Instructions 1386let Uses = [FRM], mayRaiseFPException = true in { 1387defm VFWMACC_V : VWMAC_FV_V_F<"vfwmacc", 0b111100>; 1388defm VFWNMACC_V : VWMAC_FV_V_F<"vfwnmacc", 0b111101>; 1389defm VFWMSAC_V : VWMAC_FV_V_F<"vfwmsac", 0b111110>; 1390defm VFWNMSAC_V : VWMAC_FV_V_F<"vfwnmsac", 0b111111>; 1391} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV, Uses = [FRM], mayRaiseFPException = true 1392 1393// Vector Floating-Point Square-Root Instruction 1394let Uses = [FRM], mayRaiseFPException = true in { 1395defm VFSQRT_V : VSQR_FV_VS2<"vfsqrt.v", 0b010011, 0b00000>; 1396defm VFREC7_V : VRCP_FV_VS2<"vfrec7.v", 0b010011, 0b00101>; 1397} 1398 1399let mayRaiseFPException = true in 1400defm VFRSQRT7_V : VRCP_FV_VS2<"vfrsqrt7.v", 0b010011, 0b00100>; 1401 1402// Vector Floating-Point MIN/MAX Instructions 1403let mayRaiseFPException = true in { 1404defm VFMIN_V : VMINMAX_FV_V_F<"vfmin", 0b000100>; 1405defm VFMAX_V : VMINMAX_FV_V_F<"vfmax", 0b000110>; 1406} 1407 1408// Vector Floating-Point Sign-Injection Instructions 1409defm VFSGNJ_V : VSGNJ_FV_V_F<"vfsgnj", 0b001000>; 1410defm VFSGNJN_V : VSGNJ_FV_V_F<"vfsgnjn", 0b001001>; 1411defm VFSGNJX_V : VSGNJ_FV_V_F<"vfsgnjx", 0b001010>; 1412 1413def : InstAlias<"vfneg.v $vd, $vs$vm", 1414 (VFSGNJN_VV VR:$vd, VR:$vs, VR:$vs, VMaskOp:$vm)>; 1415def : InstAlias<"vfneg.v $vd, $vs", 1416 (VFSGNJN_VV VR:$vd, VR:$vs, VR:$vs, zero_reg)>; 1417def : InstAlias<"vfabs.v $vd, $vs$vm", 1418 (VFSGNJX_VV VR:$vd, VR:$vs, VR:$vs, VMaskOp:$vm)>; 1419def : InstAlias<"vfabs.v $vd, $vs", 1420 (VFSGNJX_VV VR:$vd, VR:$vs, VR:$vs, zero_reg)>; 1421 1422// Vector Floating-Point Compare Instructions 1423let RVVConstraint = NoConstraint, mayRaiseFPException = true in { 1424defm VMFEQ_V : VCMP_FV_V_F<"vmfeq", 0b011000>; 1425defm VMFNE_V : VCMP_FV_V_F<"vmfne", 0b011100>; 1426defm VMFLT_V : VCMP_FV_V_F<"vmflt", 0b011011>; 1427defm VMFLE_V : VCMP_FV_V_F<"vmfle", 0b011001>; 1428defm VMFGT_V : VCMP_FV_F<"vmfgt", 0b011101>; 1429defm VMFGE_V : VCMP_FV_F<"vmfge", 0b011111>; 1430} // RVVConstraint = NoConstraint, mayRaiseFPException = true 1431 1432def : InstAlias<"vmfgt.vv $vd, $va, $vb$vm", 1433 (VMFLT_VV VR:$vd, VR:$vb, VR:$va, VMaskOp:$vm), 0>; 1434def : InstAlias<"vmfge.vv $vd, $va, $vb$vm", 1435 (VMFLE_VV VR:$vd, VR:$vb, VR:$va, VMaskOp:$vm), 0>; 1436 1437// Vector Floating-Point Classify Instruction 1438defm VFCLASS_V : VCLS_FV_VS2<"vfclass.v", 0b010011, 0b10000>; 1439 1440let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { 1441 1442// Vector Floating-Point Merge Instruction 1443let vm = 0 in 1444def VFMERGE_VFM : RVInstVX<0b010111, OPFVF, (outs VR:$vd), 1445 (ins VR:$vs2, FPR32:$rs1, VMV0:$v0), 1446 "vfmerge.vfm", "$vd, $vs2, $rs1, v0">, 1447 SchedBinaryMC<"WriteVFMergeV", "ReadVFMergeV", "ReadVFMergeF">; 1448 1449// Vector Floating-Point Move Instruction 1450let RVVConstraint = NoConstraint in 1451let vm = 1, vs2 = 0 in 1452def VFMV_V_F : RVInstVX<0b010111, OPFVF, (outs VR:$vd), 1453 (ins FPR32:$rs1), "vfmv.v.f", "$vd, $rs1">, 1454 SchedUnaryMC<"WriteVFMovV", "ReadVFMovF", forceMasked=0>; 1455 1456} // hasSideEffects = 0, mayLoad = 0, mayStore = 0 1457 1458// Single-Width Floating-Point/Integer Type-Convert Instructions 1459let mayRaiseFPException = true in { 1460let Uses = [FRM] in { 1461defm VFCVT_XU_F_V : VCVTI_FV_VS2<"vfcvt.xu.f.v", 0b010010, 0b00000>; 1462defm VFCVT_X_F_V : VCVTI_FV_VS2<"vfcvt.x.f.v", 0b010010, 0b00001>; 1463} 1464defm VFCVT_RTZ_XU_F_V : VCVTI_FV_VS2<"vfcvt.rtz.xu.f.v", 0b010010, 0b00110>; 1465defm VFCVT_RTZ_X_F_V : VCVTI_FV_VS2<"vfcvt.rtz.x.f.v", 0b010010, 0b00111>; 1466let Uses = [FRM] in { 1467defm VFCVT_F_XU_V : VCVTF_IV_VS2<"vfcvt.f.xu.v", 0b010010, 0b00010>; 1468defm VFCVT_F_X_V : VCVTF_IV_VS2<"vfcvt.f.x.v", 0b010010, 0b00011>; 1469} 1470} // mayRaiseFPException = true 1471 1472// Widening Floating-Point/Integer Type-Convert Instructions 1473let Constraints = "@earlyclobber $vd", RVVConstraint = WidenCvt, 1474 mayRaiseFPException = true in { 1475let Uses = [FRM] in { 1476defm VFWCVT_XU_F_V : VWCVTI_FV_VS2<"vfwcvt.xu.f.v", 0b010010, 0b01000>; 1477defm VFWCVT_X_F_V : VWCVTI_FV_VS2<"vfwcvt.x.f.v", 0b010010, 0b01001>; 1478} 1479defm VFWCVT_RTZ_XU_F_V : VWCVTI_FV_VS2<"vfwcvt.rtz.xu.f.v", 0b010010, 0b01110>; 1480defm VFWCVT_RTZ_X_F_V : VWCVTI_FV_VS2<"vfwcvt.rtz.x.f.v", 0b010010, 0b01111>; 1481defm VFWCVT_F_XU_V : VWCVTF_IV_VS2<"vfwcvt.f.xu.v", 0b010010, 0b01010>; 1482defm VFWCVT_F_X_V : VWCVTF_IV_VS2<"vfwcvt.f.x.v", 0b010010, 0b01011>; 1483defm VFWCVT_F_F_V : VWCVTF_FV_VS2<"vfwcvt.f.f.v", 0b010010, 0b01100>; 1484} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenCvt 1485 1486// Narrowing Floating-Point/Integer Type-Convert Instructions 1487let Constraints = "@earlyclobber $vd", mayRaiseFPException = true in { 1488let Uses = [FRM] in { 1489defm VFNCVT_XU_F_W : VNCVTI_FV_VS2<"vfncvt.xu.f.w", 0b010010, 0b10000>; 1490defm VFNCVT_X_F_W : VNCVTI_FV_VS2<"vfncvt.x.f.w", 0b010010, 0b10001>; 1491} 1492defm VFNCVT_RTZ_XU_F_W : VNCVTI_FV_VS2<"vfncvt.rtz.xu.f.w", 0b010010, 0b10110>; 1493defm VFNCVT_RTZ_X_F_W : VNCVTI_FV_VS2<"vfncvt.rtz.x.f.w", 0b010010, 0b10111>; 1494let Uses = [FRM] in { 1495defm VFNCVT_F_XU_W : VNCVTF_IV_VS2<"vfncvt.f.xu.w", 0b010010, 0b10010>; 1496defm VFNCVT_F_X_W : VNCVTF_IV_VS2<"vfncvt.f.x.w", 0b010010, 0b10011>; 1497defm VFNCVT_F_F_W : VNCVTF_FV_VS2<"vfncvt.f.f.w", 0b010010, 0b10100>; 1498} 1499defm VFNCVT_ROD_F_F_W : VNCVTF_FV_VS2<"vfncvt.rod.f.f.w", 0b010010, 0b10101>; 1500} // Constraints = "@earlyclobber $vd", mayRaiseFPException = true 1501} // Predicates = HasVInstructionsAnyF] 1502 1503let Predicates = [HasVInstructions] in { 1504 1505// Vector Single-Width Integer Reduction Instructions 1506let RVVConstraint = NoConstraint in { 1507defm VREDSUM : VRED_MV_V<"vredsum", 0b000000>; 1508defm VREDMAXU : VREDMINMAX_MV_V<"vredmaxu", 0b000110>; 1509defm VREDMAX : VREDMINMAX_MV_V<"vredmax", 0b000111>; 1510defm VREDMINU : VREDMINMAX_MV_V<"vredminu", 0b000100>; 1511defm VREDMIN : VREDMINMAX_MV_V<"vredmin", 0b000101>; 1512defm VREDAND : VRED_MV_V<"vredand", 0b000001>; 1513defm VREDOR : VRED_MV_V<"vredor", 0b000010>; 1514defm VREDXOR : VRED_MV_V<"vredxor", 0b000011>; 1515} // RVVConstraint = NoConstraint 1516 1517// Vector Widening Integer Reduction Instructions 1518let Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint in { 1519// Set earlyclobber for following instructions for second and mask operands. 1520// This has the downside that the earlyclobber constraint is too coarse and 1521// will impose unnecessary restrictions by not allowing the destination to 1522// overlap with the first (wide) operand. 1523defm VWREDSUMU : VWRED_IV_V<"vwredsumu", 0b110000>; 1524defm VWREDSUM : VWRED_IV_V<"vwredsum", 0b110001>; 1525} // Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint 1526 1527} // Predicates = [HasVInstructions] 1528 1529let Predicates = [HasVInstructionsAnyF] in { 1530// Vector Single-Width Floating-Point Reduction Instructions 1531let RVVConstraint = NoConstraint in { 1532let Uses = [FRM], mayRaiseFPException = true in { 1533defm VFREDOSUM : VREDO_FV_V<"vfredosum", 0b000011>; 1534defm VFREDUSUM : VRED_FV_V<"vfredusum", 0b000001>; 1535} 1536let mayRaiseFPException = true in { 1537defm VFREDMAX : VREDMINMAX_FV_V<"vfredmax", 0b000111>; 1538defm VFREDMIN : VREDMINMAX_FV_V<"vfredmin", 0b000101>; 1539} 1540} // RVVConstraint = NoConstraint 1541 1542def : InstAlias<"vfredsum.vs $vd, $vs2, $vs1$vm", 1543 (VFREDUSUM_VS VR:$vd, VR:$vs2, VR:$vs1, VMaskOp:$vm), 0>; 1544 1545// Vector Widening Floating-Point Reduction Instructions 1546let Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint in { 1547// Set earlyclobber for following instructions for second and mask operands. 1548// This has the downside that the earlyclobber constraint is too coarse and 1549// will impose unnecessary restrictions by not allowing the destination to 1550// overlap with the first (wide) operand. 1551let Uses = [FRM], mayRaiseFPException = true in { 1552defm VFWREDOSUM : VWREDO_FV_V<"vfwredosum", 0b110011>; 1553defm VFWREDUSUM : VWRED_FV_V<"vfwredusum", 0b110001>; 1554} 1555} // Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint 1556 1557def : InstAlias<"vfwredsum.vs $vd, $vs2, $vs1$vm", 1558 (VFWREDUSUM_VS VR:$vd, VR:$vs2, VR:$vs1, VMaskOp:$vm), 0>; 1559} // Predicates = [HasVInstructionsAnyF] 1560 1561let Predicates = [HasVInstructions] in { 1562// Vector Mask-Register Logical Instructions 1563let RVVConstraint = NoConstraint in { 1564defm VMAND_M : VMALU_MV_Mask<"vmand", 0b011001, "m">; 1565defm VMNAND_M : VMALU_MV_Mask<"vmnand", 0b011101, "m">; 1566defm VMANDN_M : VMALU_MV_Mask<"vmandn", 0b011000, "m">; 1567defm VMXOR_M : VMALU_MV_Mask<"vmxor", 0b011011, "m">; 1568defm VMOR_M : VMALU_MV_Mask<"vmor", 0b011010, "m">; 1569defm VMNOR_M : VMALU_MV_Mask<"vmnor", 0b011110, "m">; 1570defm VMORN_M : VMALU_MV_Mask<"vmorn", 0b011100, "m">; 1571defm VMXNOR_M : VMALU_MV_Mask<"vmxnor", 0b011111, "m">; 1572} 1573 1574def : InstAlias<"vmmv.m $vd, $vs", 1575 (VMAND_MM VR:$vd, VR:$vs, VR:$vs)>; 1576def : InstAlias<"vmclr.m $vd", 1577 (VMXOR_MM VR:$vd, VR:$vd, VR:$vd)>; 1578def : InstAlias<"vmset.m $vd", 1579 (VMXNOR_MM VR:$vd, VR:$vd, VR:$vd)>; 1580def : InstAlias<"vmnot.m $vd, $vs", 1581 (VMNAND_MM VR:$vd, VR:$vs, VR:$vs)>; 1582 1583def : InstAlias<"vmandnot.mm $vd, $vs2, $vs1", 1584 (VMANDN_MM VR:$vd, VR:$vs2, VR:$vs1), 0>; 1585def : InstAlias<"vmornot.mm $vd, $vs2, $vs1", 1586 (VMORN_MM VR:$vd, VR:$vs2, VR:$vs1), 0>; 1587 1588let hasSideEffects = 0, mayLoad = 0, mayStore = 0, 1589 RVVConstraint = NoConstraint in { 1590 1591// Vector mask population count vcpop 1592def VCPOP_M : RVInstV<0b010000, 0b10000, OPMVV, (outs GPR:$vd), 1593 (ins VR:$vs2, VMaskOp:$vm), 1594 "vcpop.m", "$vd, $vs2$vm">, 1595 SchedUnaryMC<"WriteVMPopV", "ReadVMPopV">; 1596 1597// vfirst find-first-set mask bit 1598def VFIRST_M : RVInstV<0b010000, 0b10001, OPMVV, (outs GPR:$vd), 1599 (ins VR:$vs2, VMaskOp:$vm), 1600 "vfirst.m", "$vd, $vs2$vm">, 1601 SchedUnaryMC<"WriteVMFFSV", "ReadVMFFSV">; 1602 1603} // hasSideEffects = 0, mayLoad = 0, mayStore = 0 1604 1605def : InstAlias<"vpopc.m $vd, $vs2$vm", 1606 (VCPOP_M GPR:$vd, VR:$vs2, VMaskOp:$vm), 0>; 1607 1608let Constraints = "@earlyclobber $vd", RVVConstraint = Iota in { 1609 1610// vmsbf.m set-before-first mask bit 1611defm VMSBF_M : VMSFS_MV_V<"vmsbf.m", 0b010100, 0b00001>; 1612// vmsif.m set-including-first mask bit 1613defm VMSIF_M : VMSFS_MV_V<"vmsif.m", 0b010100, 0b00011>; 1614// vmsof.m set-only-first mask bit 1615defm VMSOF_M : VMSFS_MV_V<"vmsof.m", 0b010100, 0b00010>; 1616// Vector Iota Instruction 1617defm VIOTA_M : VIOTA_MV_V<"viota.m", 0b010100, 0b10000>; 1618 1619} // Constraints = "@earlyclobber $vd", RVVConstraint = Iota 1620 1621// Vector Element Index Instruction 1622let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { 1623 1624let vs2 = 0 in 1625def VID_V : RVInstV<0b010100, 0b10001, OPMVV, (outs VR:$vd), 1626 (ins VMaskOp:$vm), "vid.v", "$vd$vm">, 1627 SchedNullaryMC<"WriteVIdxV">; 1628 1629// Integer Scalar Move Instructions 1630let vm = 1, RVVConstraint = NoConstraint in { 1631def VMV_X_S : RVInstV<0b010000, 0b00000, OPMVV, (outs GPR:$vd), 1632 (ins VR:$vs2), "vmv.x.s", "$vd, $vs2">, 1633 Sched<[WriteVMovXS, ReadVMovXS]>; 1634let Constraints = "$vd = $vd_wb" in 1635def VMV_S_X : RVInstV2<0b010000, 0b00000, OPMVX, (outs VR:$vd_wb), 1636 (ins VR:$vd, GPR:$rs1), "vmv.s.x", "$vd, $rs1">, 1637 Sched<[WriteVMovSX, ReadVMovSX_V, ReadVMovSX_X]>; 1638} 1639 1640} // hasSideEffects = 0, mayLoad = 0, mayStore = 0 1641 1642} // Predicates = [HasVInstructions] 1643 1644let Predicates = [HasVInstructionsAnyF] in { 1645 1646let hasSideEffects = 0, mayLoad = 0, mayStore = 0, vm = 1, 1647 RVVConstraint = NoConstraint in { 1648// Floating-Point Scalar Move Instructions 1649def VFMV_F_S : RVInstV<0b010000, 0b00000, OPFVV, (outs FPR32:$vd), 1650 (ins VR:$vs2), "vfmv.f.s", "$vd, $vs2">, 1651 Sched<[WriteVMovFS, ReadVMovFS]>; 1652let Constraints = "$vd = $vd_wb" in 1653def VFMV_S_F : RVInstV2<0b010000, 0b00000, OPFVF, (outs VR:$vd_wb), 1654 (ins VR:$vd, FPR32:$rs1), "vfmv.s.f", "$vd, $rs1">, 1655 Sched<[WriteVMovSF, ReadVMovSF_V, ReadVMovSF_F]>; 1656 1657} // hasSideEffects = 0, mayLoad = 0, mayStore = 0, vm = 1 1658 1659} // Predicates = [HasVInstructionsAnyF] 1660 1661let Predicates = [HasVInstructions] in { 1662// Vector Slide Instructions 1663let Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp in { 1664defm VSLIDEUP_V : VSLD_IV_X_I<"vslideup", 0b001110, /*slidesUp=*/true>; 1665defm VSLIDE1UP_V : VSLD1_MV_X<"vslide1up", 0b001110>; 1666} // Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp 1667defm VSLIDEDOWN_V : VSLD_IV_X_I<"vslidedown", 0b001111, /*slidesUp=*/false>; 1668defm VSLIDE1DOWN_V : VSLD1_MV_X<"vslide1down", 0b001111>; 1669} // Predicates = [HasVInstructions] 1670 1671let Predicates = [HasVInstructionsAnyF] in { 1672let Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp in { 1673defm VFSLIDE1UP_V : VSLD1_FV_F<"vfslide1up", 0b001110>; 1674} // Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp 1675defm VFSLIDE1DOWN_V : VSLD1_FV_F<"vfslide1down", 0b001111>; 1676} // Predicates = [HasVInstructionsAnyF] 1677 1678let Predicates = [HasVInstructions] in { 1679// Vector Register Gather Instruction 1680let Constraints = "@earlyclobber $vd", RVVConstraint = Vrgather in { 1681defm VRGATHER_V : VGTR_IV_V_X_I<"vrgather", 0b001100>; 1682def VRGATHEREI16_VV : VALUVV<0b001110, OPIVV, "vrgatherei16.vv">, 1683 SchedBinaryMC<"WriteVRGatherEI16VV", 1684 "ReadVRGatherEI16VV_data", 1685 "ReadVRGatherEI16VV_index">; 1686} // Constraints = "@earlyclobber $vd", RVVConstraint = Vrgather 1687 1688// Vector Compress Instruction 1689let Constraints = "@earlyclobber $vd", RVVConstraint = Vcompress in { 1690defm VCOMPRESS_V : VCPR_MV_Mask<"vcompress", 0b010111>; 1691} // Constraints = "@earlyclobber $vd", RVVConstraint = Vcompress 1692 1693let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isMoveReg = 1, 1694 RVVConstraint = NoConstraint in { 1695// A future extension may relax the vector register alignment restrictions. 1696foreach n = [1, 2, 4, 8] in { 1697 defvar vrc = !cast<VReg>(!if(!eq(n, 1), "VR", "VRM"#n)); 1698 def VMV#n#R_V : RVInstV<0b100111, !add(n, -1), OPIVI, (outs vrc:$vd), 1699 (ins vrc:$vs2), "vmv" # n # "r.v", "$vd, $vs2">, 1700 VMVRSched<n> { 1701 let Uses = []; 1702 let vm = 1; 1703 } 1704} 1705} // hasSideEffects = 0, mayLoad = 0, mayStore = 0 1706} // Predicates = [HasVInstructions] 1707 1708let Predicates = [HasVInstructions] in { 1709 foreach nf=2-8 in { 1710 foreach eew = [8, 16, 32] in { 1711 defvar w = !cast<RISCVWidth>("LSWidth"#eew); 1712 1713 def VLSEG#nf#E#eew#_V : 1714 VUnitStrideSegmentLoad<!add(nf, -1), w, "vlseg"#nf#"e"#eew#".v">, 1715 VLSEGSchedMC<nf, eew>; 1716 def VLSEG#nf#E#eew#FF_V : 1717 VUnitStrideSegmentLoadFF<!add(nf, -1), w, "vlseg"#nf#"e"#eew#"ff.v">, 1718 VLSEGFFSchedMC<nf, eew>; 1719 def VSSEG#nf#E#eew#_V : 1720 VUnitStrideSegmentStore<!add(nf, -1), w, "vsseg"#nf#"e"#eew#".v">, 1721 VSSEGSchedMC<nf, eew>; 1722 // Vector Strided Instructions 1723 def VLSSEG#nf#E#eew#_V : 1724 VStridedSegmentLoad<!add(nf, -1), w, "vlsseg"#nf#"e"#eew#".v">, 1725 VLSSEGSchedMC<nf, eew>; 1726 def VSSSEG#nf#E#eew#_V : 1727 VStridedSegmentStore<!add(nf, -1), w, "vssseg"#nf#"e"#eew#".v">, 1728 VSSSEGSchedMC<nf, eew>; 1729 1730 // Vector Indexed Instructions 1731 def VLUXSEG#nf#EI#eew#_V : 1732 VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedUnord, w, 1733 "vluxseg"#nf#"ei"#eew#".v">, 1734 VLXSEGSchedMC<nf, eew, isOrdered=0>; 1735 def VLOXSEG#nf#EI#eew#_V : 1736 VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedOrder, w, 1737 "vloxseg"#nf#"ei"#eew#".v">, 1738 VLXSEGSchedMC<nf, eew, isOrdered=1>; 1739 def VSUXSEG#nf#EI#eew#_V : 1740 VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedUnord, w, 1741 "vsuxseg"#nf#"ei"#eew#".v">, 1742 VSXSEGSchedMC<nf, eew, isOrdered=0>; 1743 def VSOXSEG#nf#EI#eew#_V : 1744 VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedOrder, w, 1745 "vsoxseg"#nf#"ei"#eew#".v">, 1746 VSXSEGSchedMC<nf, eew, isOrdered=1>; 1747 } 1748 } 1749} // Predicates = [HasVInstructions] 1750 1751let Predicates = [HasVInstructionsI64] in { 1752 foreach nf=2-8 in { 1753 // Vector Unit-strided Segment Instructions 1754 def VLSEG#nf#E64_V : 1755 VUnitStrideSegmentLoad<!add(nf, -1), LSWidth64, "vlseg"#nf#"e64.v">, 1756 VLSEGSchedMC<nf, 64>; 1757 def VLSEG#nf#E64FF_V : 1758 VUnitStrideSegmentLoadFF<!add(nf, -1), LSWidth64, "vlseg"#nf#"e64ff.v">, 1759 VLSEGFFSchedMC<nf, 64>; 1760 def VSSEG#nf#E64_V : 1761 VUnitStrideSegmentStore<!add(nf, -1), LSWidth64, "vsseg"#nf#"e64.v">, 1762 VSSEGSchedMC<nf, 64>; 1763 1764 // Vector Strided Segment Instructions 1765 def VLSSEG#nf#E64_V : 1766 VStridedSegmentLoad<!add(nf, -1), LSWidth64, "vlsseg"#nf#"e64.v">, 1767 VLSSEGSchedMC<nf, 64>; 1768 def VSSSEG#nf#E64_V : 1769 VStridedSegmentStore<!add(nf, -1), LSWidth64, "vssseg"#nf#"e64.v">, 1770 VSSSEGSchedMC<nf, 64>; 1771 } 1772} // Predicates = [HasVInstructionsI64] 1773let Predicates = [HasVInstructionsI64, IsRV64] in { 1774 foreach nf = 2 - 8 in { 1775 // Vector Indexed Segment Instructions 1776 def VLUXSEG #nf #EI64_V 1777 : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedUnord, LSWidth64, 1778 "vluxseg" #nf #"ei64.v">, 1779 VLXSEGSchedMC<nf, 64, isOrdered=0>; 1780 def VLOXSEG #nf #EI64_V 1781 : VIndexedSegmentLoad<!add(nf, -1), MOPLDIndexedOrder, LSWidth64, 1782 "vloxseg" #nf #"ei64.v">, 1783 VLXSEGSchedMC<nf, 64, isOrdered=1>; 1784 def VSUXSEG #nf #EI64_V 1785 : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedUnord, LSWidth64, 1786 "vsuxseg" #nf #"ei64.v">, 1787 VSXSEGSchedMC<nf, 64, isOrdered=0>; 1788 def VSOXSEG #nf #EI64_V 1789 : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedOrder, LSWidth64, 1790 "vsoxseg" #nf #"ei64.v">, 1791 VSXSEGSchedMC<nf, 64, isOrdered=1>; 1792 } 1793} // Predicates = [HasVInstructionsI64, IsRV64] 1794 1795include "RISCVInstrInfoZvfbf.td" 1796include "RISCVInstrInfoVPseudos.td" 1797