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/linux/Documentation/devicetree/bindings/interconnect/
H A Dqcom,msm8996.yaml111 reg = <0x00408000 0x5a000>;
117 reg = <0x00543000 0x6000>;
/linux/arch/arm/nwfpe/
H A Dfpopcode.h18 |c o n d|1 1 0 P|U|u|W|L| Rn |v| Fd |0|0|0|1| o f f s e t | CPDT
19 |c o n d|1 1 0 P|U|w|W|L| Rn |x| Fd |0|0|1|0| o f f s e t | CPDT (copro 2)
21 |c o n d|1 1 1 0|a|b|c|d|e| Fn |j| Fd |0|0|0|1|f|g|h|0|i| Fm | CPDO
22 |c o n d|1 1 1 0|a|b|c|L|e| Fn | Rd |0|0|0|1|f|g|h|1|i| Fm | CPRT
23 |c o n d|1 1 1 0|a|b|c|1|e| Fn |1|1|1|1|0|0|0|1|f|g|h|1|i| Fm | comparisons
45 P pre/post index bit: 0 = postindex, 1 = preindex
46 U up/down bit: 0 = stack grows down, 1 = stack grows up
48 L load/store bit: 0 = store, 1 = load
60 j dyadic/monadic bit: 0 = dyadic, 1 = monadic
69 | Single | 0 | 0 | x | 1 words |
[all …]
/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac100.h21 #define MAC_CONTROL 0x00000000 /* MAC Control */
22 #define MAC_ADDR_HIGH 0x00000004 /* MAC Address High */
23 #define MAC_ADDR_LOW 0x00000008 /* MAC Address Low */
24 #define MAC_HASH_HIGH 0x0000000c /* Multicast Hash Table High */
25 #define MAC_HASH_LOW 0x00000010 /* Multicast Hash Table Low */
26 #define MAC_MII_ADDR 0x00000014 /* MII Address */
27 #define MAC_MII_DATA 0x00000018 /* MII Data */
28 #define MAC_FLOW_CTRL 0x0000001c /* Flow Control */
29 #define MAC_VLAN1 0x00000020 /* VLAN1 Tag */
30 #define MAC_VLAN2 0x00000024 /* VLAN2 Tag */
[all …]
/linux/drivers/video/fbdev/i810/
H A Di810_gtf.c31 { 15, 0x0070c000 }, { 19, 0x0070c000 }, { 25, 0x22003000 },
32 { 28, 0x22003000 }, { 31, 0x22003000 }, { 36, 0x22007000 },
33 { 40, 0x22007000 }, { 45, 0x22007000 }, { 49, 0x22008000 },
34 { 50, 0x22008000 }, { 56, 0x22008000 }, { 65, 0x22008000 },
35 { 75, 0x22008000 }, { 78, 0x22008000 }, { 80, 0x22008000 },
36 { 94, 0x22008000 }, { 96, 0x22107000 }, { 99, 0x22107000 },
37 { 108, 0x22107000 }, { 121, 0x22107000 }, { 128, 0x22107000 },
38 { 132, 0x22109000 }, { 135, 0x22109000 }, { 157, 0x2210b000 },
39 { 162, 0x2210b000 }, { 175, 0x2210b000 }, { 189, 0x2220e000 },
40 { 195, 0x2220e000 }, { 202, 0x2220e000 }, { 204, 0x2220e000 },
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsdx75.dtsi32 #clock-cells = <0>;
38 #clock-cells = <0>;
44 #size-cells = <0>;
46 CPU0: cpu@0 {
49 reg = <0x0 0x0>;
50 clocks = <&cpufreq_hw 0>;
54 qcom,freq-domain = <&cpufreq_hw 0>;
75 reg = <0x0 0x100>;
76 clocks = <&cpufreq_hw 0>;
80 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsm6350.dtsi32 #clock-cells = <0>;
40 #clock-cells = <0>;
46 #size-cells = <0>;
48 CPU0: cpu@0 {
51 reg = <0x0 0x0>;
52 clocks = <&cpufreq_hw 0>;
57 qcom,freq-domain = <&cpufreq_hw 0>;
81 reg = <0x0 0x100>;
82 clocks = <&cpufreq_hw 0>;
87 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dmsm8996.dtsi29 #clock-cells = <0>;
36 #clock-cells = <0>;
44 #size-cells = <0>;
46 CPU0: cpu@0 {
49 reg = <0x0 0x0>;
53 clocks = <&kryocc 0>;
68 reg = <0x0 0x1>;
72 clocks = <&kryocc 0>;
82 reg = <0x0 0x100>;
101 reg = <0x0 0x101>;
[all …]
H A Dsm8350.dtsi38 #clock-cells = <0>;
46 #clock-cells = <0>;
52 #size-cells = <0>;
54 CPU0: cpu@0 {
57 reg = <0x0 0x0>;
58 clocks = <&cpufreq_hw 0>;
61 qcom,freq-domain = <&cpufreq_hw 0>;
81 reg = <0x0 0x100>;
82 clocks = <&cpufreq_hw 0>;
85 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsa8775p.dtsi27 #clock-cells = <0>;
32 #clock-cells = <0>;
38 #size-cells = <0>;
40 CPU0: cpu@0 {
43 reg = <0x0 0x0>;
45 qcom,freq-domain = <&cpufreq_hw 0>;
65 reg = <0x0 0x100>;
67 qcom,freq-domain = <&cpufreq_hw 0>;
82 reg = <0x0 0x200>;
84 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsm8550.dtsi38 #clock-cells = <0>;
43 #clock-cells = <0>;
47 #clock-cells = <0>;
55 #clock-cells = <0>;
65 #size-cells = <0>;
67 CPU0: cpu@0 {
70 reg = <0 0>;
71 clocks = <&cpufreq_hw 0>;
76 qcom,freq-domain = <&cpufreq_hw 0>;
96 reg = <0 0x100>;
[all …]
H A Dsc8280xp.dtsi33 #clock-cells = <0>;
38 #clock-cells = <0>;
45 #size-cells = <0>;
47 CPU0: cpu@0 {
50 reg = <0x0 0x0>;
51 clocks = <&cpufreq_hw 0>;
58 qcom,freq-domain = <&cpufreq_hw 0>;
78 reg = <0x0 0x100>;
79 clocks = <&cpufreq_hw 0>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dx1e80100.dtsi36 #clock-cells = <0>;
42 #clock-cells = <0>;
47 #clock-cells = <0>;
56 #clock-cells = <0>;
66 #size-cells = <0>;
68 CPU0: cpu@0 {
71 reg = <0x0 0x0>;
88 reg = <0x0 0x100>;
99 reg = <0x0 0x200>;
110 reg = <0x0 0x300>;
[all …]
H A Dsm8250.dtsi80 #clock-cells = <0>;
88 #clock-cells = <0>;
94 #size-cells = <0>;
96 CPU0: cpu@0 {
99 reg = <0x0 0x0>;
100 clocks = <&cpufreq_hw 0>;
107 qcom,freq-domain = <&cpufreq_hw 0>;
109 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
115 cache-size = <0x20000>;
121 cache-size = <0x400000>;
[all …]
H A Dsc7280.dtsi81 #clock-cells = <0>;
87 #clock-cells = <0>;
98 reg = <0x0 0x004cd000 0x0 0x1000>;
102 reg = <0x0 0x80000000 0x0 0x600000>;
107 reg = <0x0 0x80600000 0x0 0x200000>;
112 reg = <0x0 0x80800000 0x0 0x60000>;
117 reg = <0x0 0x80860000 0x0 0x20000>;
123 reg = <0x0 0x80884000 0x0 0x10000>;
128 reg = <0x0 0x808ff000 0x0 0x1000>;
133 reg = <0x0 0x80900000 0x0 0x200000>;
[all …]
/linux/drivers/video/fbdev/
H A Dsm712fb.c71 .red = {16, 8, 0},
72 .green = {8, 8, 0},
73 .blue = {0, 8, 0},
78 .nonstd = 0,
88 .type_aux = 0,
89 .xpanstep = 0,
90 .ypanstep = 0,
91 .ywrapstep = 0,
102 {"0x301", 640, 480, 8},
103 {"0x303", 800, 600, 8},
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_2_3_default.h26 #define mmBIF_BX_PF_MM_INDEX_DEFAULT 0x00000000
27 #define mmBIF_BX_PF_MM_DATA_DEFAULT 0x00000000
28 #define mmBIF_BX_PF_MM_INDEX_HI_DEFAULT 0x00000000
32 #define mmSYSHUB_INDEX_OVLP_DEFAULT 0x00000000
33 #define mmSYSHUB_DATA_OVLP_DEFAULT 0x00000000
34 #define mmPCIE_INDEX_DEFAULT 0x00000000
35 #define mmPCIE_DATA_DEFAULT 0x00000000
36 #define mmPCIE_INDEX2_DEFAULT 0x00000000
37 #define mmPCIE_DATA2_DEFAULT 0x00000000
38 #define mmSBIOS_SCRATCH_0_DEFAULT 0x00000000
[all …]