Lines Matching +full:0 +full:x00408000
27 #clock-cells = <0>;
32 #clock-cells = <0>;
38 #size-cells = <0>;
40 CPU0: cpu@0 {
43 reg = <0x0 0x0>;
45 qcom,freq-domain = <&cpufreq_hw 0>;
65 reg = <0x0 0x100>;
67 qcom,freq-domain = <&cpufreq_hw 0>;
82 reg = <0x0 0x200>;
84 qcom,freq-domain = <&cpufreq_hw 0>;
99 reg = <0x0 0x300>;
101 qcom,freq-domain = <&cpufreq_hw 0>;
116 reg = <0x0 0x10000>;
139 reg = <0x0 0x10100>;
156 reg = <0x0 0x10200>;
173 reg = <0x0 0x10300>;
228 GOLD_CPU_SLEEP_0: cpu-sleep-0 {
231 arm,psci-suspend-param = <0x40000003>;
241 arm,psci-suspend-param = <0x40000004>;
250 CLUSTER_SLEEP_GOLD: cluster-sleep-0 {
252 arm,psci-suspend-param = <0x41000044>;
260 arm,psci-suspend-param = <0x42000144>;
375 reg = <0x0 0x80000000 0x0 0x0>;
397 #power-domain-cells = <0>;
404 #power-domain-cells = <0>;
411 #power-domain-cells = <0>;
418 #power-domain-cells = <0>;
425 #power-domain-cells = <0>;
432 #power-domain-cells = <0>;
439 #power-domain-cells = <0>;
446 #power-domain-cells = <0>;
453 #power-domain-cells = <0>;
459 #power-domain-cells = <0>;
465 #power-domain-cells = <0>;
476 reg = <0x0 0x80000000 0x0 0x10000000>;
481 reg = <0x0 0x90000000 0x0 0x600000>;
486 reg = <0x0 0x90600000 0x0 0x200000>;
491 reg = <0x0 0x90800000 0x0 0x60000>;
497 reg = <0x0 0x90860000 0x0 0x20000>;
502 reg = <0x0 0x908b0000 0x0 0x10000>;
507 reg = <0x0 0x908c0000 0x0 0x1000>;
512 reg = <0x0 0x908f0000 0x0 0xe000>;
517 reg = <0x0 0x908fe000 0x0 0x2000>;
523 reg = <0x0 0x90900000 0x0 0x200000>;
529 reg = <0x0 0x90c00000 0x0 0x100000>;
534 reg = <0x0 0x90d00000 0x0 0x100000>;
539 reg = <0x0 0x90e00000 0x0 0x300000>;
544 reg = <0x0 0x91b00000 0x0 0x40000>;
549 reg = <0x0 0x91b40000 0x0 0x40000>;
554 reg = <0x0 0x91b80000 0x0 0x10000>;
559 reg = <0x0 0x91b90000 0x0 0x10000>;
564 reg = <0x0 0x91ba0000 0x0 0x1000>;
570 reg = <0x0 0x91c00000 0x0 0x1400000>;
575 reg = <0x0 0x93b00000 0x0 0xf00000>;
580 reg = <0x0 0x94a00000 0x0 0x800000>;
585 reg = <0x0 0x95200000 0x0 0x500000>;
590 reg = <0x0 0x95c00000 0x0 0x1e00000>;
595 reg = <0x0 0x97b00000 0x0 0x1e00000>;
600 reg = <0x0 0x99900000 0x0 0x1e00000>;
605 reg = <0x0 0x9b800000 0x0 0x1e00000>;
610 reg = <0x0 0x9d600000 0x0 0x2000>;
615 reg = <0x0 0x9d700000 0x0 0x1e00000>;
620 reg = <0x0 0x9f500000 0x0 0x700000>;
625 reg = <0x0 0x9fc00000 0x0 0x700000>;
630 reg = <0x0 0xae000000 0x0 0x1000000>;
635 reg = <0x0 0xb0000000 0x0 0x800000>;
640 reg = <0x0 0xbeb00000 0x0 0x11500000>;
645 reg = <0x0 0xd0000000 0x0 0x40000>;
650 reg = <0x0 0xd0040000 0x0 0x10000>;
655 reg = <0x0 0xd0050000 0x0 0x4000>;
660 reg = <0x0 0xd0054000 0x0 0x9c000>;
665 reg = <0x0 0xd00f0000 0x0 0x10000>;
670 reg = <0x0 0xd0100000 0x0 0x1200000>;
675 reg = <0x0 0xd1300000 0x0 0x500000>;
680 reg = <0x0 0xd1800000 0x0 0x100000>;
685 reg = <0x0 0xd1900000 0x0 0x3800000>;
690 reg = <0x0 0xdb100000 0x0 0x100000>;
695 reg = <0x0 0xdb200000 0x0 0x100000>;
708 qcom,local-pid = <0>;
731 qcom,local-pid = <0>;
754 qcom,local-pid = <0>;
777 qcom,local-pid = <0>;
800 qcom,local-pid = <0>;
815 soc: soc@0 {
819 ranges = <0 0 0 0 0x10 0>;
823 reg = <0x0 0x00100000 0x0 0xc7018>;
829 <0>,
830 <0>,
831 <0>,
834 <0>,
835 <0>,
836 <0>,
839 <0>,
840 <0>,
841 <0>;
847 reg = <0x0 0x00408000 0x0 0x1000>;
856 reg = <0x0 0x008c0000 0x0 0x6000>;
861 iommus = <&apps_smmu 0x5a3 0x0>;
868 reg = <0x0 0x880000 0x0 0x4000>;
870 #size-cells = <0>;
889 reg = <0x0 0x880000 0x0 0x4000>;
891 #size-cells = <0>;
910 reg = <0x0 0x884000 0x0 0x4000>;
912 #size-cells = <0>;
931 reg = <0x0 0x884000 0x0 0x4000>;
933 #size-cells = <0>;
952 reg = <0x0 0x888000 0x0 0x4000>;
954 #size-cells = <0>;
973 reg = <0x0 0x00888000 0x0 0x4000>;
988 #size-cells = <0>;
994 reg = <0x0 0x88c000 0x0 0x4000>;
996 #size-cells = <0>;
1015 reg = <0x0 0x88c000 0x0 0x4000>;
1017 #size-cells = <0>;
1036 reg = <0x0 0x0088c000 0x0 0x4000>;
1051 reg = <0x0 0x00890000 0x0 0x4000>;
1066 #size-cells = <0>;
1072 reg = <0x0 0x890000 0x0 0x4000>;
1074 #size-cells = <0>;
1093 reg = <0x0 0x894000 0x0 0x4000>;
1095 #size-cells = <0>;
1114 reg = <0x0 0x894000 0x0 0x4000>;
1116 #size-cells = <0>;
1135 reg = <0x0 0x898000 0x0 0x4000>;
1137 #size-cells = <0>;
1156 reg = <0x0 0x898000 0x0 0x4000>;
1158 #size-cells = <0>;
1178 reg = <0x0 0x9c0000 0x0 0x6000>;
1185 iommus = <&apps_smmu 0x403 0x0>;
1190 reg = <0x0 0x980000 0x0 0x4000>;
1192 #size-cells = <0>;
1211 reg = <0x0 0x980000 0x0 0x4000>;
1213 #size-cells = <0>;
1232 reg = <0x0 0x984000 0x0 0x4000>;
1234 #size-cells = <0>;
1253 reg = <0x0 0x984000 0x0 0x4000>;
1255 #size-cells = <0>;
1274 reg = <0x0 0x988000 0x0 0x4000>;
1276 #size-cells = <0>;
1295 reg = <0x0 0x988000 0x0 0x4000>;
1297 #size-cells = <0>;
1316 reg = <0x0 0x98c000 0x0 0x4000>;
1318 #size-cells = <0>;
1337 reg = <0x0 0x98c000 0x0 0x4000>;
1339 #size-cells = <0>;
1358 reg = <0x0 0x990000 0x0 0x4000>;
1360 #size-cells = <0>;
1379 reg = <0x0 0x990000 0x0 0x4000>;
1381 #size-cells = <0>;
1400 reg = <0x0 0x994000 0x0 0x4000>;
1402 #size-cells = <0>;
1421 reg = <0x0 0x994000 0x0 0x4000>;
1423 #size-cells = <0>;
1442 reg = <0x0 0x994000 0x0 0x4000>;
1458 reg = <0x0 0x00ac0000 0x0 0x6000>;
1465 iommus = <&apps_smmu 0x443 0x0>;
1470 reg = <0x0 0xa80000 0x0 0x4000>;
1472 #size-cells = <0>;
1491 reg = <0x0 0xa80000 0x0 0x4000>;
1493 #size-cells = <0>;
1512 reg = <0x0 0xa84000 0x0 0x4000>;
1514 #size-cells = <0>;
1533 reg = <0x0 0xa84000 0x0 0x4000>;
1535 #size-cells = <0>;
1554 reg = <0x0 0xa88000 0x0 0x4000>;
1556 #size-cells = <0>;
1575 reg = <0x0 0xa88000 0x0 0x4000>;
1577 #size-cells = <0>;
1596 reg = <0x0 0xa88000 0x0 0x4000>;
1611 reg = <0x0 0xa8c000 0x0 0x4000>;
1613 #size-cells = <0>;
1632 reg = <0x0 0xa8c000 0x0 0x4000>;
1634 #size-cells = <0>;
1653 reg = <0x0 0x00a8c000 0x0 0x4000>;
1658 interconnects = <&clk_virt MASTER_QUP_CORE_1 0
1659 &clk_virt SLAVE_QUP_CORE_1 0>,
1660 <&gem_noc MASTER_APPSS_PROC 0
1661 &config_noc SLAVE_QUP_1 0>;
1669 reg = <0x0 0xa90000 0x0 0x4000>;
1671 #size-cells = <0>;
1690 reg = <0x0 0xa90000 0x0 0x4000>;
1692 #size-cells = <0>;
1711 reg = <0x0 0xa94000 0x0 0x4000>;
1713 #size-cells = <0>;
1732 reg = <0x0 0xa94000 0x0 0x4000>;
1734 #size-cells = <0>;
1753 reg = <0x0 0x00a94000 0x0 0x4000>;
1768 reg = <0x0 0xa98000 0x0 0x4000>;
1770 #size-cells = <0>;
1790 reg = <0x0 0xbc0000 0x0 0x6000>;
1797 iommus = <&apps_smmu 0x43 0x0>;
1802 reg = <0x0 0xb80000 0x0 0x4000>;
1804 #size-cells = <0>;
1823 reg = <0x0 0xb80000 0x0 0x4000>;
1825 #size-cells = <0>;
1845 reg = <0 0x010d2000 0 0x1000>;
1850 reg = <0x0 0x01d84000 0x0 0x3000>;
1860 iommus = <&apps_smmu 0x100 0x0>;
1879 <0 0>,
1880 <0 0>,
1882 <0 0>,
1883 <0 0>,
1884 <0 0>,
1885 <0 0>;
1892 reg = <0x0 0x01d87000 0x0 0xe10>;
1902 resets = <&ufs_mem_hc 0>;
1904 #phy-cells = <0>;
1911 reg = <0x0 0x01d88000 0x0 0x8000>;
1917 reg = <0x0 0x4002000 0x0 0x1000>,
1918 <0x0 0x16280000 0x0 0x180000>;
1936 reg = <0x0 0x4003000 0x0 0x1000>;
1956 reg = <0x0 0x4004000 0x0 0x1000>;
1972 #size-cells = <0>;
1974 port@0 {
1975 reg = <0>;
1994 reg = <0x0 0x400f000 0x0 0x1000>;
2014 reg = <0x0 0x4041000 0x0 0x1000>;
2030 #size-cells = <0>;
2052 reg = <0x0 0x4042000 0x0 0x1000>;
2068 #size-cells = <0>;
2082 reg = <0x0 0x4045000 0x0 0x1000>;
2098 #size-cells = <0>;
2100 port@0 {
2101 reg = <0>;
2120 reg = <0x0 0x4b04000 0x0 0x1000>;
2136 #size-cells = <0>;
2158 reg = <0x0 0x4b05000 0x0 0x1000>;
2184 reg = <0x0 0x4b06000 0x0 0x1000>;
2191 #size-cells = <0>;
2214 reg = <0x0 0x4b08000 0x0 0x1000>;
2230 #size-cells = <0>;
2232 port@0 {
2233 reg = <0>;
2276 reg = <0x0 0x4b09000 0x0 0x1000>;
2296 reg = <0x0 0x4b0a000 0x0 0x1000>;
2316 reg = <0x0 0x4b0b000 0x0 0x1000>;
2336 reg = <0x0 0x4b0c000 0x0 0x1000>;
2356 reg = <0x0 0x4b0d000 0x0 0x1000>;
2376 reg = <0x0 0x4b13000 0x0 0x1000>;
2384 reg = <0x0 0x6040000 0x0 0x1000>;
2404 reg = <0x0 0x6140000 0x0 0x1000>;
2424 reg = <0x0 0x6240000 0x0 0x1000>;
2444 reg = <0x0 0x6340000 0x0 0x1000>;
2464 reg = <0x0 0x6440000 0x0 0x1000>;
2484 reg = <0x0 0x6540000 0x0 0x1000>;
2504 reg = <0x0 0x6640000 0x0 0x1000>;
2524 reg = <0x0 0x6740000 0x0 0x1000>;
2544 reg = <0x0 0x6800000 0x0 0x1000>;
2560 #size-cells = <0>;
2562 port@0 {
2563 reg = <0>;
2630 reg = <0x0 0x6810000 0x0 0x1000>;
2646 #size-cells = <0>;
2648 port@0 {
2649 reg = <0>;
2668 reg = <0x0 0x6860000 0x0 0x1000>;
2688 reg = <0x0 0x6861000 0x0 0x1000>;
2708 reg = <0x0 0x6863000 0x0 0x1000>;
2724 #size-cells = <0>;
2726 port@0 {
2727 reg = <0>;
2770 reg = <0x0 0x68a0000 0x0 0x1000>;
2790 reg = <0x0 0x68b0000 0x0 0x1000>;
2810 reg = <0x0 0x68c0000 0x0 0x1000>;
2831 reg = <0 0x088e4000 0 0x120>;
2836 #phy-cells = <0>;
2843 reg = <0 0x088e8000 0 0x2000>;
2857 #clock-cells = <0>;
2860 #phy-cells = <0>;
2867 reg = <0 0x0a6f8800 0 0x400>;
2899 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
2900 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
2909 reg = <0 0x0a600000 0 0xe000>;
2911 iommus = <&apps_smmu 0x080 0x0>;
2920 reg = <0 0x088e6000 0 0x120>;
2925 #phy-cells = <0>;
2932 reg = <0 0x088ea000 0 0x2000>;
2946 #clock-cells = <0>;
2949 #phy-cells = <0>;
2956 reg = <0 0x0a8f8800 0 0x400>;
2988 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>,
2989 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
2998 reg = <0 0x0a800000 0 0xe000>;
3000 iommus = <&apps_smmu 0x0a0 0x0>;
3009 reg = <0 0x088e7000 0 0x120>;
3014 #phy-cells = <0>;
3021 reg = <0 0x0a4f8800 0 0x400>;
3051 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>,
3052 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB2 0>;
3061 reg = <0 0x0a400000 0 0xe000>;
3063 iommus = <&apps_smmu 0x020 0x0>;
3071 reg = <0x0 0x01f40000 0x0 0x20000>;
3077 reg = <0x0 0x03d90000 0x0 0xa000>;
3092 reg = <0x0 0x03da0000 0x0 0x20000>;
3127 reg = <0x0 0x08901000 0x0 0xe10>;
3130 #phy-cells = <0>;
3136 reg = <0x0 0x08902000 0x0 0xe10>;
3139 #phy-cells = <0>;
3145 reg = <0x0 0x9091000 0x0 0x1000>;
3155 opp-0 {
3199 reg = <0x0 0x90b5400 0x0 0x600>;
3209 opp-0 {
3230 reg = <0x0 0x90b6400 0x0 0x600>;
3240 reg = <0x0 0x09200000 0x0 0x80000>,
3241 <0x0 0x09300000 0x0 0x80000>,
3242 <0x0 0x09400000 0x0 0x80000>,
3243 <0x0 0x09500000 0x0 0x80000>,
3244 <0x0 0x09600000 0x0 0x80000>,
3245 <0x0 0x09700000 0x0 0x80000>,
3246 <0x0 0x09a00000 0x0 0x80000>;
3259 reg = <0x0 0x0b220000 0x0 0x30000>,
3260 <0x0 0x17c000f0 0x0 0x64>;
3261 qcom,pdc-ranges = <0 480 40>,
3306 reg = <0x0 0x0c251000 0x0 0x1ff>,
3307 <0x0 0x0c224000 0x0 0x8>;
3317 reg = <0x0 0x0c252000 0x0 0x1ff>,
3318 <0x0 0x0c225000 0x0 0x8>;
3328 reg = <0x0 0x0c263000 0x0 0x1ff>,
3329 <0x0 0x0c222000 0x0 0x8>;
3339 reg = <0x0 0x0c265000 0x0 0x1ff>,
3340 <0x0 0x0c223000 0x0 0x8>;
3350 reg = <0x0 0x0c300000 0x0 0x400>;
3355 #clock-cells = <0>;
3360 reg = <0x0 0x0c3f0000 0x0 0x400>;
3365 reg = <0x0 0x0c440000 0x0 0x1100>,
3366 <0x0 0x0c600000 0x0 0x2000000>,
3367 <0x0 0x0e600000 0x0 0x100000>,
3368 <0x0 0x0e700000 0x0 0xa0000>,
3369 <0x0 0x0c40a000 0x0 0x26000>;
3375 qcom,channel = <0>;
3376 qcom,ee = <0>;
3382 #size-cells = <0>;
3387 reg = <0x0 0x0f000000 0x0 0x1000000>;
3393 gpio-ranges = <&tlmm 0 0 149>;
3399 reg = <0x0 0x146d8000 0x0 0x1000>;
3400 ranges = <0x0 0x0 0x146d8000 0x1000>;
3407 reg = <0x94c 0xc8>;
3413 reg = <0x0 0x15000000 0x0 0x100000>;
3552 reg = <0x0 0x15200000 0x0 0x80000>;
3627 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
3628 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
3633 redistributor-stride = <0x0 0x20000>;
3638 reg = <0x0 0x17c10000 0x0 0x1000>;
3640 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
3645 reg = <0x0 0x17c20000 0x0 0x1000>;
3646 ranges = <0x0 0x0 0x0 0x20000000>;
3651 reg = <0x17c21000 0x1000>,
3652 <0x17c22000 0x1000>;
3655 frame-number = <0>;
3659 reg = <0x17c23000 0x1000>;
3666 reg = <0x17c25000 0x1000>;
3673 reg = <0x17c27000 0x1000>;
3680 reg = <0x17c29000 0x1000>;
3687 reg = <0x17c2b000 0x1000>;
3694 reg = <0x17c2d000 0x1000>;
3703 reg = <0x0 0x18200000 0x0 0x10000>,
3704 <0x0 0x18210000 0x0 0x10000>,
3705 <0x0 0x18220000 0x0 0x10000>;
3706 reg-names = "drv-0", "drv-1", "drv-2";
3710 qcom,tcs-offset = <0xd00>;
3715 <CONTROL_TCS 0>;
3737 rpmhpd_opp_ret: opp-0 {
3783 reg = <0x0 0x18591000 0x0 0x1000>,
3784 <0x0 0x18593000 0x0 0x1000>;
3795 reg = <0x0 0x20c00000 0x0 0x10000>;
3798 <&smp2p_gpdsp0_in 0 0>,
3799 <&smp2p_gpdsp0_in 2 0>,
3800 <&smp2p_gpdsp0_in 1 0>,
3801 <&smp2p_gpdsp0_in 3 0>;
3812 interconnects = <&gpdsp_anoc MASTER_DSP0 0
3813 &config_noc SLAVE_CLK_CTL 0>;
3819 qcom,smem-states = <&smp2p_gpdsp0_out 0>;
3838 reg = <0x0 0x21c00000 0x0 0x10000>;
3841 <&smp2p_gpdsp1_in 0 0>,
3842 <&smp2p_gpdsp1_in 2 0>,
3843 <&smp2p_gpdsp1_in 1 0>,
3844 <&smp2p_gpdsp1_in 3 0>;
3855 interconnects = <&gpdsp_anoc MASTER_DSP1 0
3856 &config_noc SLAVE_CLK_CTL 0>;
3862 qcom,smem-states = <&smp2p_gpdsp1_out 0>;
3881 reg = <0x0 0x23000000 0x0 0x10000>,
3882 <0x0 0x23016000 0x0 0x100>;
3909 iommus = <&apps_smmu 0x140 0xf>;
3922 reg = <0x0 0x23040000 0x0 0x10000>,
3923 <0x0 0x23056000 0x0 0x100>;
3950 iommus = <&apps_smmu 0x120 0xf>;
3963 reg = <0x0 0x26300000 0x0 0x10000>;
3966 <&smp2p_cdsp0_in 0 IRQ_TYPE_EDGE_RISING>,
3981 interconnects = <&nspa_noc MASTER_CDSP_PROC 0
3982 &mc_virt SLAVE_EBI1 0>;
3988 qcom,smem-states = <&smp2p_cdsp0_out 0>;
4008 #size-cells = <0>;
4013 iommus = <&apps_smmu 0x2141 0x04a0>,
4014 <&apps_smmu 0x2161 0x04a0>,
4015 <&apps_smmu 0x2181 0x0400>,
4016 <&apps_smmu 0x21c1 0x04a0>,
4017 <&apps_smmu 0x21e1 0x04a0>,
4018 <&apps_smmu 0x2541 0x04a0>,
4019 <&apps_smmu 0x2561 0x04a0>,
4020 <&apps_smmu 0x2581 0x0400>,
4021 <&apps_smmu 0x25c1 0x04a0>,
4022 <&apps_smmu 0x25e1 0x04a0>;
4029 iommus = <&apps_smmu 0x2142 0x04a0>,
4030 <&apps_smmu 0x2162 0x04a0>,
4031 <&apps_smmu 0x2182 0x0400>,
4032 <&apps_smmu 0x21c2 0x04a0>,
4033 <&apps_smmu 0x21e2 0x04a0>,
4034 <&apps_smmu 0x2542 0x04a0>,
4035 <&apps_smmu 0x2562 0x04a0>,
4036 <&apps_smmu 0x2582 0x0400>,
4037 <&apps_smmu 0x25c2 0x04a0>,
4038 <&apps_smmu 0x25e2 0x04a0>;
4045 iommus = <&apps_smmu 0x2143 0x04a0>,
4046 <&apps_smmu 0x2163 0x04a0>,
4047 <&apps_smmu 0x2183 0x0400>,
4048 <&apps_smmu 0x21c3 0x04a0>,
4049 <&apps_smmu 0x21e3 0x04a0>,
4050 <&apps_smmu 0x2543 0x04a0>,
4051 <&apps_smmu 0x2563 0x04a0>,
4052 <&apps_smmu 0x2583 0x0400>,
4053 <&apps_smmu 0x25c3 0x04a0>,
4054 <&apps_smmu 0x25e3 0x04a0>;
4061 iommus = <&apps_smmu 0x2144 0x04a0>,
4062 <&apps_smmu 0x2164 0x04a0>,
4063 <&apps_smmu 0x2184 0x0400>,
4064 <&apps_smmu 0x21c4 0x04a0>,
4065 <&apps_smmu 0x21e4 0x04a0>,
4066 <&apps_smmu 0x2544 0x04a0>,
4067 <&apps_smmu 0x2564 0x04a0>,
4068 <&apps_smmu 0x2584 0x0400>,
4069 <&apps_smmu 0x25c4 0x04a0>,
4070 <&apps_smmu 0x25e4 0x04a0>;
4077 iommus = <&apps_smmu 0x2145 0x04a0>,
4078 <&apps_smmu 0x2165 0x04a0>,
4079 <&apps_smmu 0x2185 0x0400>,
4080 <&apps_smmu 0x21c5 0x04a0>,
4081 <&apps_smmu 0x21e5 0x04a0>,
4082 <&apps_smmu 0x2545 0x04a0>,
4083 <&apps_smmu 0x2565 0x04a0>,
4084 <&apps_smmu 0x2585 0x0400>,
4085 <&apps_smmu 0x25c5 0x04a0>,
4086 <&apps_smmu 0x25e5 0x04a0>;
4093 iommus = <&apps_smmu 0x2146 0x04a0>,
4094 <&apps_smmu 0x2166 0x04a0>,
4095 <&apps_smmu 0x2186 0x0400>,
4096 <&apps_smmu 0x21c6 0x04a0>,
4097 <&apps_smmu 0x21e6 0x04a0>,
4098 <&apps_smmu 0x2546 0x04a0>,
4099 <&apps_smmu 0x2566 0x04a0>,
4100 <&apps_smmu 0x2586 0x0400>,
4101 <&apps_smmu 0x25c6 0x04a0>,
4102 <&apps_smmu 0x25e6 0x04a0>;
4109 iommus = <&apps_smmu 0x2147 0x04a0>,
4110 <&apps_smmu 0x2167 0x04a0>,
4111 <&apps_smmu 0x2187 0x0400>,
4112 <&apps_smmu 0x21c7 0x04a0>,
4113 <&apps_smmu 0x21e7 0x04a0>,
4114 <&apps_smmu 0x2547 0x04a0>,
4115 <&apps_smmu 0x2567 0x04a0>,
4116 <&apps_smmu 0x2587 0x0400>,
4117 <&apps_smmu 0x25c7 0x04a0>,
4118 <&apps_smmu 0x25e7 0x04a0>;
4125 iommus = <&apps_smmu 0x2148 0x04a0>,
4126 <&apps_smmu 0x2168 0x04a0>,
4127 <&apps_smmu 0x2188 0x0400>,
4128 <&apps_smmu 0x21c8 0x04a0>,
4129 <&apps_smmu 0x21e8 0x04a0>,
4130 <&apps_smmu 0x2548 0x04a0>,
4131 <&apps_smmu 0x2568 0x04a0>,
4132 <&apps_smmu 0x2588 0x0400>,
4133 <&apps_smmu 0x25c8 0x04a0>,
4134 <&apps_smmu 0x25e8 0x04a0>;
4141 iommus = <&apps_smmu 0x2149 0x04a0>,
4142 <&apps_smmu 0x2169 0x04a0>,
4143 <&apps_smmu 0x2189 0x0400>,
4144 <&apps_smmu 0x21c9 0x04a0>,
4145 <&apps_smmu 0x21e9 0x04a0>,
4146 <&apps_smmu 0x2549 0x04a0>,
4147 <&apps_smmu 0x2569 0x04a0>,
4148 <&apps_smmu 0x2589 0x0400>,
4149 <&apps_smmu 0x25c9 0x04a0>,
4150 <&apps_smmu 0x25e9 0x04a0>;
4157 iommus = <&apps_smmu 0x214a 0x04a0>,
4158 <&apps_smmu 0x216a 0x04a0>,
4159 <&apps_smmu 0x218a 0x0400>,
4160 <&apps_smmu 0x21ca 0x04a0>,
4161 <&apps_smmu 0x21ea 0x04a0>,
4162 <&apps_smmu 0x254a 0x04a0>,
4163 <&apps_smmu 0x256a 0x04a0>,
4164 <&apps_smmu 0x258a 0x0400>,
4165 <&apps_smmu 0x25ca 0x04a0>,
4166 <&apps_smmu 0x25ea 0x04a0>;
4173 iommus = <&apps_smmu 0x214b 0x04a0>,
4174 <&apps_smmu 0x216b 0x04a0>,
4175 <&apps_smmu 0x218b 0x0400>,
4176 <&apps_smmu 0x21cb 0x04a0>,
4177 <&apps_smmu 0x21eb 0x04a0>,
4178 <&apps_smmu 0x254b 0x04a0>,
4179 <&apps_smmu 0x256b 0x04a0>,
4180 <&apps_smmu 0x258b 0x0400>,
4181 <&apps_smmu 0x25cb 0x04a0>,
4182 <&apps_smmu 0x25eb 0x04a0>;
4191 reg = <0x0 0x2A300000 0x0 0x10000>;
4194 <&smp2p_cdsp1_in 0 IRQ_TYPE_EDGE_RISING>,
4209 interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0
4210 &mc_virt SLAVE_EBI1 0>;
4216 qcom,smem-states = <&smp2p_cdsp1_out 0>;
4236 #size-cells = <0>;
4241 iommus = <&apps_smmu 0x2941 0x04a0>,
4242 <&apps_smmu 0x2961 0x04a0>,
4243 <&apps_smmu 0x2981 0x0400>,
4244 <&apps_smmu 0x29c1 0x04a0>,
4245 <&apps_smmu 0x29e1 0x04a0>,
4246 <&apps_smmu 0x2d41 0x04a0>,
4247 <&apps_smmu 0x2d61 0x04a0>,
4248 <&apps_smmu 0x2d81 0x0400>,
4249 <&apps_smmu 0x2dc1 0x04a0>,
4250 <&apps_smmu 0x2de1 0x04a0>;
4257 iommus = <&apps_smmu 0x2942 0x04a0>,
4258 <&apps_smmu 0x2962 0x04a0>,
4259 <&apps_smmu 0x2982 0x0400>,
4260 <&apps_smmu 0x29c2 0x04a0>,
4261 <&apps_smmu 0x29e2 0x04a0>,
4262 <&apps_smmu 0x2d42 0x04a0>,
4263 <&apps_smmu 0x2d62 0x04a0>,
4264 <&apps_smmu 0x2d82 0x0400>,
4265 <&apps_smmu 0x2dc2 0x04a0>,
4266 <&apps_smmu 0x2de2 0x04a0>;
4273 iommus = <&apps_smmu 0x2943 0x04a0>,
4274 <&apps_smmu 0x2963 0x04a0>,
4275 <&apps_smmu 0x2983 0x0400>,
4276 <&apps_smmu 0x29c3 0x04a0>,
4277 <&apps_smmu 0x29e3 0x04a0>,
4278 <&apps_smmu 0x2d43 0x04a0>,
4279 <&apps_smmu 0x2d63 0x04a0>,
4280 <&apps_smmu 0x2d83 0x0400>,
4281 <&apps_smmu 0x2dc3 0x04a0>,
4282 <&apps_smmu 0x2de3 0x04a0>;
4289 iommus = <&apps_smmu 0x2944 0x04a0>,
4290 <&apps_smmu 0x2964 0x04a0>,
4291 <&apps_smmu 0x2984 0x0400>,
4292 <&apps_smmu 0x29c4 0x04a0>,
4293 <&apps_smmu 0x29e4 0x04a0>,
4294 <&apps_smmu 0x2d44 0x04a0>,
4295 <&apps_smmu 0x2d64 0x04a0>,
4296 <&apps_smmu 0x2d84 0x0400>,
4297 <&apps_smmu 0x2dc4 0x04a0>,
4298 <&apps_smmu 0x2de4 0x04a0>;
4305 iommus = <&apps_smmu 0x2945 0x04a0>,
4306 <&apps_smmu 0x2965 0x04a0>,
4307 <&apps_smmu 0x2985 0x0400>,
4308 <&apps_smmu 0x29c5 0x04a0>,
4309 <&apps_smmu 0x29e5 0x04a0>,
4310 <&apps_smmu 0x2d45 0x04a0>,
4311 <&apps_smmu 0x2d65 0x04a0>,
4312 <&apps_smmu 0x2d85 0x0400>,
4313 <&apps_smmu 0x2dc5 0x04a0>,
4314 <&apps_smmu 0x2de5 0x04a0>;
4321 iommus = <&apps_smmu 0x2946 0x04a0>,
4322 <&apps_smmu 0x2966 0x04a0>,
4323 <&apps_smmu 0x2986 0x0400>,
4324 <&apps_smmu 0x29c6 0x04a0>,
4325 <&apps_smmu 0x29e6 0x04a0>,
4326 <&apps_smmu 0x2d46 0x04a0>,
4327 <&apps_smmu 0x2d66 0x04a0>,
4328 <&apps_smmu 0x2d86 0x0400>,
4329 <&apps_smmu 0x2dc6 0x04a0>,
4330 <&apps_smmu 0x2de6 0x04a0>;
4337 iommus = <&apps_smmu 0x2947 0x04a0>,
4338 <&apps_smmu 0x2967 0x04a0>,
4339 <&apps_smmu 0x2987 0x0400>,
4340 <&apps_smmu 0x29c7 0x04a0>,
4341 <&apps_smmu 0x29e7 0x04a0>,
4342 <&apps_smmu 0x2d47 0x04a0>,
4343 <&apps_smmu 0x2d67 0x04a0>,
4344 <&apps_smmu 0x2d87 0x0400>,
4345 <&apps_smmu 0x2dc7 0x04a0>,
4346 <&apps_smmu 0x2de7 0x04a0>;
4353 iommus = <&apps_smmu 0x2948 0x04a0>,
4354 <&apps_smmu 0x2968 0x04a0>,
4355 <&apps_smmu 0x2988 0x0400>,
4356 <&apps_smmu 0x29c8 0x04a0>,
4357 <&apps_smmu 0x29e8 0x04a0>,
4358 <&apps_smmu 0x2d48 0x04a0>,
4359 <&apps_smmu 0x2d68 0x04a0>,
4360 <&apps_smmu 0x2d88 0x0400>,
4361 <&apps_smmu 0x2dc8 0x04a0>,
4362 <&apps_smmu 0x2de8 0x04a0>;
4369 iommus = <&apps_smmu 0x2949 0x04a0>,
4370 <&apps_smmu 0x2969 0x04a0>,
4371 <&apps_smmu 0x2989 0x0400>,
4372 <&apps_smmu 0x29c9 0x04a0>,
4373 <&apps_smmu 0x29e9 0x04a0>,
4374 <&apps_smmu 0x2d49 0x04a0>,
4375 <&apps_smmu 0x2d69 0x04a0>,
4376 <&apps_smmu 0x2d89 0x0400>,
4377 <&apps_smmu 0x2dc9 0x04a0>,
4378 <&apps_smmu 0x2de9 0x04a0>;
4385 iommus = <&apps_smmu 0x294a 0x04a0>,
4386 <&apps_smmu 0x296a 0x04a0>,
4387 <&apps_smmu 0x298a 0x0400>,
4388 <&apps_smmu 0x29ca 0x04a0>,
4389 <&apps_smmu 0x29ea 0x04a0>,
4390 <&apps_smmu 0x2d4a 0x04a0>,
4391 <&apps_smmu 0x2d6a 0x04a0>,
4392 <&apps_smmu 0x2d8a 0x0400>,
4393 <&apps_smmu 0x2dca 0x04a0>,
4394 <&apps_smmu 0x2dea 0x04a0>;
4401 iommus = <&apps_smmu 0x294b 0x04a0>,
4402 <&apps_smmu 0x296b 0x04a0>,
4403 <&apps_smmu 0x298b 0x0400>,
4404 <&apps_smmu 0x29cb 0x04a0>,
4405 <&apps_smmu 0x29eb 0x04a0>,
4406 <&apps_smmu 0x2d4b 0x04a0>,
4407 <&apps_smmu 0x2d6b 0x04a0>,
4408 <&apps_smmu 0x2d8b 0x0400>,
4409 <&apps_smmu 0x2dcb 0x04a0>,
4410 <&apps_smmu 0x2deb 0x04a0>;
4417 iommus = <&apps_smmu 0x294c 0x04a0>,
4418 <&apps_smmu 0x296c 0x04a0>,
4419 <&apps_smmu 0x298c 0x0400>,
4420 <&apps_smmu 0x29cc 0x04a0>,
4421 <&apps_smmu 0x29ec 0x04a0>,
4422 <&apps_smmu 0x2d4c 0x04a0>,
4423 <&apps_smmu 0x2d6c 0x04a0>,
4424 <&apps_smmu 0x2d8c 0x0400>,
4425 <&apps_smmu 0x2dcc 0x04a0>,
4426 <&apps_smmu 0x2dec 0x04a0>;
4433 iommus = <&apps_smmu 0x294d 0x04a0>,
4434 <&apps_smmu 0x296d 0x04a0>,
4435 <&apps_smmu 0x298d 0x0400>,
4436 <&apps_smmu 0x29Cd 0x04a0>,
4437 <&apps_smmu 0x29ed 0x04a0>,
4438 <&apps_smmu 0x2d4d 0x04a0>,
4439 <&apps_smmu 0x2d6d 0x04a0>,
4440 <&apps_smmu 0x2d8d 0x0400>,
4441 <&apps_smmu 0x2dcd 0x04a0>,
4442 <&apps_smmu 0x2ded 0x04a0>;
4451 reg = <0x0 0x30000000 0x0 0x100>;
4454 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
4468 interconnects = <&lpass_ag_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>;
4474 qcom,smem-states = <&smp2p_adsp_out 0>;
4497 #size-cells = <0>;
4502 iommus = <&apps_smmu 0x3003 0x0>;
4509 iommus = <&apps_smmu 0x3004 0x0>;
4516 iommus = <&apps_smmu 0x3005 0x0>;
4526 aoss-0-thermal {
4527 thermal-sensors = <&tsens0 0>;
4544 cpu-0-0-0-thermal {
4564 cpu-0-1-0-thermal {
4584 cpu-0-2-0-thermal {
4604 cpu-0-3-0-thermal {
4624 gpuss-0-thermal {
4702 camss-0-thermal {
4720 pcie-0-thermal {
4738 cpuss-0-0-thermal {
4757 thermal-sensors = <&tsens1 0>;
4774 cpu-0-0-1-thermal {
4794 cpu-0-1-1-thermal {
4814 cpu-0-2-1-thermal {
4834 cpu-0-3-1-thermal {
4968 cpuss-0-1-thermal {
4987 thermal-sensors = <&tsens2 0>;
5004 cpu-1-0-0-thermal {
5024 cpu-1-1-0-thermal {
5044 cpu-1-2-0-thermal {
5064 cpu-1-3-0-thermal {
5084 nsp-0-0-0-thermal {
5104 nsp-0-1-0-thermal {
5124 nsp-0-2-0-thermal {
5144 nsp-1-0-0-thermal {
5164 nsp-1-1-0-thermal {
5184 nsp-1-2-0-thermal {
5204 ddrss-0-thermal {
5222 cpuss-1-0-thermal {
5241 thermal-sensors = <&tsens3 0>;
5258 cpu-1-0-1-thermal {
5338 nsp-0-0-1-thermal {
5358 nsp-0-1-1-thermal {
5378 nsp-0-2-1-thermal {
5398 nsp-1-0-1-thermal {
5505 reg = <0x0 0x01c00000 0x0 0x3000>,
5506 <0x0 0x40000000 0x0 0xf20>,
5507 <0x0 0x40000f20 0x0 0xa8>,
5508 <0x0 0x40001000 0x0 0x4000>,
5509 <0x0 0x40100000 0x0 0x100000>,
5510 <0x0 0x01c03000 0x0 0x1000>;
5516 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
5517 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
5518 bus-range = <0x00 0xff>;
5522 linux,pci-domain = <0>;
5536 interrupt-map-mask = <0 0 0 0x7>;
5537 interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
5538 <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
5539 <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
5540 <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
5557 interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
5558 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>;
5561 iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
5562 <0x100 &pcie_smmu 0x0001 0x1>;
5573 pcie@0 {
5575 reg = <0x0 0x0 0x0 0x0 0x0>;
5576 bus-range = <0x01 0xff>;
5586 reg = <0x0 0x01c00000 0x0 0x3000>,
5587 <0x0 0x40000000 0x0 0xf20>,
5588 <0x0 0x40000f20 0x0 0xa8>,
5589 <0x0 0x40001000 0x0 0x4000>,
5590 <0x0 0x40200000 0x0 0x100000>,
5591 <0x0 0x01c03000 0x0 0x1000>,
5592 <0x0 0x40005000 0x0 0x2000>;
5614 interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
5615 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>;
5619 iommus = <&pcie_smmu 0x0000 0x7f>;
5633 reg = <0x0 0x1c04000 0x0 0x2000>;
5652 #clock-cells = <0>;
5655 #phy-cells = <0>;
5662 reg = <0x0 0x01c10000 0x0 0x3000>,
5663 <0x0 0x60000000 0x0 0xf20>,
5664 <0x0 0x60000f20 0x0 0xa8>,
5665 <0x0 0x60001000 0x0 0x4000>,
5666 <0x0 0x60100000 0x0 0x100000>,
5667 <0x0 0x01c13000 0x0 0x1000>;
5673 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
5674 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>;
5675 bus-range = <0x00 0xff>;
5693 interrupt-map-mask = <0 0 0 0x7>;
5694 interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
5695 <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
5696 <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
5697 <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
5714 interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>,
5715 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>;
5718 iommu-map = <0x0 &pcie_smmu 0x0080 0x1>,
5719 <0x100 &pcie_smmu 0x0081 0x1>;
5730 pcie@0 {
5732 reg = <0x0 0x0 0x0 0x0 0x0>;
5733 bus-range = <0x01 0xff>;
5743 reg = <0x0 0x01c10000 0x0 0x3000>,
5744 <0x0 0x60000000 0x0 0xf20>,
5745 <0x0 0x60000f20 0x0 0xa8>,
5746 <0x0 0x60001000 0x0 0x4000>,
5747 <0x0 0x60200000 0x0 0x100000>,
5748 <0x0 0x01c13000 0x0 0x1000>,
5749 <0x0 0x60005000 0x0 0x2000>;
5771 interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>,
5772 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>;
5776 iommus = <&pcie_smmu 0x80 0x7f>;
5790 reg = <0x0 0x1c14000 0x0 0x4000>;
5809 #clock-cells = <0>;
5812 #phy-cells = <0>;