Lines Matching +full:0 +full:x00408000
32 #clock-cells = <0>;
38 #clock-cells = <0>;
44 #size-cells = <0>;
46 CPU0: cpu@0 {
49 reg = <0x0 0x0>;
50 clocks = <&cpufreq_hw 0>;
54 qcom,freq-domain = <&cpufreq_hw 0>;
75 reg = <0x0 0x100>;
76 clocks = <&cpufreq_hw 0>;
80 qcom,freq-domain = <&cpufreq_hw 0>;
96 reg = <0x0 0x200>;
97 clocks = <&cpufreq_hw 0>;
101 qcom,freq-domain = <&cpufreq_hw 0>;
117 reg = <0x0 0x300>;
118 clocks = <&cpufreq_hw 0>;
122 qcom,freq-domain = <&cpufreq_hw 0>;
158 CPU_OFF: cpu-sleep-0 {
163 arm,psci-suspend-param = <0x40000003>;
172 arm,psci-suspend-param = <0x40000004>;
179 CLUSTER_SLEEP_0: cluster-sleep-0 {
181 arm,psci-suspend-param = <0x41000044>;
189 arm,psci-suspend-param = <0x41001344>;
197 arm,psci-suspend-param = <0x4100b344>;
211 clk_virt: interconnect-0 {
226 reg = <0x0 0x80000000 0x0 0x0>;
239 #power-domain-cells = <0>;
245 #power-domain-cells = <0>;
251 #power-domain-cells = <0>;
257 #power-domain-cells = <0>;
263 #power-domain-cells = <0>;
274 reg = <0x0 0x80000000 0x0 0x800000>;
279 reg = <0x0 0x80800000 0x0 0x200000>;
284 reg = <0x0 0x81380000 0x0 0x80000>;
289 reg = <0x0 0x814e0000 0x0 0x2a0000>;
294 reg = <0x0 0x81780000 0x0 0xa00000>;
299 reg = <0x0 0x87a00000 0x0 0x1c0000>;
304 reg = <0x0 0x87c00000 0x0 0x100000>;
309 reg = <0x0 0x87d00000 0x0 0x40000>;
314 reg = <0x0 0x87d40000 0x0 0x40000>;
319 reg = <0x0 0x87d80000 0x0 0x10000>;
324 reg = <0x0 0x87e00000 0x0 0x20000>;
329 reg = <0x0 0x87e20000 0x0 0xc0000>;
335 reg = <0x0 0x87ee0000 0x0 0x20000>;
340 reg = <0x0 0x87f00000 0x0 0x20000>;
345 reg = <0x0 0x87f20000 0x0 0x10000>;
350 reg = <0x0 0x87f30000 0x0 0x1000>;
355 reg = <0x0 0x87f31000 0x0 0x40000>;
360 reg = <0x0 0x87f71000 0x0 0x4000>;
365 reg = <0x0 0x87f75000 0x0 0x10000>;
370 reg = <0x0 0x88500000 0x0 0x300000>;
375 reg = <0x0 0x88800000 0x0 0x300000>;
381 reg = <0x0 0x88b00000 0x0 0x400000>;
386 reg = <0x0 0x88f00000 0x0 0x2500000>;
391 reg = <0x0 0x8b400000 0x0 0x2b80000>;
396 reg = <0x0 0x8df80000 0x0 0x80000>;
401 reg = <0x0 0x8e000000 0x0 0xf100000>;
406 reg = <0x0 0xbdb00000 0x0 0x2000000>;
411 reg = <0x0 0xbfb00000 0x0 0x100000>;
416 reg = <0x0 0xbfc00000 0x0 0x400000>;
430 qcom,local-pid = <0>;
462 soc: soc@0 {
466 ranges = <0 0 0 0 0x10 0>;
467 dma-ranges = <0 0 0 0 0x10 0>;
471 reg = <0x0 0x0080000 0x0 0x1f7400>;
474 <0>,
475 <0>,
476 <0>,
477 <0>,
478 <0>,
479 <0>,
480 <0>,
481 <0>,
482 <0>,
483 <0>,
484 <0>,
485 <0>,
486 <0>;
494 reg = <0 0x00408000 0 0x1000>;
503 reg = <0x0 0x00900000 0x0 0x60000>;
518 dma-channel-mask = <0x7f>;
519 iommus = <&apps_smmu 0xf6 0x0>;
525 reg = <0x0 0x009c0000 0x0 0x2000>;
530 iommus = <&apps_smmu 0xe3 0x0>;
541 reg = <0x0 0x00980000 0x0 0x4000>;
546 #size-cells = <0>;
547 pinctrl-0 = <&qup_i2c0_data_clk>;
556 dmas = <&gpi_dma 0 0 QCOM_GPI_I2C>,
557 <&gpi_dma 1 0 QCOM_GPI_I2C>;
564 reg = <0x0 0x00980000 0x0 0x4000>;
569 #size-cells = <0>;
570 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
579 dmas = <&gpi_dma 0 0 QCOM_GPI_SPI>,
580 <&gpi_dma 1 0 QCOM_GPI_SPI>;
587 reg = <0x0 0x00984000 0x0 0x4000>;
597 pinctrl-0 = <&qupv3_se1_2uart_active>;
606 reg = <0x0 0x00988000 0x0 0x4000>;
611 #size-cells = <0>;
612 pinctrl-0 = <&qup_i2c2_data_clk>;
621 dmas = <&gpi_dma 0 2 QCOM_GPI_I2C>,
629 reg = <0x0 0x00988000 0x0 0x4000>;
634 #size-cells = <0>;
635 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
644 dmas = <&gpi_dma 0 2 QCOM_GPI_SPI>,
652 reg = <0x0 0x0098c000 0x0 0x4000>;
657 #size-cells = <0>;
658 pinctrl-0 = <&qup_i2c3_data_clk>;
667 dmas = <&gpi_dma 0 3 QCOM_GPI_I2C>,
675 reg = <0x0 0x0098c000 0x0 0x4000>;
680 #size-cells = <0>;
681 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
690 dmas = <&gpi_dma 0 3 QCOM_GPI_SPI>,
698 reg = <0x0 0x00990000 0x0 0x4000>;
702 pinctrl-0 = <&qup_uart4_default>, <&qup_uart4_cts_rts>;
714 reg = <0x0 0x00994000 0x0 0x4000>;
719 #size-cells = <0>;
720 pinctrl-0 = <&qup_i2c5_data_clk>;
729 dmas = <&gpi_dma 0 5 QCOM_GPI_I2C>,
737 reg = <0x0 0x00998000 0x0 0x4000>;
742 #size-cells = <0>;
743 pinctrl-0 = <&qup_i2c6_data_clk>;
752 dmas = <&gpi_dma 0 6 QCOM_GPI_I2C>,
760 reg = <0x0 0x00998000 0x0 0x4000>;
765 #size-cells = <0>;
766 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
775 dmas = <&gpi_dma 0 6 QCOM_GPI_SPI>,
783 reg = <0x0 0x0099c000 0x0 0x4000>;
788 #size-cells = <0>;
789 pinctrl-0 = <&qup_i2c7_data_clk>;
798 dmas = <&gpi_dma 0 7 QCOM_GPI_I2C>,
806 reg = <0x0 0x0099c000 0x0 0x4000>;
811 #size-cells = <0>;
812 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
821 dmas = <&gpi_dma 0 7 QCOM_GPI_SPI>,
830 reg = <0x0 0x00ff4000 0x0 0x154>;
831 #phy-cells = <0>;
843 reg = <0x0 0x00ff6000 0x0 0x2000>;
861 #clock-cells = <0>;
864 #phy-cells = <0>;
871 reg = <0x0 0x01640000 0x0 0x4b400>;
878 reg = <0x0 0x016c0000 0x0 0x14200>;
885 reg = <0x0 0x01f40000 0x0 0x40000>;
891 reg = <0x0 0x01fc0000 0x0 0x30000>;
896 reg = <0 0x04080000 0 0x4040>;
899 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
925 qcom,smem-states = <&smp2p_modem_out 0>;
943 reg = <0x0 0x08804000 0x0 0x1000>;
956 iommus = <&apps_smmu 0x00a0 0x0>;
957 qcom,dll-config = <0x0007442c>;
958 qcom,ddr-config = <0x80040868>;
970 sdhci-caps-mask = <0x3 0>;
991 reg = <0x0 0x0a6f8800 0x0 0x400>;
1035 reg = <0x0 0x0a600000 0x0 0xcd00>;
1037 iommus = <&apps_smmu 0x80 0x0>;
1047 #size-cells = <0>;
1049 port@0 {
1050 reg = <0>;
1068 reg = <0x0 0xb220000 0x0 0x30000>,
1069 <0x0 0x174000f0 0x0 0x64>;
1070 qcom,pdc-ranges = <0 147 52>,
1080 reg = <0 0x0c310000 0 0x1000>;
1086 #clock-cells = <0>;
1091 reg = <0x0 0x0c400000 0x0 0x3000>,
1092 <0x0 0x0c500000 0x0 0x400000>,
1093 <0x0 0x0c440000 0x0 0x80000>,
1094 <0x0 0x0c4c0000 0x0 0x10000>,
1095 <0x0 0x0c42d000 0x0 0x4000>;
1103 qcom,ee = <0>;
1104 qcom,channel = <0>;
1105 qcom,bus-id = <0>;
1107 #size-cells = <0>;
1114 reg = <0x0 0x0f000000 0x0 0x400000>;
1118 gpio-ranges = <&tlmm 0 0 133>;
1328 reg = <0x0 0x15000000 0x0 0x40000>;
1372 redistributor-stride = <0x0 0x20000>;
1373 reg = <0x0 0x17200000 0x0 0x10000>,
1374 <0x0 0x17260000 0x0 0x80000>;
1380 reg = <0x0 0x17420000 0x0 0x1000>;
1383 ranges = <0 0 0 0x20000000>;
1386 reg = <0x17421000 0x1000>,
1387 <0x17422000 0x1000>;
1388 frame-number = <0>;
1394 reg = <0x17423000 0x1000>;
1401 reg = <0x17425000 0x1000>;
1408 reg = <0x17427000 0x1000>;
1415 reg = <0x17429000 0x1000>;
1422 reg = <0x1742b000 0x1000>;
1429 reg = <0x1742d000 0x1000>;
1439 reg = <0x0 0x17a00000 0x0 0x10000>,
1440 <0x0 0x17a10000 0x0 0x10000>,
1441 <0x0 0x17a20000 0x0 0x10000>;
1442 reg-names = "drv-0", "drv-1", "drv-2";
1448 qcom,tcs-offset = <0xd00>;
1453 <CONTROL_TCS 0>;
1519 reg = <0x0 0x17d91000 0x0 0x1000>;
1526 interrupt-names = "dcvsh-irq-0";
1533 reg = <0x0 0x190e0000 0x0 0x8200>;
1540 reg = <0x0 0x19100000 0x0 0x34080>;