Lines Matching +full:0 +full:x00408000
29 #clock-cells = <0>;
36 #clock-cells = <0>;
44 #size-cells = <0>;
46 CPU0: cpu@0 {
49 reg = <0x0 0x0>;
53 clocks = <&kryocc 0>;
68 reg = <0x0 0x1>;
72 clocks = <&kryocc 0>;
82 reg = <0x0 0x100>;
101 reg = <0x0 0x101>;
137 CPU_SLEEP_0: cpu-sleep-0 {
140 arm,psci-suspend-param = <0x00000004>;
156 opp-supported-hw = <0xf>;
162 opp-supported-hw = <0xf>;
168 opp-supported-hw = <0xf>;
174 opp-supported-hw = <0xf>;
180 opp-supported-hw = <0xf>;
186 opp-supported-hw = <0xf>;
192 opp-supported-hw = <0xf>;
198 opp-supported-hw = <0xf>;
204 opp-supported-hw = <0xf>;
210 opp-supported-hw = <0xf>;
216 opp-supported-hw = <0xf>;
222 opp-supported-hw = <0xf>;
228 opp-supported-hw = <0xd>;
234 opp-supported-hw = <0x2>;
240 opp-supported-hw = <0xd>;
246 opp-supported-hw = <0x9>;
252 opp-supported-hw = <0x04>;
258 opp-supported-hw = <0x9>;
272 opp-supported-hw = <0xf>;
278 opp-supported-hw = <0xf>;
284 opp-supported-hw = <0xf>;
290 opp-supported-hw = <0xf>;
296 opp-supported-hw = <0xf>;
302 opp-supported-hw = <0xf>;
308 opp-supported-hw = <0xf>;
314 opp-supported-hw = <0xf>;
320 opp-supported-hw = <0xf>;
326 opp-supported-hw = <0xf>;
332 opp-supported-hw = <0xf>;
338 opp-supported-hw = <0xf>;
344 opp-supported-hw = <0xf>;
350 opp-supported-hw = <0xf>;
356 opp-supported-hw = <0xf>;
362 opp-supported-hw = <0xf>;
368 opp-supported-hw = <0xf>;
374 opp-supported-hw = <0xf>;
380 opp-supported-hw = <0xf>;
386 opp-supported-hw = <0xf>;
392 opp-supported-hw = <0xe>;
398 opp-supported-hw = <0x1>;
404 opp-supported-hw = <0x4>;
410 opp-supported-hw = <0x1>;
416 opp-supported-hw = <0x1>;
422 opp-supported-hw = <0x1>;
428 opp-supported-hw = <0x1>;
437 qcom,dload-mode = <&tcsr_2 0x13000>;
444 reg = <0x0 0x80000000 0x0 0x0>;
472 mboxes = <&apcs_glb 0>;
528 reg = <0x0 0x85800000 0x0 0x600000>;
533 reg = <0x0 0x85e00000 0x0 0x200000>;
538 reg = <0x0 0x86000000 0x0 0x200000>;
543 reg = <0x0 0x86200000 0x0 0x2600000>;
550 size = <0x0 0x200000>;
551 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
559 reg = <0x0 0x88800000 0x0 0x6200000>;
564 reg = <0x0 0x8ea00000 0x0 0x1b00000>;
569 reg = <0x0 0x90500000 0x0 0xa00000>;
575 reg = <0x0 0x90f00000 0x0 0x100000>;
580 reg = <0x0 0x91000000 0x0 0x500000>;
585 reg = <0x0 0x91500000 0x0 0x200000>;
590 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
591 size = <0x0 0x4000>;
610 qcom,local-pid = <0>;
634 qcom,local-pid = <0>;
658 qcom,local-pid = <0>;
674 soc: soc@0 {
677 ranges = <0 0 0 0xffffffff>;
682 reg = <0x00034000 0x488>;
685 ranges = <0x0 0x00034000 0x4000>;
700 reg = <0x1000 0x130>,
701 <0x1200 0x200>,
702 <0x1400 0x1dc>;
709 #clock-cells = <0>;
712 #phy-cells = <0>;
716 reg = <0x2000 0x130>,
717 <0x2200 0x200>,
718 <0x2400 0x1dc>;
725 #clock-cells = <0>;
728 #phy-cells = <0>;
732 reg = <0x3000 0x130>,
733 <0x3200 0x200>,
734 <0x3400 0x1dc>;
741 #clock-cells = <0>;
744 #phy-cells = <0>;
750 reg = <0x00068000 0x6000>;
755 reg = <0x00074000 0x8ff>;
760 reg = <0x24e 0x2>;
765 reg = <0x24f 0x1>;
770 reg = <0x133 0x1>;
777 reg = <0x00083000 0x1000>;
787 reg = <0x00300000 0x90000>;
796 <&ufsphy 0>,
813 reg = <0x00408000 0x5a000>;
819 reg = <0x004a9000 0x1000>, /* TM */
820 <0x004a8000 0x1000>; /* SROT */
830 reg = <0x004ad000 0x1000>, /* TM */
831 <0x004ac000 0x1000>; /* SROT */
841 reg = <0x00644000 0x24000>;
846 qcom,ee = <0>;
852 reg = <0x0067a000 0x6000>;
863 reg = <0x00500000 0x1000>;
869 reg = <0x00524000 0x1c000>;
875 reg = <0x00543000 0x6000>;
888 reg = <0x00562000 0x5000>;
894 reg = <0x00583000 0x7000>;
903 reg = <0x005a4000 0x1c000>;
911 reg = <0x005c0000 0x3000>;
917 reg = <0x00740000 0x20000>;
923 reg = <0x00760000 0x20000>;
928 reg = <0x007a0000 0x18000>;
936 reg = <0x008c0000 0x40000>;
941 <&mdss_dsi0_phy 0>,
943 <&mdss_dsi1_phy 0>,
968 reg = <0x00900000 0x1000>,
969 <0x009b0000 0x1040>,
970 <0x009b8000 0x1040>;
995 reg = <0x00901000 0x90000>;
999 interrupts = <0>;
1012 iommus = <&mdp_smmu 0>;
1026 #size-cells = <0>;
1028 port@0 {
1029 reg = <0>;
1054 reg = <0x00994000 0x400>;
1075 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
1081 #size-cells = <0>;
1085 #size-cells = <0>;
1087 port@0 {
1088 reg = <0>;
1104 reg = <0x00994400 0x100>,
1105 <0x00994500 0x300>,
1106 <0x00994800 0x188>;
1112 #phy-cells = <0>;
1122 reg = <0x00996000 0x400>;
1143 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
1149 #size-cells = <0>;
1153 #size-cells = <0>;
1155 port@0 {
1156 reg = <0>;
1172 reg = <0x00996400 0x100>,
1173 <0x00996500 0x300>,
1174 <0x00996800 0x188>;
1180 #phy-cells = <0>;
1189 reg = <0x009a0000 0x50c>,
1190 <0x00070000 0x6158>,
1191 <0x009e0000 0xfff>;
1218 #size-cells = <0>;
1220 port@0 {
1221 reg = <0>;
1230 #phy-cells = <0>;
1232 reg = <0x009a0600 0x1c4>,
1233 <0x009a0a00 0x124>,
1234 <0x009a0c00 0x124>,
1235 <0x009a0e00 0x124>,
1236 <0x009a1000 0x124>,
1237 <0x009a1200 0x0c8>;
1252 #clock-cells = <0>;
1261 reg = <0x00b00000 0x3f000>;
1282 iommus = <&adreno_smmu 0>;
1297 * 624Mhz is only available on speed bins 0 and 3.
1298 * 560Mhz is only available on speed bins 0, 2 and 3.
1303 opp-supported-hw = <0x09>;
1307 opp-supported-hw = <0x0d>;
1311 opp-supported-hw = <0xff>;
1315 opp-supported-hw = <0xff>;
1319 opp-supported-hw = <0xff>;
1323 opp-supported-hw = <0xff>;
1327 opp-supported-hw = <0xff>;
1338 reg = <0x01010000 0x300000>;
1341 gpio-ranges = <&tlmm 0 0 150>;
1857 reg = <0x00290000 0x10000>;
1862 reg = <0x0400f000 0x1000>,
1863 <0x04400000 0x800000>,
1864 <0x04c00000 0x800000>,
1865 <0x05800000 0x200000>,
1866 <0x0400a000 0x002100>;
1870 qcom,ee = <0>;
1871 qcom,channel = <0>;
1873 #size-cells = <0>;
1878 bus@0 {
1883 ranges = <0x0 0x0 0xffffffff>;
1889 bus-range = <0x00 0xff>;
1892 reg = <0x00600000 0x2000>,
1893 <0x0c000000 0xf1d>,
1894 <0x0c000f20 0xa8>,
1895 <0x0c100000 0x100000>;
1903 ranges = <0x01000000 0x0 0x00000000 0x0c200000 0x0 0x100000>,
1904 <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
1911 interrupt-map-mask = <0 0 0 0x7>;
1912 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1913 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1914 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1915 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1918 pinctrl-0 = <&pcie0_state_on>;
1921 linux,pci-domain = <0>;
1935 pcie@0 {
1937 reg = <0x0 0x0 0x0 0x0 0x0>;
1938 bus-range = <0x01 0xff>;
1949 bus-range = <0x00 0xff>;
1954 reg = <0x00608000 0x2000>,
1955 <0x0d000000 0xf1d>,
1956 <0x0d000f20 0xa8>,
1957 <0x0d100000 0x100000>;
1966 ranges = <0x01000000 0x0 0x00000000 0x0d200000 0x0 0x100000>,
1967 <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
1974 interrupt-map-mask = <0 0 0 0x7>;
1975 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1976 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1977 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1978 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1981 pinctrl-0 = <&pcie1_state_on>;
1998 pcie@0 {
2000 reg = <0x0 0x0 0x0 0x0 0x0>;
2001 bus-range = <0x01 0xff>;
2012 bus-range = <0x00 0xff>;
2015 reg = <0x00610000 0x2000>,
2016 <0x0e000000 0xf1d>,
2017 <0x0e000f20 0xa8>,
2018 <0x0e100000 0x100000>;
2027 ranges = <0x01000000 0x0 0x00000000 0x0e200000 0x0 0x100000>,
2028 <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
2035 interrupt-map-mask = <0 0 0 0x7>;
2036 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2037 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2038 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2039 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2042 pinctrl-0 = <&pcie2_state_on>;
2058 pcie@0 {
2060 reg = <0x0 0x0 0x0 0x0 0x0>;
2061 bus-range = <0x01 0xff>;
2073 reg = <0x00624000 0x2500>;
2103 <0 0>,
2104 <0 0>,
2105 <0 0>,
2108 <0 0>,
2109 <0 0>,
2110 <0 0>;
2123 reg = <0x00627000 0x1000>;
2128 resets = <&ufshc 0>;
2132 #phy-cells = <0>;
2139 reg = <0x00a34000 0x1000>,
2140 <0x00a00030 0x4>,
2141 <0x00a35000 0x1000>,
2142 <0x00a00038 0x4>,
2143 <0x00a36000 0x1000>,
2144 <0x00a00040 0x4>,
2145 <0x00a30000 0x100>,
2146 <0x00a30400 0x100>,
2147 <0x00a30800 0x100>,
2148 <0x00a30c00 0x100>,
2149 <0x00a31000 0x500>,
2150 <0x00a00020 0x10>,
2151 <0x00a10000 0x1000>,
2152 <0x00a14000 0x1000>;
2261 iommus = <&vfe_smmu 0>,
2268 #size-cells = <0>;
2275 #size-cells = <0>;
2276 reg = <0xa0c000 0x1000>;
2291 pinctrl-0 = <&cci0_default &cci1_default>;
2294 cci_i2c0: i2c-bus@0 {
2295 reg = <0>;
2298 #size-cells = <0>;
2305 #size-cells = <0>;
2311 reg = <0x00b40000 0x10000>;
2328 reg = <0x00c00000 0xff000>;
2339 iommus = <&venus_smmu 0x00>,
2340 <&venus_smmu 0x01>,
2341 <&venus_smmu 0x0a>,
2342 <&venus_smmu 0x07>,
2343 <&venus_smmu 0x0e>,
2344 <&venus_smmu 0x0f>,
2345 <&venus_smmu 0x08>,
2346 <&venus_smmu 0x09>,
2347 <&venus_smmu 0x0b>,
2348 <&venus_smmu 0x0c>,
2349 <&venus_smmu 0x0d>,
2350 <&venus_smmu 0x10>,
2351 <&venus_smmu 0x11>,
2352 <&venus_smmu 0x21>,
2353 <&venus_smmu 0x28>,
2354 <&venus_smmu 0x29>,
2355 <&venus_smmu 0x2b>,
2356 <&venus_smmu 0x2c>,
2357 <&venus_smmu 0x2d>,
2358 <&venus_smmu 0x31>;
2379 reg = <0x00d00000 0x10000>;
2395 reg = <0x00d40000 0x20000>;
2415 reg = <0x00da0000 0x10000>;
2430 reg = <0x01600000 0x20000>;
2456 reg = <0x01c00000 0x4000>;
2458 interrupts-extended = <&intc 0 390 IRQ_TYPE_EDGE_RISING>,
2459 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2474 qcom,smem-states = <&slpi_smp2p_out 0>;
2501 reg = <0x2080000 0x100>,
2502 <0x2180000 0x020>;
2505 interrupts-extended = <&intc 0 448 IRQ_TYPE_EDGE_RISING>,
2506 <&mpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2539 qcom,smem-states = <&mpss_smp2p_out 0>;
2542 qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x4000>;
2570 qcom,smd-edge = <0>;
2577 reg = <0x3002000 0x1000>,
2578 <0x8280000 0x180000>;
2596 reg = <0x3020000 0x1000>;
2613 reg = <0x3021000 0x1000>;
2620 #size-cells = <0>;
2643 reg = <0x3022000 0x1000>;
2650 #size-cells = <0>;
2673 reg = <0x3023000 0x1000>;
2699 reg = <0x3025000 0x1000>;
2706 #size-cells = <0>;
2708 port@0 {
2709 reg = <0>;
2745 reg = <0x3026000 0x1000>;
2761 #size-cells = <0>;
2763 port@0 {
2764 reg = <0>;
2783 reg = <0x3027000 0x1000>;
2809 reg = <0x3028000 0x1000>;
2827 reg = <0x3810000 0x1000>;
2837 reg = <0x3840000 0x1000>;
2856 reg = <0x3910000 0x1000>;
2866 reg = <0x3940000 0x1000>;
2883 funnel@39b0000 { /* APSS Funnel 0 */
2885 reg = <0x39b0000 0x1000>;
2892 #size-cells = <0>;
2894 port@0 {
2895 reg = <0>;
2921 reg = <0x3a10000 0x1000>;
2931 reg = <0x3a40000 0x1000>;
2950 reg = <0x3b10000 0x1000>;
2960 reg = <0x3b40000 0x1000>;
2979 reg = <0x3bb0000 0x1000>;
2986 #size-cells = <0>;
2988 port@0 {
2989 reg = <0>;
3015 reg = <0x3bc0000 0x1000>;
3022 #size-cells = <0>;
3024 port@0 {
3025 reg = <0>;
3053 reg = <0x06400000 0x90000>;
3063 reg = <0x06af8800 0x400>;
3096 reg = <0x06a00000 0xcc00>;
3100 snps,hird-threshold = /bits/ 8 <0>;
3111 reg = <0x07410000 0x1000>;
3122 #clock-cells = <0>;
3123 #phy-cells = <0>;
3135 reg = <0x07411000 0x180>;
3136 #phy-cells = <0>;
3149 reg = <0x07412000 0x180>;
3150 #phy-cells = <0>;
3163 reg = <0x07464900 0x11c>, <0x07464000 0x800>;
3177 pinctrl-0 = <&sdc1_state_on>;
3187 reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
3201 pinctrl-0 = <&sdc2_state_on>;
3210 reg = <0x07544000 0x2b000>;
3216 qcom,ee = <0>;
3221 reg = <0x07570000 0x1000>;
3227 pinctrl-0 = <&blsp1_uart2_default>;
3236 reg = <0x07575000 0x600>;
3242 pinctrl-0 = <&blsp1_spi1_default>;
3247 #size-cells = <0>;
3253 reg = <0x07577000 0x1000>;
3259 pinctrl-0 = <&blsp1_i2c3_default>;
3264 #size-cells = <0>;
3270 reg = <0x757a000 0x1000>;
3276 pinctrl-0 = <&blsp1_i2c6_default>;
3281 #size-cells = <0>;
3287 reg = <0x07584000 0x2b000>;
3293 qcom,ee = <0>;
3298 reg = <0x075b0000 0x1000>;
3308 reg = <0x075b1000 0x1000>;
3318 reg = <0x075b5000 0x1000>;
3324 pinctrl-0 = <&blsp2_i2c1_default>;
3329 #size-cells = <0>;
3335 reg = <0x075b6000 0x1000>;
3341 pinctrl-0 = <&blsp2_i2c2_default>;
3346 #size-cells = <0>;
3352 reg = <0x075b7000 0x1000>;
3359 pinctrl-0 = <&blsp2_i2c3_default>;
3364 #size-cells = <0>;
3370 reg = <0x75b9000 0x1000>;
3376 pinctrl-0 = <&blsp2_i2c5_default>;
3380 #size-cells = <0>;
3386 reg = <0x75ba000 0x1000>;
3392 pinctrl-0 = <&blsp2_i2c6_default>;
3397 #size-cells = <0>;
3403 reg = <0x075ba000 0x600>;
3409 pinctrl-0 = <&blsp2_spi6_default>;
3414 #size-cells = <0>;
3420 reg = <0x076f8800 0x400>;
3453 reg = <0x07600000 0xcc00>;
3466 reg = <0x09184000 0x32000>;
3476 reg = <0x091c0000 0x2c000>;
3481 #size-cells = <0>;
3488 reg = <0x09300000 0x80000>;
3490 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
3491 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3503 qcom,smem-states = <&adsp_smp2p_out 0>;
3533 #size-cells = <0>;
3546 #size-cells = <0>;
3560 #size-cells = <0>;
3571 #sound-dai-cells = <0>;
3582 #size-cells = <0>;
3637 reg = <0x09820000 0x1000>;
3640 #clock-cells = <0>;
3648 reg = <0x09840000 0x1000>;
3652 frame-number = <0>;
3655 reg = <0x09850000 0x1000>,
3656 <0x09860000 0x1000>;
3662 reg = <0x09870000 0x1000>;
3669 reg = <0x09880000 0x1000>;
3676 reg = <0x09890000 0x1000>;
3683 reg = <0x098a0000 0x1000>;
3690 reg = <0x098b0000 0x1000>;
3697 reg = <0x098c0000 0x1000>;
3704 reg = <0x09a10000 0x1000>;
3709 reg = <0x09a11000 0x10000>;
3711 #clock-cells = <0>;
3720 redistributor-stride = <0x0 0x40000>;
3721 reg = <0x09bc0000 0x10000>,
3722 <0x09c00000 0x100000>;