Lines Matching +full:0 +full:x00408000
36 #clock-cells = <0>;
42 #clock-cells = <0>;
47 #clock-cells = <0>;
56 #clock-cells = <0>;
66 #size-cells = <0>;
68 CPU0: cpu@0 {
71 reg = <0x0 0x0>;
88 reg = <0x0 0x100>;
99 reg = <0x0 0x200>;
110 reg = <0x0 0x300>;
121 reg = <0x0 0x10000>;
138 reg = <0x0 0x10100>;
149 reg = <0x0 0x10200>;
160 reg = <0x0 0x10300>;
171 reg = <0x0 0x20000>;
188 reg = <0x0 0x20100>;
199 reg = <0x0 0x20200>;
210 reg = <0x0 0x20300>;
277 CLUSTER_C4: cpu-sleep-0 {
280 arm,psci-suspend-param = <0x00000004>;
288 CLUSTER_CL4: cluster-sleep-0 {
291 arm,psci-suspend-param = <0x01000044>;
300 arm,psci-suspend-param = <0x01000054>;
316 clk_virt: interconnect-0 {
331 reg = <0 0x80000000 0 0>;
344 #power-domain-cells = <0>;
349 #power-domain-cells = <0>;
354 #power-domain-cells = <0>;
359 #power-domain-cells = <0>;
364 #power-domain-cells = <0>;
369 #power-domain-cells = <0>;
374 #power-domain-cells = <0>;
379 #power-domain-cells = <0>;
384 #power-domain-cells = <0>;
389 #power-domain-cells = <0>;
394 #power-domain-cells = <0>;
399 #power-domain-cells = <0>;
404 #power-domain-cells = <0>;
410 #power-domain-cells = <0>;
416 #power-domain-cells = <0>;
422 #power-domain-cells = <0>;
433 reg = <0x0 0x80000000 0x0 0x800000>;
438 reg = <0x0 0x80800000 0x0 0x200000>;
443 reg = <0x0 0x80a00000 0x0 0x400000>;
448 reg = <0x0 0x80e00000 0x0 0x40000>;
453 reg = <0x0 0x80e40000 0x0 0x540000>;
458 reg = <0x0 0x81380000 0x0 0x80000>;
463 reg = <0x0 0x81400000 0x0 0x1a0000>;
468 reg = <0x0 0x81a00000 0x0 0x40000>;
473 reg = <0x0 0x81a40000 0x0 0x1c0000>;
478 reg = <0x0 0x81c00000 0x0 0x60000>;
484 reg = <0x0 0x81c60000 0x0 0x20000>;
489 reg = <0x0 0x81c80000 0x0 0x20000>;
494 reg = <0x0 0x81ca0000 0x0 0x40000>;
499 reg = <0x0 0x81ce0000 0x0 0x4000>;
504 reg = <0x0 0x81ce4000 0x0 0x10000>;
509 reg = <0x0 0x81cff000 0x0 0x1000>;
514 reg = <0x0 0x81e00000 0x0 0x100000>;
519 reg = <0x0 0x81f00000 0x0 0x10000>;
524 reg = <0x0 0x81f10000 0x0 0x10000>;
529 reg = <0x0 0x81f20000 0x0 0x10000>;
534 reg = <0x0 0x81f30000 0x0 0x6000>;
539 reg = <0x0 0x81f36000 0x0 0x1000>;
544 reg = <0x0 0x81f37000 0x0 0x1000>;
549 reg = <0x0 0x82700000 0x0 0x100000>;
554 reg = <0x0 0x82800000 0x0 0xc00000>;
559 reg = <0x0 0x84b00000 0x0 0x800000>;
564 reg = <0x0 0x85300000 0x0 0x80000>;
569 reg = <0x0 0x866c0000 0x0 0x40000>;
574 reg = <0x0 0x86700000 0x0 0x400000>;
579 reg = <0x0 0x86b00000 0x0 0xc00000>;
584 reg = <0x0 0x87700000 0x0 0x700000>;
589 reg = <0x0 0x87e00000 0x0 0x3a00000>;
594 reg = <0x0 0x8b800000 0x0 0x80000>;
599 reg = <0x0 0x8b900000 0x0 0x2000000>;
604 reg = <0x0 0x8d900000 0x0 0x80000>;
609 reg = <0x0 0x8d9fe000 0x0 0x2000>;
614 reg = <0x0 0x8da00000 0x0 0x700000>;
619 reg = <0x0 0x8e100000 0x0 0x800000>;
624 reg = <0x0 0x8e900000 0x0 0x700000>;
629 reg = <0x0 0x8f000000 0x0 0xa00000>;
634 reg = <0x0 0x8fa00000 0x0 0x1900000>;
639 reg = <0x0 0x91300000 0x0 0x80000>;
644 reg = <0x0 0xd8000000 0x0 0x40000>;
649 reg = <0x0 0xd8040000 0x0 0xa0000>;
654 reg = <0x0 0xd80e0000 0x0 0x520000>;
659 reg = <0x0 0xd8600000 0x0 0x8a00000>;
664 reg = <0x0 0xe1000000 0x0 0x26a0000>;
669 reg = <0x0 0xff800000 0x0 0x600000>;
675 reg = <0x0 0xffe00000 0x0 0x200000>;
692 qcom,local-pid = <0>;
718 qcom,local-pid = <0>;
733 soc: soc@0 {
738 dma-ranges = <0 0 0 0 0x10 0>;
739 ranges = <0 0 0 0 0x10 0>;
743 reg = <0 0x00100000 0 0x200000>;
747 <0>,
751 <0>,
764 reg = <0 0x00408000 0 0x1000>;
775 reg = <0 0x00800000 0 0x60000>;
791 dma-channel-mask = <0x3e>;
794 iommus = <&apps_smmu 0x436 0x0>;
801 reg = <0 0x008c0000 0 0x2000>;
808 iommus = <&apps_smmu 0x423 0x0>;
818 reg = <0 0x00880000 0 0x4000>;
835 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
836 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
840 pinctrl-0 = <&qup_i2c16_data_clk>;
844 #size-cells = <0>;
851 reg = <0 0x00880000 0 0x4000>;
868 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
869 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
873 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
877 #size-cells = <0>;
884 reg = <0 0x00884000 0 0x4000>;
901 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
906 pinctrl-0 = <&qup_i2c17_data_clk>;
910 #size-cells = <0>;
917 reg = <0 0x00884000 0 0x4000>;
934 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
939 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
943 #size-cells = <0>;
950 reg = <0 0x00888000 0 0x4000>;
967 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
972 pinctrl-0 = <&qup_i2c18_data_clk>;
976 #size-cells = <0>;
983 reg = <0 0x00888000 0 0x4000>;
1000 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1005 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
1009 #size-cells = <0>;
1016 reg = <0 0x0088c000 0 0x4000>;
1033 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1038 pinctrl-0 = <&qup_i2c19_data_clk>;
1042 #size-cells = <0>;
1049 reg = <0 0x0088c000 0 0x4000>;
1066 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1071 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
1075 #size-cells = <0>;
1082 reg = <0 0x00890000 0 0x4000>;
1099 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1104 pinctrl-0 = <&qup_i2c20_data_clk>;
1108 #size-cells = <0>;
1115 reg = <0 0x00890000 0 0x4000>;
1132 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1137 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
1141 #size-cells = <0>;
1148 reg = <0 0x00894000 0 0x4000>;
1165 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1170 pinctrl-0 = <&qup_i2c21_data_clk>;
1174 #size-cells = <0>;
1181 reg = <0 0x00894000 0 0x4000>;
1198 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1203 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
1207 #size-cells = <0>;
1214 reg = <0 0x00894000 0 0x4000>;
1228 pinctrl-0 = <&qup_uart21_default>;
1236 reg = <0 0x00898000 0 0x4000>;
1253 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
1258 pinctrl-0 = <&qup_i2c22_data_clk>;
1262 #size-cells = <0>;
1269 reg = <0 0x00898000 0 0x4000>;
1286 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
1291 pinctrl-0 = <&qup_spi22_data_clk>, <&qup_spi22_cs>;
1295 #size-cells = <0>;
1302 reg = <0 0x0089c000 0 0x4000>;
1319 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>,
1324 pinctrl-0 = <&qup_i2c23_data_clk>;
1328 #size-cells = <0>;
1335 reg = <0 0x0089c000 0 0x4000>;
1352 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>,
1357 pinctrl-0 = <&qup_spi23_data_clk>, <&qup_spi23_cs>;
1361 #size-cells = <0>;
1369 reg = <0 0x00a00000 0 0x60000>;
1385 dma-channel-mask = <0x3e>;
1388 iommus = <&apps_smmu 0x136 0x0>;
1395 reg = <0 0x00ac0000 0 0x2000>;
1402 iommus = <&apps_smmu 0x123 0x0>;
1412 reg = <0 0x00a80000 0 0x4000>;
1429 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1430 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1434 pinctrl-0 = <&qup_i2c8_data_clk>;
1438 #size-cells = <0>;
1445 reg = <0 0x00a80000 0 0x4000>;
1462 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1463 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1467 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1471 #size-cells = <0>;
1478 reg = <0 0x00a84000 0 0x4000>;
1495 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1500 pinctrl-0 = <&qup_i2c9_data_clk>;
1504 #size-cells = <0>;
1511 reg = <0 0x00a84000 0 0x4000>;
1528 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1533 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1537 #size-cells = <0>;
1544 reg = <0 0x00a88000 0 0x4000>;
1561 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1566 pinctrl-0 = <&qup_i2c10_data_clk>;
1570 #size-cells = <0>;
1577 reg = <0 0x00a88000 0 0x4000>;
1594 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1599 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1603 #size-cells = <0>;
1610 reg = <0 0x00a8c000 0 0x4000>;
1627 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1632 pinctrl-0 = <&qup_i2c11_data_clk>;
1636 #size-cells = <0>;
1643 reg = <0 0x00a8c000 0 0x4000>;
1660 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1665 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1669 #size-cells = <0>;
1676 reg = <0 0x00a90000 0 0x4000>;
1693 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1698 pinctrl-0 = <&qup_i2c12_data_clk>;
1702 #size-cells = <0>;
1709 reg = <0 0x00a90000 0 0x4000>;
1726 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1731 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1735 #size-cells = <0>;
1742 reg = <0 0x00a94000 0 0x4000>;
1759 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1764 pinctrl-0 = <&qup_i2c13_data_clk>;
1768 #size-cells = <0>;
1775 reg = <0 0x00a94000 0 0x4000>;
1792 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1797 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1801 #size-cells = <0>;
1808 reg = <0 0x00a98000 0 0x4000>;
1825 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1830 pinctrl-0 = <&qup_i2c14_data_clk>;
1834 #size-cells = <0>;
1841 reg = <0 0x00a98000 0 0x4000>;
1858 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1863 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1867 #size-cells = <0>;
1874 reg = <0 0x00a9c000 0 0x4000>;
1891 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
1896 pinctrl-0 = <&qup_i2c15_data_clk>;
1900 #size-cells = <0>;
1907 reg = <0 0x00a9c000 0 0x4000>;
1924 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
1929 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1933 #size-cells = <0>;
1941 reg = <0 0x00b00000 0 0x60000>;
1957 dma-channel-mask = <0x3e>;
1960 iommus = <&apps_smmu 0x456 0x0>;
1967 reg = <0 0x00bc0000 0 0x2000>;
1974 iommus = <&apps_smmu 0x443 0x0>;
1983 reg = <0 0x00b80000 0 0x4000>;
2000 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
2001 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
2005 pinctrl-0 = <&qup_i2c0_data_clk>;
2009 #size-cells = <0>;
2016 reg = <0 0x00b80000 0 0x4000>;
2033 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
2034 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
2038 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
2042 #size-cells = <0>;
2049 reg = <0 0x00b84000 0 0x4000>;
2066 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
2071 pinctrl-0 = <&qup_i2c1_data_clk>;
2075 #size-cells = <0>;
2082 reg = <0 0x00b84000 0 0x4000>;
2099 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
2104 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
2108 #size-cells = <0>;
2115 reg = <0 0x00b88000 0 0x4000>;
2132 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
2137 pinctrl-0 = <&qup_i2c2_data_clk>;
2141 #size-cells = <0>;
2148 reg = <0 0x00b88000 0 0x4000>;
2162 pinctrl-0 = <&qup_uart2_default>;
2170 reg = <0 0x00b88000 0 0x4000>;
2187 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
2192 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
2196 #size-cells = <0>;
2203 reg = <0 0x00b8c000 0 0x4000>;
2220 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
2225 pinctrl-0 = <&qup_i2c3_data_clk>;
2229 #size-cells = <0>;
2236 reg = <0 0x00b8c000 0 0x4000>;
2253 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
2258 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
2262 #size-cells = <0>;
2269 reg = <0 0x00b90000 0 0x4000>;
2286 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
2291 pinctrl-0 = <&qup_i2c4_data_clk>;
2295 #size-cells = <0>;
2302 reg = <0 0x00b90000 0 0x4000>;
2319 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
2324 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
2328 #size-cells = <0>;
2335 reg = <0 0x00b94000 0 0x4000>;
2352 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
2357 pinctrl-0 = <&qup_i2c5_data_clk>;
2361 #size-cells = <0>;
2368 reg = <0 0x00b94000 0 0x4000>;
2385 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
2390 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
2394 #size-cells = <0>;
2401 reg = <0 0x00b98000 0 0x4000>;
2418 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
2423 pinctrl-0 = <&qup_i2c6_data_clk>;
2427 #size-cells = <0>;
2434 reg = <0 0x00b98000 0 0x4000>;
2451 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
2456 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
2460 #size-cells = <0>;
2467 reg = <0 0x00b9c000 0 0x4000>;
2484 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
2489 pinctrl-0 = <&qup_i2c7_data_clk>;
2493 #size-cells = <0>;
2500 reg = <0 0x00b9c000 0 0x4000>;
2517 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
2522 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
2526 #size-cells = <0>;
2534 reg = <0 0x0c271000 0 0x1000>,
2535 <0 0x0c222000 0 0x1000>;
2549 reg = <0 0x0c272000 0 0x1000>,
2550 <0 0x0c223000 0 0x1000>;
2564 reg = <0 0x0c273000 0 0x1000>,
2565 <0 0x0c224000 0 0x1000>;
2579 reg = <0 0x0c274000 0 0x1000>,
2580 <0 0x0c225000 0 0x1000>;
2595 reg = <0 0x00fd3000 0 0x154>;
2596 #phy-cells = <0>;
2608 reg = <0 0x00fd5000 0 0x4000>;
2635 #size-cells = <0>;
2637 port@0 {
2638 reg = <0>;
2665 reg = <0 0x00fd9000 0 0x154>;
2666 #phy-cells = <0>;
2678 reg = <0 0x00fda000 0 0x4000>;
2705 #size-cells = <0>;
2707 port@0 {
2708 reg = <0>;
2735 reg = <0 0x00fde000 0 0x154>;
2736 #phy-cells = <0>;
2748 reg = <0 0x00fdf000 0 0x4000>;
2775 #size-cells = <0>;
2777 port@0 {
2778 reg = <0>;
2804 reg = <0 0x01500000 0 0x14400>;
2813 reg = <0 0x01600000 0 0x6600>;
2822 reg = <0 0x01680000 0 0x1c080>;
2831 reg = <0 0x016c0000 0 0xd080>;
2840 reg = <0 0x016d0000 0 0x7000>;
2849 reg = <0 0x016e0000 0 0x14400>;
2858 reg = <0 0x01700000 0 0x1c400>;
2867 reg = <0 0x01740000 0 0x9080>;
2876 reg = <0 0x01750000 0 0x8800>;
2885 reg = <0 0x01760000 0 0x7080>;
2894 reg = <0 0x01770000 0 0xf080>;
2903 reg = <0 0x01780000 0 0x5B800>;
2913 reg = <0 0x01bf8000 0 0x3000>,
2914 <0 0x70000000 0 0xf20>,
2915 <0 0x70000f40 0 0xa8>,
2916 <0 0x70001000 0 0x1000>,
2917 <0 0x70100000 0 0x100000>,
2918 <0 0x01bfb000 0 0x1000>;
2927 ranges = <0x01000000 0x0 0x00000000 0x0 0x70200000 0x0 0x100000>,
2928 <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x1d00000>;
2929 bus-range = <0x00 0xff>;
2954 interrupt-map-mask = <0 0 0 0x7>;
2955 interrupt-map = <0 0 0 1 &intc 0 0 0 843 IRQ_TYPE_LEVEL_HIGH>,
2956 <0 0 0 2 &intc 0 0 0 844 IRQ_TYPE_LEVEL_HIGH>,
2957 <0 0 0 3 &intc 0 0 0 845 IRQ_TYPE_LEVEL_HIGH>,
2958 <0 0 0 4 &intc 0 0 0 772 IRQ_TYPE_LEVEL_HIGH>;
3001 reg = <0 0x01bfc000 0 0x2000>,
3002 <0 0x01bfe000 0 0x2000>;
3027 qcom,4ln-config-sel = <&tcsr 0x1a000 0>;
3029 #clock-cells = <0>;
3032 #phy-cells = <0>;
3040 reg = <0 0x01c00000 0 0x3000>,
3041 <0 0x7e000000 0 0xf1d>,
3042 <0 0x7e000f40 0 0xa8>,
3043 <0 0x7e001000 0 0x1000>,
3044 <0 0x7e100000 0 0x100000>,
3045 <0 0x01c03000 0 0x1000>;
3054 ranges = <0x01000000 0x0 0x00000000 0x0 0x7e200000 0x0 0x100000>,
3055 <0x02000000 0x0 0x7e300000 0x0 0x7e300000 0x0 0x1d00000>;
3056 bus-range = <0x00 0xff>;
3081 interrupt-map-mask = <0 0 0 0x7>;
3082 interrupt-map = <0 0 0 1 &intc 0 0 0 70 IRQ_TYPE_LEVEL_HIGH>,
3083 <0 0 0 2 &intc 0 0 0 71 IRQ_TYPE_LEVEL_HIGH>,
3084 <0 0 0 3 &intc 0 0 0 72 IRQ_TYPE_LEVEL_HIGH>,
3085 <0 0 0 4 &intc 0 0 0 73 IRQ_TYPE_LEVEL_HIGH>;
3128 reg = <0 0x01c06000 0 0x2000>;
3151 #clock-cells = <0>;
3154 #phy-cells = <0>;
3162 reg = <0 0x01c08000 0 0x3000>,
3163 <0 0x7c000000 0 0xf1d>,
3164 <0 0x7c000f40 0 0xa8>,
3165 <0 0x7c001000 0 0x1000>,
3166 <0 0x7c100000 0 0x100000>,
3167 <0 0x01c0b000 0 0x1000>;
3176 ranges = <0x01000000 0x0 0x00000000 0x0 0x7c200000 0x0 0x100000>,
3177 <0x02000000 0x0 0x7c300000 0x0 0x7c300000 0x0 0x1d00000>;
3178 bus-range = <0x00 0xff>;
3203 interrupt-map-mask = <0 0 0 0x7>;
3204 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>,
3205 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>,
3206 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>,
3207 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>;
3247 pcie4_port0: pcie@0 {
3249 reg = <0x0 0x0 0x0 0x0 0x0>;
3250 bus-range = <0x01 0xff>;
3260 reg = <0 0x01c0e000 0 0x2000>;
3283 #clock-cells = <0>;
3286 #phy-cells = <0>;
3293 reg = <0 0x01f40000 0 0x20000>;
3299 reg = <0 0x01fc0000 0 0x30000>;
3307 reg = <0x0 0x03d00000 0x0 0x40000>,
3308 <0x0 0x03d9e000 0x0 0x1000>,
3309 <0x0 0x03d61000 0x0 0x800>;
3317 iommus = <&adreno_smmu 0 0x0>,
3318 <&adreno_smmu 1 0x0>;
3325 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
3395 reg = <0x0 0x03d6a000 0x0 0x35000>,
3396 <0x0 0x03d50000 0x0 0x10000>,
3397 <0x0 0x0b280000 0x0 0x10000>;
3424 iommus = <&adreno_smmu 5 0x0>;
3447 reg = <0 0x03d90000 0 0xa000>;
3459 reg = <0x0 0x03da0000 0x0 0x40000>;
3502 reg = <0 0x26400000 0 0x311200>;
3511 reg = <0 0x320C0000 0 0xe080>;
3520 reg = <0 0x06aa0000 0 0x1000>;
3530 #clock-cells = <0>;
3538 reg = <0 0x06ab0000 0 0x10000>;
3544 pinctrl-0 = <&wsa2_swr_active>;
3552 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x3…
3553 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
3554 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3555 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3556 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3557 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
3558 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
3559 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
3560 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
3563 #size-cells = <0>;
3570 reg = <0 0x06ac0000 0 0x1000>;
3580 #clock-cells = <0>;
3587 reg = <0 0x06ad0000 0 0x10000>;
3593 pinctrl-0 = <&rx_swr_active>;
3601 qcom,ports-sinterval = /bits/ 16 <0x03 0x1f 0x1f 0x07 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3602 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3603 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3604 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3605 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3606 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3607 …qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff…
3608 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
3609 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3612 #size-cells = <0>;
3619 reg = <0 0x06ae0000 0 0x1000>;
3629 #clock-cells = <0>;
3636 reg = <0 0x06b00000 0 0x1000>;
3646 #clock-cells = <0>;
3654 reg = <0 0x06b10000 0 0x10000>;
3660 pinctrl-0 = <&wsa_swr_active>;
3668 …qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x3…
3669 … qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
3670 … qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
3671 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3672 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
3673 …qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x1…
3674 …qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00…
3675 …qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
3676 …qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x…
3679 #size-cells = <0>;
3686 reg = <0 0x06b6c000 0 0x1000>;
3693 reg = <0 0x06d30000 0 0x10000>;
3703 pinctrl-0 = <&tx_swr_active>;
3709 qcom,ports-sinterval-low = /bits/ 8 <0x00 0x01 0x03 0x03 0x00>;
3710 qcom,ports-offset1 = /bits/ 8 <0x00 0x01 0x02 0x00 0x00>;
3711 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00 0xff>;
3712 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
3713 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
3714 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
3715 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
3716 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
3717 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x00 0x01 0xff>;
3720 #size-cells = <0>;
3727 reg = <0 0x06d44000 0 0x1000>;
3735 #clock-cells = <0>;
3742 reg = <0 0x06e80000 0 0x20000>,
3743 <0 0x07250000 0 0x10000>;
3751 gpio-ranges = <&lpass_tlmm 0 0 23>;
3860 reg = <0 0x06ea0000 0 0x12000>;
3867 reg = <0 0x07e40000 0 0xe080>;
3876 reg = <0 0x07400000 0 0x19080>;
3885 reg = <0 0x07430000 0 0x3A200>;
3895 reg = <0 0x088e0000 0 0x154>;
3896 #phy-cells = <0>;
3909 reg = <0 0x088e1000 0 0x154>;
3910 #phy-cells = <0>;
3923 reg = <0 0x088e2000 0 0x154>;
3924 #phy-cells = <0>;
3936 reg = <0 0x088e3000 0 0x2000>;
3954 #clock-cells = <0>;
3957 #phy-cells = <0>;
3964 reg = <0 0x088e5000 0 0x2000>;
3982 #clock-cells = <0>;
3985 #phy-cells = <0>;
3992 reg = <0 0x0a0f8800 0 0x400>;
4049 reg = <0 0x0a000000 0 0xcd00>;
4053 iommus = <&apps_smmu 0x14a0 0x0>;
4068 #size-cells = <0>;
4070 port@0 {
4071 reg = <0>;
4090 reg = <0 0x0a2f8800 0 0x400>;
4143 reg = <0 0x0a200000 0 0xcd00>;
4145 iommus = <&apps_smmu 0x14e0 0x0>;
4152 #size-cells = <0>;
4154 port@0 {
4155 reg = <0>;
4166 reg = <0 0x0a4f8800 0 0x400>;
4230 reg = <0 0x0a400000 0 0xcd00>;
4234 iommus = <&apps_smmu 0x1400 0x0>;
4238 phy-names = "usb2-0", "usb3-0",
4252 reg = <0 0x0a6f8800 0 0x400>;
4302 reg = <0 0x0a600000 0 0xcd00>;
4306 iommus = <&apps_smmu 0x1420 0x0>;
4321 #size-cells = <0>;
4323 port@0 {
4324 reg = <0>;
4343 reg = <0 0x0a8f8800 0 0x400>;
4400 reg = <0 0x0a800000 0 0xcd00>;
4404 iommus = <&apps_smmu 0x1460 0x0>;
4419 #size-cells = <0>;
4421 port@0 {
4422 reg = <0>;
4441 reg = <0 0x0ae00000 0 0x1000>;
4464 iommus = <&apps_smmu 0x1c00 0x2>;
4477 reg = <0 0x0ae01000 0 0x8f000>,
4478 <0 0x0aeb0000 0 0x2008>;
4482 interrupts-extended = <&mdss 0>;
4501 #size-cells = <0>;
4503 port@0 {
4504 reg = <0>;
4568 reg = <0 0x0ae90000 0 0x200>,
4569 <0 0x0ae90200 0 0x200>,
4570 <0 0x0ae90400 0 0x600>,
4571 <0 0x0ae91000 0 0x400>,
4572 <0 0x0ae91400 0 0x400>;
4599 #sound-dai-cells = <0>;
4605 #size-cells = <0>;
4607 port@0 {
4608 reg = <0>;
4651 reg = <0 0x0ae98000 0 0x200>,
4652 <0 0x0ae98200 0 0x200>,
4653 <0 0x0ae98400 0 0x600>,
4654 <0 0x0ae99000 0 0x400>,
4655 <0 0x0ae99400 0 0x400>;
4682 #sound-dai-cells = <0>;
4688 #size-cells = <0>;
4690 port@0 {
4691 reg = <0>;
4734 reg = <0 0x0ae9a000 0 0x200>,
4735 <0 0x0ae9a200 0 0x200>,
4736 <0 0x0ae9a400 0 0x600>,
4737 <0 0x0ae9b000 0 0x400>,
4738 <0 0x0ae9b400 0 0x400>;
4765 #sound-dai-cells = <0>;
4771 #size-cells = <0>;
4773 port@0 {
4774 reg = <0>;
4816 reg = <0 0x0aea0000 0 0x200>,
4817 <0 0x0aea0200 0 0x200>,
4818 <0 0x0aea0400 0 0x600>,
4819 <0 0x0aea1000 0 0x400>,
4820 <0 0x0aea1400 0 0x400>;
4837 assigned-clock-parents = <&mdss_dp3_phy 0>,
4847 #sound-dai-cells = <0>;
4853 #size-cells = <0>;
4855 port@0 {
4856 reg = <0>;
4897 reg = <0 0x0aec2a00 0 0x19c>,
4898 <0 0x0aec2200 0 0xec>,
4899 <0 0x0aec2600 0 0xec>,
4900 <0 0x0aec2000 0 0x1c8>;
4910 #phy-cells = <0>;
4917 reg = <0 0x0aec5a00 0 0x19c>,
4918 <0 0x0aec5200 0 0xec>,
4919 <0 0x0aec5600 0 0xec>,
4920 <0 0x0aec5000 0 0x1c8>;
4930 #phy-cells = <0>;
4937 reg = <0 0x0af00000 0 0x20000>;
4942 <0>, /* dsi0 */
4943 <0>,
4944 <0>, /* dsi1 */
4945 <0>,
4952 <&mdss_dp3_phy 0>, /* dp3 */
4963 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
4965 qcom,pdc-ranges = <0 480 42>, <42 251 5>,
4975 reg = <0 0x0c300000 0 0x400>;
4981 #clock-cells = <0>;
4986 reg = <0 0x0c3f0000 0 0x400>;
4991 reg = <0 0x0c400000 0 0x3000>,
4992 <0 0x0c500000 0 0x400000>,
4993 <0 0x0c440000 0 0x80000>;
4996 qcom,ee = <0>;
4997 qcom,channel = <0>;
5004 reg = <0 0x0c42d000 0 0x4000>,
5005 <0 0x0c4c0000 0 0x10000>;
5014 #size-cells = <0>;
5018 reg = <0 0x0c432000 0 0x4000>,
5019 <0 0x0c4d0000 0 0x10000>;
5028 #size-cells = <0>;
5034 reg = <0 0x0f100000 0 0xf00000>;
5044 gpio-ranges = <&tlmm 0 0 239>;
5648 reg = <0 0x15000000 0 0x100000>;
5754 reg = <0 0x17000000 0 0x10000>, /* GICD */
5755 <0 0x17080000 0 0x480000>; /* GICR * 12 */
5763 redistributor-stride = <0x0 0x40000>;
5771 reg = <0 0x17040000 0 0x40000>;
5782 reg = <0 0x17500000 0 0x10000>,
5783 <0 0x17510000 0 0x10000>,
5784 <0 0x17520000 0 0x10000>;
5785 reg-names = "drv-0", "drv-1", "drv-2";
5790 qcom,tcs-offset = <0xd00>;
5793 <WAKE_TCS 2>, <CONTROL_TCS 0>;
5886 reg = <0 0x17800000 0 0x1000>;
5890 ranges = <0 0 0 0 0x20000000>;
5893 reg = <0 0x17801000 0x1000>,
5894 <0 0x17802000 0x1000>;
5899 frame-number = <0>;
5903 reg = <0 0x17803000 0x1000>;
5913 reg = <0 0x17805000 0x1000>;
5923 reg = <0 0x17807000 0x1000>;
5933 reg = <0 0x17809000 0x1000>;
5943 reg = <0 0x1780b000 0x1000>;
5953 reg = <0 0x1780d000 0x1000>;
5965 reg = <0 0x24091000 0 0x1000>;
5977 opp-0 {
6022 reg = <0 0x240b3400 0 0x600>;
6034 opp-0 {
6063 reg = <0 0x240b5400 0 0x600>;
6076 reg = <0 0x240b6400 0 0x600>;
6088 reg = <0 0x25000000 0 0x200000>,
6089 <0 0x25200000 0 0x200000>,
6090 <0 0x25400000 0 0x200000>,
6091 <0 0x25600000 0 0x200000>,
6092 <0 0x25800000 0 0x200000>,
6093 <0 0x25a00000 0 0x200000>,
6094 <0 0x25c00000 0 0x200000>,
6095 <0 0x25e00000 0 0x200000>,
6096 <0 0x26000000 0 0x200000>,
6097 <0 0x26200000 0 0x200000>;
6113 reg = <0 0x30000000 0 0x100>;
6116 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
6142 qcom,smem-states = <&smp2p_adsp_out 0>;
6163 #size-cells = <0>;
6168 iommus = <&apps_smmu 0x1003 0x80>,
6169 <&apps_smmu 0x1063 0x0>;
6176 iommus = <&apps_smmu 0x1004 0x80>,
6177 <&apps_smmu 0x1064 0x0>;
6184 iommus = <&apps_smmu 0x1005 0x80>,
6185 <&apps_smmu 0x1065 0x0>;
6192 iommus = <&apps_smmu 0x1006 0x80>,
6193 <&apps_smmu 0x1066 0x0>;
6200 iommus = <&apps_smmu 0x1007 0x80>,
6201 <&apps_smmu 0x1067 0x0>;
6212 #size-cells = <0>;
6217 #sound-dai-cells = <0>;
6228 iommus = <&apps_smmu 0x1001 0x80>,
6229 <&apps_smmu 0x1061 0x0>;
6250 reg = <0 0x32300000 0 0x1400000>;
6253 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
6281 qcom,smem-states = <&smp2p_cdsp_out 0>;
6302 #size-cells = <0>;
6307 iommus = <&apps_smmu 0x0c01 0x20>;
6314 iommus = <&apps_smmu 0x0c02 0x20>;
6321 iommus = <&apps_smmu 0x0c03 0x20>;
6328 iommus = <&apps_smmu 0x0c04 0x20>;
6335 iommus = <&apps_smmu 0x0c05 0x20>;
6342 iommus = <&apps_smmu 0x0c06 0x20>;
6349 iommus = <&apps_smmu 0x0c07 0x20>;
6356 iommus = <&apps_smmu 0x0c08 0x20>;
6365 iommus = <&apps_smmu 0x0c0c 0x20>;
6372 iommus = <&apps_smmu 0x0c0d 0x20>;
6379 iommus = <&apps_smmu 0x0c0e 0x20>;
6386 iommus = <&apps_smmu 0x0c0f 0x20>;
6405 thermal-sensors = <&tsens0 0>;
6416 hysteresis = <0>;
6422 cpu0-0-top-thermal {
6448 cpu0-0-btm-thermal {
6642 hysteresis = <0>;
6660 hysteresis = <0>;
6678 hysteresis = <0>;
6699 thermal-sensors = <&tsens1 0>;
6710 hysteresis = <0>;
6716 cpu1-0-top-thermal {
6742 cpu1-0-btm-thermal {
6936 hysteresis = <0>;
6954 hysteresis = <0>;
6961 thermal-sensors = <&tsens2 0>;
6972 hysteresis = <0>;
6978 cpu2-0-top-thermal {
7004 cpu2-0-btm-thermal {
7198 hysteresis = <0>;
7216 hysteresis = <0>;
7223 thermal-sensors = <&tsens3 0>;
7234 hysteresis = <0>;
7252 hysteresis = <0>;
7270 hysteresis = <0>;
7288 hysteresis = <0>;
7306 hysteresis = <0>;
7312 gpuss-0-thermal {
7532 hysteresis = <0>;
7550 hysteresis = <0>;