Lines Matching +full:0 +full:x00408000
80 #clock-cells = <0>;
88 #clock-cells = <0>;
94 #size-cells = <0>;
96 CPU0: cpu@0 {
99 reg = <0x0 0x0>;
100 clocks = <&cpufreq_hw 0>;
107 qcom,freq-domain = <&cpufreq_hw 0>;
109 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
115 cache-size = <0x20000>;
121 cache-size = <0x400000>;
130 reg = <0x0 0x100>;
131 clocks = <&cpufreq_hw 0>;
138 qcom,freq-domain = <&cpufreq_hw 0>;
140 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
146 cache-size = <0x20000>;
155 reg = <0x0 0x200>;
156 clocks = <&cpufreq_hw 0>;
163 qcom,freq-domain = <&cpufreq_hw 0>;
165 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
171 cache-size = <0x20000>;
180 reg = <0x0 0x300>;
181 clocks = <&cpufreq_hw 0>;
188 qcom,freq-domain = <&cpufreq_hw 0>;
190 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
196 cache-size = <0x20000>;
205 reg = <0x0 0x400>;
215 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
221 cache-size = <0x40000>;
230 reg = <0x0 0x500>;
240 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
246 cache-size = <0x40000>;
255 reg = <0x0 0x600>;
265 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
271 cache-size = <0x40000>;
280 reg = <0x0 0x700>;
290 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
296 cache-size = <0x80000>;
341 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
344 arm,psci-suspend-param = <0x40000004>;
351 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
354 arm,psci-suspend-param = <0x40000004>;
363 CLUSTER_SLEEP_0: cluster-sleep-0 {
365 arm,psci-suspend-param = <0x4100c244>;
672 qcom,dload-mode = <&tcsr 0x13000>;
680 reg = <0x0 0x80000000 0x0 0x0>;
693 #power-domain-cells = <0>;
699 #power-domain-cells = <0>;
705 #power-domain-cells = <0>;
711 #power-domain-cells = <0>;
717 #power-domain-cells = <0>;
723 #power-domain-cells = <0>;
729 #power-domain-cells = <0>;
735 #power-domain-cells = <0>;
741 #power-domain-cells = <0>;
771 reg = <0x0 0x80000000 0x0 0x600000>;
776 reg = <0x0 0x80700000 0x0 0x160000>;
782 reg = <0x0 0x80860000 0x0 0x20000>;
787 reg = <0x0 0x80900000 0x0 0x200000>;
792 reg = <0x0 0x80b00000 0x0 0x5300000>;
797 reg = <0x0 0x86200000 0x0 0x500000>;
802 reg = <0x0 0x86700000 0x0 0x100000>;
807 reg = <0x0 0x86800000 0x0 0x10000>;
812 reg = <0x0 0x86810000 0x0 0xa000>;
817 reg = <0x0 0x8681a000 0x0 0x2000>;
822 reg = <0x0 0x86900000 0x0 0x500000>;
827 reg = <0x0 0x86e00000 0x0 0x500000>;
832 reg = <0x0 0x87300000 0x0 0x500000>;
837 reg = <0x0 0x87800000 0x0 0x1400000>;
842 reg = <0x0 0x88c00000 0x0 0x1500000>;
847 reg = <0x0 0x8a100000 0x0 0x1d00000>;
852 reg = <0x0 0x8be00000 0x0 0x100000>;
857 reg = <0x0 0x8bf00000 0x0 0x4600000>;
877 qcom,local-pid = <0>;
901 qcom,local-pid = <0>;
925 qcom,local-pid = <0>;
940 soc: soc@0 {
943 ranges = <0 0 0 0 0x10 0>;
944 dma-ranges = <0 0 0 0 0x10 0>;
949 reg = <0x0 0x00100000 0x0 0x1f0000>;
963 reg = <0 0x00408000 0 0x1000>;
972 reg = <0 0x00784000 0 0x8ff>;
977 reg = <0x19b 0x1>;
984 reg = <0 0x00793000 0 0x1000>;
991 reg = <0 0x00800000 0 0x70000>;
1003 dma-channel-mask = <0x3f>;
1004 iommus = <&apps_smmu 0x76 0x0>;
1011 reg = <0x0 0x008c0000 0x0 0x6000>;
1017 iommus = <&apps_smmu 0x63 0x0>;
1023 reg = <0 0x00880000 0 0x4000>;
1027 pinctrl-0 = <&qup_i2c14_default>;
1029 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
1030 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
1033 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1034 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1035 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1040 #size-cells = <0>;
1046 reg = <0 0x00880000 0 0x4000>;
1050 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
1051 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
1055 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1056 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1057 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1062 #size-cells = <0>;
1068 reg = <0 0x00884000 0 0x4000>;
1072 pinctrl-0 = <&qup_i2c15_default>;
1074 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1078 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1079 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1080 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1085 #size-cells = <0>;
1091 reg = <0 0x00884000 0 0x4000>;
1095 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1100 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1101 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1102 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1107 #size-cells = <0>;
1113 reg = <0 0x00888000 0 0x4000>;
1117 pinctrl-0 = <&qup_i2c16_default>;
1119 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1123 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1124 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1125 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1130 #size-cells = <0>;
1136 reg = <0 0x00888000 0 0x4000>;
1140 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1145 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1146 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1147 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1152 #size-cells = <0>;
1158 reg = <0 0x0088c000 0 0x4000>;
1162 pinctrl-0 = <&qup_i2c17_default>;
1164 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1168 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1169 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1170 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1175 #size-cells = <0>;
1181 reg = <0 0x0088c000 0 0x4000>;
1185 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1190 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1191 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1192 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1197 #size-cells = <0>;
1203 reg = <0 0x0088c000 0 0x4000>;
1207 pinctrl-0 = <&qup_uart17_default>;
1211 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1212 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1220 reg = <0 0x00890000 0 0x4000>;
1224 pinctrl-0 = <&qup_i2c18_default>;
1226 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1230 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1231 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1232 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1237 #size-cells = <0>;
1243 reg = <0 0x00890000 0 0x4000>;
1247 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1252 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1253 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1254 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1259 #size-cells = <0>;
1265 reg = <0 0x00890000 0 0x4000>;
1269 pinctrl-0 = <&qup_uart18_default>;
1273 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1274 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1282 reg = <0 0x00894000 0 0x4000>;
1286 pinctrl-0 = <&qup_i2c19_default>;
1288 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1292 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1293 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1294 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1299 #size-cells = <0>;
1305 reg = <0 0x00894000 0 0x4000>;
1309 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1314 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1315 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1316 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1321 #size-cells = <0>;
1328 reg = <0 0x00900000 0 0x70000>;
1343 dma-channel-mask = <0x7ff>;
1344 iommus = <&apps_smmu 0x5b6 0x0>;
1351 reg = <0x0 0x009c0000 0x0 0x6000>;
1357 iommus = <&apps_smmu 0x5a3 0x0>;
1363 reg = <0 0x00980000 0 0x4000>;
1367 pinctrl-0 = <&qup_i2c0_default>;
1369 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1370 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1373 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1374 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1375 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1380 #size-cells = <0>;
1386 reg = <0 0x00980000 0 0x4000>;
1390 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1391 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1395 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1396 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1397 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1402 #size-cells = <0>;
1408 reg = <0 0x00984000 0 0x4000>;
1412 pinctrl-0 = <&qup_i2c1_default>;
1414 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1418 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1419 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1420 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1425 #size-cells = <0>;
1431 reg = <0 0x00984000 0 0x4000>;
1435 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1440 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1441 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1442 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1447 #size-cells = <0>;
1453 reg = <0 0x00988000 0 0x4000>;
1457 pinctrl-0 = <&qup_i2c2_default>;
1459 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1463 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1464 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1465 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1470 #size-cells = <0>;
1476 reg = <0 0x00988000 0 0x4000>;
1480 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1485 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1486 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1487 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1492 #size-cells = <0>;
1498 reg = <0 0x00988000 0 0x4000>;
1502 pinctrl-0 = <&qup_uart2_default>;
1506 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1507 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1515 reg = <0 0x0098c000 0 0x4000>;
1519 pinctrl-0 = <&qup_i2c3_default>;
1521 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1525 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1526 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1527 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1532 #size-cells = <0>;
1538 reg = <0 0x0098c000 0 0x4000>;
1542 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1547 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1548 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1549 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1554 #size-cells = <0>;
1560 reg = <0 0x00990000 0 0x4000>;
1564 pinctrl-0 = <&qup_i2c4_default>;
1566 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1570 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1571 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1572 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1577 #size-cells = <0>;
1583 reg = <0 0x00990000 0 0x4000>;
1587 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1592 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1593 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1594 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1599 #size-cells = <0>;
1605 reg = <0 0x00994000 0 0x4000>;
1609 pinctrl-0 = <&qup_i2c5_default>;
1611 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1615 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1616 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1617 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1622 #size-cells = <0>;
1628 reg = <0 0x00994000 0 0x4000>;
1632 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1637 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1638 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1639 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1644 #size-cells = <0>;
1650 reg = <0 0x00998000 0 0x4000>;
1654 pinctrl-0 = <&qup_i2c6_default>;
1656 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1660 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1661 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1662 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1667 #size-cells = <0>;
1673 reg = <0 0x00998000 0 0x4000>;
1677 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1682 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1683 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1684 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1689 #size-cells = <0>;
1695 reg = <0 0x00998000 0 0x4000>;
1699 pinctrl-0 = <&qup_uart6_default>;
1703 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1704 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1712 reg = <0 0x0099c000 0 0x4000>;
1716 pinctrl-0 = <&qup_i2c7_default>;
1718 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1722 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1723 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1724 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1729 #size-cells = <0>;
1735 reg = <0 0x0099c000 0 0x4000>;
1739 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1744 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1745 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1746 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1751 #size-cells = <0>;
1758 reg = <0 0x00a00000 0 0x70000>;
1770 dma-channel-mask = <0x3f>;
1771 iommus = <&apps_smmu 0x56 0x0>;
1778 reg = <0x0 0x00ac0000 0x0 0x6000>;
1784 iommus = <&apps_smmu 0x43 0x0>;
1790 reg = <0 0x00a80000 0 0x4000>;
1794 pinctrl-0 = <&qup_i2c8_default>;
1796 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1797 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1800 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1801 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1802 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1807 #size-cells = <0>;
1813 reg = <0 0x00a80000 0 0x4000>;
1817 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1818 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1822 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1823 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1824 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1829 #size-cells = <0>;
1835 reg = <0 0x00a84000 0 0x4000>;
1839 pinctrl-0 = <&qup_i2c9_default>;
1841 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1845 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1846 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1847 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1852 #size-cells = <0>;
1858 reg = <0 0x00a84000 0 0x4000>;
1862 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1867 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1868 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1869 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1874 #size-cells = <0>;
1880 reg = <0 0x00a88000 0 0x4000>;
1884 pinctrl-0 = <&qup_i2c10_default>;
1886 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1890 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1891 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1892 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1897 #size-cells = <0>;
1903 reg = <0 0x00a88000 0 0x4000>;
1907 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1912 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1913 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1914 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1919 #size-cells = <0>;
1925 reg = <0 0x00a8c000 0 0x4000>;
1929 pinctrl-0 = <&qup_i2c11_default>;
1931 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1935 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1936 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1937 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1942 #size-cells = <0>;
1948 reg = <0 0x00a8c000 0 0x4000>;
1952 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1957 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1958 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1959 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1964 #size-cells = <0>;
1970 reg = <0 0x00a90000 0 0x4000>;
1974 pinctrl-0 = <&qup_i2c12_default>;
1976 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1980 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1981 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1982 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1987 #size-cells = <0>;
1993 reg = <0 0x00a90000 0 0x4000>;
1997 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
2002 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
2003 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
2004 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
2009 #size-cells = <0>;
2015 reg = <0x0 0x00a90000 0x0 0x4000>;
2019 pinctrl-0 = <&qup_uart12_default>;
2023 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
2024 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
2032 reg = <0 0x00a94000 0 0x4000>;
2036 pinctrl-0 = <&qup_i2c13_default>;
2038 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
2042 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
2043 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
2044 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
2049 #size-cells = <0>;
2055 reg = <0 0x00a94000 0 0x4000>;
2059 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
2064 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
2065 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
2066 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
2071 #size-cells = <0>;
2078 reg = <0 0x01500000 0 0xa580>;
2085 reg = <0 0x01620000 0 0x1c200>;
2092 reg = <0 0x0163d000 0 0x1000>;
2099 reg = <0 0x016e0000 0 0x1f180>;
2106 reg = <0 0x01700000 0 0x33000>;
2113 reg = <0 0x01733000 0 0xa180>;
2120 reg = <0 0x01740000 0 0x1f080>;
2127 reg = <0 0x01c00000 0 0x3000>,
2128 <0 0x60000000 0 0xf1d>,
2129 <0 0x60000f20 0 0xa8>,
2130 <0 0x60001000 0 0x1000>,
2131 <0 0x60100000 0 0x100000>,
2132 <0 0x01c03000 0 0x1000>;
2135 linux,pci-domain = <0>;
2136 bus-range = <0x00 0xff>;
2142 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
2143 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
2162 interrupt-map-mask = <0 0 0 0x7>;
2163 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2164 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2165 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2166 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2185 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
2186 <0x100 &apps_smmu 0x1c01 0x1>;
2200 pinctrl-0 = <&pcie0_default_state>;
2205 pcieport0: pcie@0 {
2207 reg = <0x0 0x0 0x0 0x0 0x0>;
2208 bus-range = <0x01 0xff>;
2218 reg = <0 0x01c06000 0 0x1000>;
2232 #clock-cells = <0>;
2234 #phy-cells = <0>;
2247 reg = <0 0x01c08000 0 0x3000>,
2248 <0 0x40000000 0 0xf1d>,
2249 <0 0x40000f20 0 0xa8>,
2250 <0 0x40001000 0 0x1000>,
2251 <0 0x40100000 0 0x100000>,
2252 <0 0x01c0b000 0 0x1000>;
2256 bus-range = <0x00 0xff>;
2262 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
2263 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2282 interrupt-map-mask = <0 0 0 0x7>;
2283 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2284 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2285 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2286 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2310 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2311 <0x100 &apps_smmu 0x1c81 0x1>;
2325 pinctrl-0 = <&pcie1_default_state>;
2330 pcie@0 {
2332 reg = <0x0 0x0 0x0 0x0 0x0>;
2333 bus-range = <0x01 0xff>;
2343 reg = <0 0x01c0e000 0 0x1000>;
2357 #clock-cells = <0>;
2359 #phy-cells = <0>;
2372 reg = <0 0x01c10000 0 0x3000>,
2373 <0 0x64000000 0 0xf1d>,
2374 <0 0x64000f20 0 0xa8>,
2375 <0 0x64001000 0 0x1000>,
2376 <0 0x64100000 0 0x100000>,
2377 <0 0x01c13000 0 0x1000>;
2381 bus-range = <0x00 0xff>;
2387 ranges = <0x01000000 0x0 0x00000000 0x0 0x64200000 0x0 0x100000>,
2388 <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>;
2407 interrupt-map-mask = <0 0 0 0x7>;
2408 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2409 <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2410 <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2411 <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2435 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
2436 <0x100 &apps_smmu 0x1d01 0x1>;
2450 pinctrl-0 = <&pcie2_default_state>;
2455 pcie@0 {
2457 reg = <0x0 0x0 0x0 0x0 0x0>;
2458 bus-range = <0x01 0xff>;
2468 reg = <0 0x01c16000 0 0x1000>;
2482 #clock-cells = <0>;
2484 #phy-cells = <0>;
2498 reg = <0 0x01d84000 0 0x3000>;
2509 iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>;
2532 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI_CH0 0>,
2533 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
2543 /bits/ 64 <0>,
2544 /bits/ 64 <0>,
2546 /bits/ 64 <0>,
2547 /bits/ 64 <0>,
2548 /bits/ 64 <0>,
2549 /bits/ 64 <0>;
2555 /bits/ 64 <0>,
2556 /bits/ 64 <0>,
2558 /bits/ 64 <0>,
2559 /bits/ 64 <0>,
2560 /bits/ 64 <0>,
2561 /bits/ 64 <0>;
2569 reg = <0 0x01d87000 0 0x1000>;
2578 resets = <&ufs_mem_hc 0>;
2583 #phy-cells = <0>;
2590 reg = <0 0x01dc4000 0 0x24000>;
2593 qcom,ee = <0>;
2597 iommus = <&apps_smmu 0x592 0x0000>,
2598 <&apps_smmu 0x598 0x0000>,
2599 <&apps_smmu 0x599 0x0000>,
2600 <&apps_smmu 0x59f 0x0000>,
2601 <&apps_smmu 0x586 0x0011>,
2602 <&apps_smmu 0x596 0x0011>;
2607 reg = <0 0x01dfa000 0 0x6000>;
2610 iommus = <&apps_smmu 0x592 0x0000>,
2611 <&apps_smmu 0x598 0x0000>,
2612 <&apps_smmu 0x599 0x0000>,
2613 <&apps_smmu 0x59f 0x0000>,
2614 <&apps_smmu 0x586 0x0011>,
2615 <&apps_smmu 0x596 0x0011>;
2616 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 0 &mc_virt SLAVE_EBI_CH0 0>;
2622 reg = <0x0 0x01f40000 0x0 0x40000>;
2628 reg = <0x0 0x1fc0000 0x0 0x30000>;
2633 reg = <0 0x03240000 0 0x1000>;
2642 #clock-cells = <0>;
2647 pinctrl-0 = <&wsa_swr_active>;
2653 reg = <0 0x03250000 0 0x2000>;
2662 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2663 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2664 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2665 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>;
2669 #size-cells = <0>;
2676 reg = <0 0x03370000 0 0x1000>;
2683 #clock-cells = <0>;
2690 pinctrl-0 = <&rx_swr_active>;
2692 reg = <0 0x03200000 0 0x1000>;
2703 #clock-cells = <0>;
2709 reg = <0 0x03210000 0 0x2000>;
2716 qcom,din-ports = <0>;
2719 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2720 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
2721 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2722 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2723 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2724 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2725 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2726 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2727 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2731 #size-cells = <0>;
2736 pinctrl-0 = <&tx_swr_active>;
2738 reg = <0 0x03220000 0 0x1000>;
2749 #clock-cells = <0>;
2756 reg = <0 0x03230000 0 0x2000>;
2767 qcom,dout-ports = <0>;
2768 qcom,ports-sinterval-low = /bits/ 8 <0xff 0x01 0x01 0x03 0x03>;
2769 qcom,ports-offset1 = /bits/ 8 <0xff 0x01 0x00 0x02 0x00>;
2770 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x00 0x00 0x00>;
2771 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2772 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2773 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2774 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2775 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2776 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x01 0x00 0x01>;
2779 #size-cells = <0>;
2784 reg = <0 0x033c0000 0x0 0x20000>,
2785 <0 0x03550000 0x0 0x10000>;
2788 gpio-ranges = <&lpass_tlmm 0 0 14>;
2923 reg = <0 0x03d00000 0 0x40000>;
2928 iommus = <&adreno_smmu 0 0x401>;
2950 opp-supported-hw = <0xa>;
2956 opp-supported-hw = <0xb>;
2962 opp-supported-hw = <0xf>;
2968 opp-supported-hw = <0xf>;
2974 opp-supported-hw = <0xf>;
2980 opp-supported-hw = <0xf>;
2986 opp-supported-hw = <0xf>;
2994 reg = <0 0x03d6a000 0 0x30000>,
2995 <0 0x3de0000 0 0x10000>,
2996 <0 0xb290000 0 0x10000>,
2997 <0 0xb490000 0 0x10000>;
3015 iommus = <&adreno_smmu 5 0x400>;
3033 reg = <0 0x03d90000 0 0x9000>;
3048 reg = <0 0x03da0000 0 0x10000>;
3072 reg = <0 0x05c00000 0 0x4000>;
3075 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
3093 qcom,smem-states = <&smp2p_slpi_out 0>;
3114 #size-cells = <0>;
3119 iommus = <&apps_smmu 0x0541 0x0>;
3125 iommus = <&apps_smmu 0x0542 0x0>;
3131 iommus = <&apps_smmu 0x0543 0x0>;
3140 reg = <0 0x06002000 0 0x1000>, <0 0x16280000 0 0x180000>;
3157 reg = <0 0x06004000 0 0x1000>;
3173 #size-cells = <0>;
3193 reg = <0 0x06005000 0 0x1000>;
3217 reg = <0 0x06041000 0 0x1000>;
3232 #size-cells = <0>;
3252 reg = <0 0x06042000 0 0x1000>;
3267 #size-cells = <0>;
3280 reg = <0 0x06045000 0 0x1000>;
3295 #size-cells = <0>;
3297 port@0 {
3298 reg = <0>;
3315 reg = <0 0x06046000 0 0x1000>;
3339 reg = <0 0x06048000 0 0x1000>;
3356 reg = <0 0x0684c000 0 0x1000>;
3372 arm,primecell-periphid = <0x000bb908>;
3374 reg = <0 0x06b04000 0 0x1000>;
3389 #size-cells = <0>;
3402 reg = <0 0x06b05000 0 0x1000>;
3427 reg = <0 0x06b06000 0 0x1000>;
3451 reg = <0 0x06c08000 0 0x1000>;
3467 reg = <0 0x06c0b000 0 0x1000>;
3482 #size-cells = <0>;
3495 reg = <0 0x06c2d000 0 0x1000>;
3510 #size-cells = <0>;
3523 reg = <0 0x07040000 0 0x1000>;
3542 reg = <0 0x07140000 0 0x1000>;
3561 reg = <0 0x07240000 0 0x1000>;
3580 reg = <0 0x07340000 0 0x1000>;
3599 reg = <0 0x07440000 0 0x1000>;
3618 reg = <0 0x07540000 0 0x1000>;
3637 reg = <0 0x07640000 0 0x1000>;
3656 reg = <0 0x07740000 0 0x1000>;
3675 reg = <0 0x07800000 0 0x1000>;
3690 #size-cells = <0>;
3692 port@0 {
3693 reg = <0>;
3752 reg = <0 0x07810000 0 0x1000>;
3776 reg = <0 0x08300000 0 0x10000>;
3779 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
3795 qcom,smem-states = <&smp2p_cdsp_out 0>;
3816 #size-cells = <0>;
3821 iommus = <&apps_smmu 0x1001 0x0460>;
3827 iommus = <&apps_smmu 0x1002 0x0460>;
3833 iommus = <&apps_smmu 0x1003 0x0460>;
3839 iommus = <&apps_smmu 0x1004 0x0460>;
3845 iommus = <&apps_smmu 0x1005 0x0460>;
3851 iommus = <&apps_smmu 0x1006 0x0460>;
3857 iommus = <&apps_smmu 0x1007 0x0460>;
3863 iommus = <&apps_smmu 0x1008 0x0460>;
3874 reg = <0 0x088e3000 0 0x400>;
3876 #phy-cells = <0>;
3887 reg = <0 0x088e4000 0 0x400>;
3889 #phy-cells = <0>;
3899 reg = <0 0x088e8000 0 0x3000>;
3922 #size-cells = <0>;
3924 port@0 {
3925 reg = <0>;
3947 reg = <0 0x088eb000 0 0x1000>;
3958 #clock-cells = <0>;
3959 #phy-cells = <0>;
3971 reg = <0 0x08804000 0 0x1000>;
3981 iommus = <&apps_smmu 0x4a0 0x0>;
3982 qcom,dll-config = <0x0007642c>;
3983 qcom,ddr-config = <0x80040868>;
4016 reg = <0 0x09091000 0 0x1000>;
4078 reg = <0 0x090b6400 0 0x600>;
4138 reg = <0 0x090c0000 0 0x4200>;
4145 reg = <0 0x09100000 0 0xb4000>;
4152 reg = <0 0x09990000 0 0x1600>;
4159 reg = <0 0x0a6f8800 0 0x400>;
4199 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>,
4200 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
4205 reg = <0 0x0a600000 0 0xcd00>;
4207 iommus = <&apps_smmu 0x0 0x0>;
4215 #size-cells = <0>;
4217 port@0 {
4218 reg = <0>;
4237 reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>,
4238 <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>,
4239 <0 0x09600000 0 0x50000>;
4246 reg = <0 0x0a8f8800 0 0x400>;
4286 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>,
4287 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>;
4292 reg = <0 0x0a800000 0 0xcd00>;
4294 iommus = <&apps_smmu 0x20 0>;
4304 reg = <0 0x0aa00000 0 0x100000>;
4317 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_VENUS_CFG 0>,
4318 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI_CH0 0>;
4321 iommus = <&apps_smmu 0x2100 0x0400>;
4365 reg = <0 0x0abf0000 0 0x10000>;
4380 #size-cells = <0>;
4382 reg = <0 0x0ac4f000 0 0x1000>;
4397 pinctrl-0 = <&cci0_default>;
4403 cci0_i2c0: i2c-bus@0 {
4404 reg = <0>;
4407 #size-cells = <0>;
4414 #size-cells = <0>;
4421 #size-cells = <0>;
4423 reg = <0 0x0ac50000 0 0x1000>;
4438 pinctrl-0 = <&cci1_default>;
4444 cci1_i2c0: i2c-bus@0 {
4445 reg = <0>;
4448 #size-cells = <0>;
4455 #size-cells = <0>;
4463 reg = <0 0x0ac6a000 0 0x2000>,
4464 <0 0x0ac6c000 0 0x2000>,
4465 <0 0x0ac6e000 0 0x1000>,
4466 <0 0x0ac70000 0 0x1000>,
4467 <0 0x0ac72000 0 0x1000>,
4468 <0 0x0ac74000 0 0x1000>,
4469 <0 0x0acb4000 0 0xd000>,
4470 <0 0x0acc3000 0 0xd000>,
4471 <0 0x0acd9000 0 0x2200>,
4472 <0 0x0acdb200 0 0x2200>;
4593 iommus = <&apps_smmu 0x800 0x400>,
4594 <&apps_smmu 0x801 0x400>,
4595 <&apps_smmu 0x840 0x400>,
4596 <&apps_smmu 0x841 0x400>,
4597 <&apps_smmu 0xc00 0x400>,
4598 <&apps_smmu 0xc01 0x400>,
4599 <&apps_smmu 0xc40 0x400>,
4600 <&apps_smmu 0xc41 0x400>;
4602 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_CAMERA_CFG 0>,
4603 <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI_CH0 0>,
4604 <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI_CH0 0>,
4605 <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI_CH0 0>;
4613 #size-cells = <0>;
4615 port@0 {
4616 reg = <0>;
4643 reg = <0 0x0ad00000 0 0x10000>;
4659 reg = <0 0x0ae00000 0 0x1000>;
4662 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>,
4663 <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>;
4678 iommus = <&apps_smmu 0x820 0x402>;
4688 reg = <0 0x0ae01000 0 0x8f000>,
4689 <0 0x0aeb0000 0 0x2008>;
4705 interrupts = <0>;
4709 #size-cells = <0>;
4711 port@0 {
4712 reg = <0>;
4761 reg = <0 0xae90000 0 0x200>,
4762 <0 0xae90200 0 0x200>,
4763 <0 0xae90400 0 0x600>,
4764 <0 0xae91000 0 0x400>,
4765 <0 0xae91400 0 0x400>;
4787 #sound-dai-cells = <0>;
4796 #size-cells = <0>;
4798 port@0 {
4799 reg = <0>;
4841 reg = <0 0x0ae94000 0 0x400>;
4861 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
4871 #size-cells = <0>;
4875 #size-cells = <0>;
4877 port@0 {
4878 reg = <0>;
4913 reg = <0 0x0ae94400 0 0x200>,
4914 <0 0x0ae94600 0 0x280>,
4915 <0 0x0ae94900 0 0x260>;
4921 #phy-cells = <0>;
4933 reg = <0 0x0ae96000 0 0x400>;
4953 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
4963 #size-cells = <0>;
4967 #size-cells = <0>;
4969 port@0 {
4970 reg = <0>;
4986 reg = <0 0x0ae96400 0 0x200>,
4987 <0 0x0ae96600 0 0x280>,
4988 <0 0x0ae96900 0 0x260>;
4994 #phy-cells = <0>;
5006 reg = <0 0x0af00000 0 0x10000>;
5010 <&mdss_dsi0_phy 0>,
5012 <&mdss_dsi1_phy 0>,
5030 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
5031 qcom,pdc-ranges = <0 480 94>, <94 609 31>,
5040 reg = <0 0x0c263000 0 0x1ff>, /* TM */
5041 <0 0x0c222000 0 0x1ff>; /* SROT */
5051 reg = <0 0x0c265000 0 0x1ff>, /* TM */
5052 <0 0x0c223000 0 0x1ff>; /* SROT */
5062 reg = <0 0x0c300000 0 0x400>;
5069 #clock-cells = <0>;
5074 reg = <0 0x0c3f0000 0 0x400>;
5079 reg = <0x0 0x0c440000 0x0 0x0001100>,
5080 <0x0 0x0c600000 0x0 0x2000000>,
5081 <0x0 0x0e600000 0x0 0x0100000>,
5082 <0x0 0x0e700000 0x0 0x00a0000>,
5083 <0x0 0x0c40a000 0x0 0x0026000>;
5087 qcom,ee = <0>;
5088 qcom,channel = <0>;
5090 #size-cells = <0>;
5097 reg = <0 0x0f100000 0 0x300000>,
5098 <0 0x0f500000 0 0x300000>,
5099 <0 0x0f900000 0 0x300000>;
5106 gpio-ranges = <&tlmm 0 0 181>;
5854 reg = <0 0x15000000 0 0x100000>;
5960 reg = <0 0x17300000 0 0x100>;
5963 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
5981 qcom,smem-states = <&smp2p_adsp_out 0>;
6001 #size-cells = <0>;
6016 #size-cells = <0>;
6033 #size-cells = <0>;
6035 iommus = <&apps_smmu 0x1801 0x0>;
6045 #sound-dai-cells = <0>;
6056 #size-cells = <0>;
6061 iommus = <&apps_smmu 0x1803 0x0>;
6067 iommus = <&apps_smmu 0x1804 0x0>;
6073 iommus = <&apps_smmu 0x1805 0x0>;
6083 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
6084 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
6090 reg = <0 0x17c10000 0 0x1000>;
6092 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
6098 ranges = <0 0 0 0x20000000>;
6100 reg = <0x0 0x17c20000 0x0 0x1000>;
6104 frame-number = <0>;
6107 reg = <0x17c21000 0x1000>,
6108 <0x17c22000 0x1000>;
6114 reg = <0x17c23000 0x1000>;
6121 reg = <0x17c25000 0x1000>;
6128 reg = <0x17c27000 0x1000>;
6135 reg = <0x17c29000 0x1000>;
6142 reg = <0x17c2b000 0x1000>;
6149 reg = <0x17c2d000 0x1000>;
6157 reg = <0x0 0x18200000 0x0 0x10000>,
6158 <0x0 0x18210000 0x0 0x10000>,
6159 <0x0 0x18220000 0x0 0x10000>;
6160 reg-names = "drv-0", "drv-1", "drv-2";
6164 qcom,tcs-offset = <0xd00>;
6234 reg = <0 0x18590000 0 0x1000>;
6244 reg = <0 0x18591000 0 0x1000>,
6245 <0 0x18592000 0 0x1000>,
6246 <0 0x18593000 0 0x1000>;
6255 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
6796 thermal-sensors = <&tsens0 0>;
6881 thermal-sensors = <&tsens1 0>;