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Searched defs:_bit (Results 1 – 25 of 41) sorted by relevance

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/linux/drivers/reset/sti/
H A Dreset-stih407.c18 #define STIH407_PDN_0(_bit) \ argument
20 #define STIH407_PDN_1(_bit) \ argument
22 #define STIH407_PDN_ETH(_bit, _stat) \ argument
57 #define STIH407_SRST_CORE(_reg, _bit) \ argument
60 #define STIH407_SRST_SBC(_reg, _bit) \ argument
63 #define STIH407_SRST_LPM(_reg, _bit) \ argument
/linux/sound/soc/mediatek/mt8195/
H A Dmt8195-audsys-clk.c28 #define GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, _flags, _cgflags) {\ argument
38 #define GATE_AFE(_id, _name, _parent, _reg, _bit) \ argument
42 #define GATE_AUD0(_id, _name, _parent, _bit) \ argument
45 #define GATE_AUD1(_id, _name, _parent, _bit) \ argument
48 #define GATE_AUD3(_id, _name, _parent, _bit) \ argument
51 #define GATE_AUD4(_id, _name, _parent, _bit) \ argument
54 #define GATE_AUD5(_id, _name, _parent, _bit) \ argument
57 #define GATE_AUD6(_id, _name, _parent, _bit) \ argument
/linux/sound/soc/mediatek/mt8188/
H A Dmt8188-audsys-clk.c28 #define GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, _flags, _cgflags) {\ argument
38 #define GATE_AFE(_id, _name, _parent, _reg, _bit) \ argument
42 #define GATE_AUD0(_id, _name, _parent, _bit) \ argument
45 #define GATE_AUD1(_id, _name, _parent, _bit) \ argument
48 #define GATE_AUD3(_id, _name, _parent, _bit) \ argument
51 #define GATE_AUD4(_id, _name, _parent, _bit) \ argument
54 #define GATE_AUD5(_id, _name, _parent, _bit) \ argument
57 #define GATE_AUD6(_id, _name, _parent, _bit) \ argument
/linux/sound/soc/mediatek/mt8186/
H A Dmt8186-audsys-clk.c27 #define GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, _flags, _cgflags) {\ argument
37 #define GATE_AFE(_id, _name, _parent, _reg, _bit) \ argument
41 #define GATE_AUD0(_id, _name, _parent, _bit) \ argument
44 #define GATE_AUD1(_id, _name, _parent, _bit) \ argument
47 #define GATE_AUD2(_id, _name, _parent, _bit) \ argument
/linux/drivers/clk/meson/
H A Dmeson-clkc-utils.h30 #define __MESON_PCLK(_name, _reg, _bit, _ops, _pdata, _flags) \ argument
45 #define MESON_PCLK(_name, _reg, _bit, _pdata, _flags) \ argument
48 #define MESON_PCLK_RO(_name, _reg, _bit, _pdata, _flags) \ argument
91 #define MESON_COMP_GATE(_prefix, _name, _reg, _bit, _iflags) \ argument
H A Dc3-peripherals.c57 #define C3_COMP_GATE(_name, _reg, _bit) \ argument
178 #define C3_SYS_PCLK(_name, _reg, _bit, _flags) \ argument
181 #define C3_SYS_PCLK_RO(_name, _reg, _bit) \ argument
287 #define C3_AXI_PCLK(_name, _reg, _bit, _flags) \ argument
H A Da9-aoclk.c34 #define A9_COMP_GATE(_name, _reg, _bit) \ argument
90 #define A9_AO_PCLK(_name, _bit, _flags) \ argument
H A Da9-peripherals.c84 #define A9_COMP_GATE(_name, _reg, _bit, _iflags) \ argument
89 #define A9_SYS_PCLK(_name, _reg, _bit) \ argument
1318 #define A9_VCLK_GATE(_name, _reg, _bit, _parent) \ argument
H A Dgxbb-aoclk.c28 #define GXBB_AO_PCLK(_name, _bit, _flags) \ argument
H A Daxg-aoclk.c39 #define AXG_AO_GATE(_name, _bit, _flags) \ argument
H A Dg12a-aoclk.c42 #define G12A_AO_PCLK(_name, _reg, _bit, _flags) \ argument
/linux/drivers/clk/renesas/
H A Drzg2l-cpg.h226 #define DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _mstop_conf, _is_coupled) \ argument
237 #define DEF_MOD(_name, _id, _parent, _off, _bit, _mstop_conf) \ argument
240 #define DEF_COUPLED(_name, _id, _parent, _off, _bit, _mstop_conf) \ argument
256 #define DEF_RST_MON(_id, _off, _bit, _monbit) \ argument
262 #define DEF_RST(_id, _off, _bit) \ argument
/linux/arch/sh/kernel/cpu/sh4a/
H A Dclock-sh7366.c108 #define DIV4(_reg, _bit, _mask, _flags) \ argument
128 #define MSTP(_parent, _reg, _bit, _flags) \ argument
H A Dclock-sh7343.c105 #define DIV4(_reg, _bit, _mask, _flags) \ argument
125 #define MSTP(_parent, _reg, _bit, _flags) \ argument
H A Dclock-sh7757.c62 #define DIV4(_bit, _mask, _flags) \ argument
H A Dclock-shx3.c61 #define DIV4(_bit, _mask, _flags) \ argument
H A Dclock-sh7785.c66 #define DIV4(_bit, _mask, _flags) \ argument
/linux/drivers/reset/
H A Dreset-uniphier.c27 #define UNIPHIER_RESET(_id, _reg, _bit) \ argument
34 #define UNIPHIER_RESETX(_id, _reg, _bit) \ argument
/linux/drivers/net/wireless/morsemicro/mm81x/
H A Dmac.c338 #define __FW_CAP_N(_n, _cap, _bit) \ in mm81x_mac_caps_init() argument
344 #define FW_CAP0(_cap, _bit) __FW_CAP_N(0, _cap, _bit) in mm81x_mac_caps_init() argument
345 #define FW_CAP3(_cap, _bit) __FW_CAP_N(3, _cap, _bit) in mm81x_mac_caps_init() argument
346 #define FW_CAP5(_cap, _bit) __FW_CAP_N(5, _cap, _bit) in mm81x_mac_caps_init() argument
347 #define FW_CAP6(_cap, _bit) __FW_CAP_N(6, _cap, _bit) in mm81x_mac_caps_init() argument
348 #define FW_CAP7(_cap, _bit) __FW_CAP_N(7, _cap, _bit) in mm81x_mac_caps_init() argument
349 #define FW_CAP8(_cap, _bit) __FW_CAP_N(8, _cap, _bit) in mm81x_mac_caps_init() argument
350 #define FW_CAP9(_cap, _bit) __FW_CAP_N(9, _cap, _bit) in mm81x_mac_caps_init() argument
/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mt2701.c30 #define MTK_PINMUX_SPEC(_pin, _offset, _bit) \ argument
/linux/drivers/clk/ultrarisc/
H A Dclk-dp1000.c67 #define DP1000_GATE(_id, _name, _parent, _bit) \ argument
/linux/arch/sh/kernel/cpu/sh2a/
H A Dclock-sh7264.c77 #define DIV4(_reg, _bit, _mask, _flags) \ argument
H A Dclock-sh7269.c105 #define DIV4(_reg, _bit, _mask, _flags) \ argument
/linux/drivers/clk/bcm/
H A Dclk-kona.h91 #define POLICY(_offset, _bit) \ argument
375 #define TRIGGER(_offset, _bit) \ argument
434 #define CCU_LVM_EN(_offset, _bit) \ argument
/linux/drivers/clk/
H A Dclk-k230.c58 _reg, _bit, _method, _reg2, \ argument
85 _reg, _bit, _method, _reg2, \ argument
110 _reg, _bit, _flags, _gate_flags, \ argument
124 _reg, _bit, _flags, _gate_flags, \ argument

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