1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT) 2 /* 3 * Copyright (C) 2026 Amlogic, Inc. All rights reserved 4 */ 5 6 #include <dt-bindings/clock/amlogic,a9-aoclkc.h> 7 #include <linux/clk-provider.h> 8 #include <linux/module.h> 9 #include <linux/platform_device.h> 10 #include "clk-regmap.h" 11 #include "clk-dualdiv.h" 12 #include "meson-clkc-utils.h" 13 14 #define AO_OSCIN_CTRL 0x00 15 #define AO_SYS_CLK0 0x04 16 #define AO_PWM_CLK_A_CTRL 0x1c 17 #define AO_PWM_CLK_B_CTRL 0x20 18 #define AO_PWM_CLK_C_CTRL 0x24 19 #define AO_PWM_CLK_D_CTRL 0x28 20 #define AO_PWM_CLK_E_CTRL 0x2c 21 #define AO_PWM_CLK_F_CTRL 0x30 22 #define AO_PWM_CLK_G_CTRL 0x34 23 #define AO_CEC_CTRL0 0x38 24 #define AO_CEC_CTRL1 0x3c 25 #define AO_RTC_BY_OSCIN_CTRL0 0x50 26 #define AO_RTC_BY_OSCIN_CTRL1 0x54 27 28 #define A9_COMP_SEL(_name, _reg, _shift, _mask, _pdata) \ 29 MESON_COMP_SEL(a9_ao_, _name, _reg, _shift, _mask, _pdata, NULL, 0, 0) 30 31 #define A9_COMP_DIV(_name, _reg, _shift, _width) \ 32 MESON_COMP_DIV(a9_ao_, _name, _reg, _shift, _width, 0, CLK_SET_RATE_PARENT) 33 34 #define A9_COMP_GATE(_name, _reg, _bit) \ 35 MESON_COMP_GATE(a9_ao_, _name, _reg, _bit, CLK_SET_RATE_PARENT) 36 37 static struct clk_regmap a9_ao_xtal_in = { 38 .data = &(struct clk_regmap_gate_data){ 39 .offset = AO_OSCIN_CTRL, 40 .bit_idx = 3, 41 }, 42 .hw.init = &(struct clk_init_data) { 43 .name = "ao_xtal_in", 44 .ops = &clk_regmap_gate_ops, 45 .parent_data = &(const struct clk_parent_data) { 46 .fw_name = "xtal", 47 }, 48 .num_parents = 1, 49 }, 50 }; 51 52 static struct clk_regmap a9_ao_xtal = { 53 .data = &(struct clk_regmap_mux_data) { 54 .offset = AO_OSCIN_CTRL, 55 .mask = 0x1, 56 .shift = 0, 57 }, 58 .hw.init = &(struct clk_init_data){ 59 .name = "ao_xtal", 60 .ops = &clk_regmap_mux_ops, 61 /* ext_32k is from external PAD, do not automatically reparent */ 62 .parent_data = (const struct clk_parent_data []) { 63 { .hw = &a9_ao_xtal_in.hw }, 64 { .fw_name = "ext_32k", }, 65 }, 66 .num_parents = 2, 67 .flags = CLK_SET_RATE_NO_REPARENT, 68 }, 69 }; 70 71 static struct clk_regmap a9_ao_sys = { 72 .data = &(struct clk_regmap_mux_data) { 73 .offset = AO_OSCIN_CTRL, 74 .mask = 0x1, 75 .shift = 1, 76 }, 77 .hw.init = &(struct clk_init_data){ 78 .name = "ao_sys", 79 .ops = &clk_regmap_mux_ops, 80 .parent_data = (const struct clk_parent_data []) { 81 { .hw = &a9_ao_xtal.hw }, 82 { .fw_name = "sys", }, 83 }, 84 .num_parents = 2, 85 }, 86 }; 87 88 static const struct clk_parent_data a9_ao_pclk_parents = { .hw = &a9_ao_sys.hw }; 89 90 #define A9_AO_PCLK(_name, _bit, _flags) \ 91 MESON_PCLK(a9_ao_sys_##_name, AO_SYS_CLK0, _bit, \ 92 &a9_ao_pclk_parents, _flags) 93 94 /* 95 * A9 integrates a low-power microprocessor (Always-on CPU: AOCPU). Some AO sys 96 * clocks control the AOCPU modules. Mark the AOCPU-related clocks with 97 * CLK_IS_CRITICAL to avoid them being disabled and impacting AOCPU functionality. 98 * AOCPU-related clocks list: 99 * - clktree 100 * - rst_ctrl 101 * - pad 102 * - irq 103 * - pwrctrl 104 * - aocpu 105 * - sram 106 */ 107 static A9_AO_PCLK(i3c, 0, 0); 108 static A9_AO_PCLK(rtc_reg, 1, 0); 109 static A9_AO_PCLK(clktree, 2, CLK_IS_CRITICAL); 110 static A9_AO_PCLK(rst_ctrl, 3, CLK_IS_CRITICAL); 111 static A9_AO_PCLK(pad, 4, CLK_IS_CRITICAL); 112 static A9_AO_PCLK(rtc_dig, 5, 0); 113 static A9_AO_PCLK(irq, 6, CLK_IS_CRITICAL); 114 static A9_AO_PCLK(pwrctrl, 7, CLK_IS_CRITICAL); 115 static A9_AO_PCLK(pwm_a, 8, 0); 116 static A9_AO_PCLK(pwm_b, 9, 0); 117 static A9_AO_PCLK(pwm_c, 10, 0); 118 static A9_AO_PCLK(pwm_d, 11, 0); 119 static A9_AO_PCLK(pwm_e, 12, 0); 120 static A9_AO_PCLK(pwm_f, 13, 0); 121 static A9_AO_PCLK(pwm_g, 14, 0); 122 static A9_AO_PCLK(i2c_a, 15, 0); 123 static A9_AO_PCLK(i2c_b, 16, 0); 124 static A9_AO_PCLK(i2c_c, 17, 0); 125 static A9_AO_PCLK(i2c_d, 18, 0); 126 static A9_AO_PCLK(sed, 19, 0); 127 static A9_AO_PCLK(ir_ctrl, 20, 0); 128 static A9_AO_PCLK(uart_b, 21, 0); 129 static A9_AO_PCLK(uart_c, 22, 0); 130 static A9_AO_PCLK(uart_d, 23, 0); 131 static A9_AO_PCLK(uart_e, 24, 0); 132 static A9_AO_PCLK(spisg_0, 25, 0); 133 static A9_AO_PCLK(rtc_secure, 26, 0); 134 static A9_AO_PCLK(cec, 27, 0); 135 static A9_AO_PCLK(aocpu, 28, CLK_IS_CRITICAL); 136 static A9_AO_PCLK(sram, 29, CLK_IS_CRITICAL); 137 static A9_AO_PCLK(spisg_1, 30, 0); 138 static A9_AO_PCLK(spisg_2, 31, 0); 139 140 static const struct clk_parent_data a9_ao_pwm_parents[] = { 141 { .hw = &a9_ao_xtal.hw }, 142 { .fw_name = "fdiv5", }, 143 { .fw_name = "fdiv4", }, 144 { .fw_name = "fdiv3", } 145 }; 146 147 static A9_COMP_SEL(pwm_a, AO_PWM_CLK_A_CTRL, 9, 0x7, a9_ao_pwm_parents); 148 static A9_COMP_DIV(pwm_a, AO_PWM_CLK_A_CTRL, 0, 8); 149 static A9_COMP_GATE(pwm_a, AO_PWM_CLK_A_CTRL, 8); 150 151 static A9_COMP_SEL(pwm_b, AO_PWM_CLK_B_CTRL, 9, 0x7, a9_ao_pwm_parents); 152 static A9_COMP_DIV(pwm_b, AO_PWM_CLK_B_CTRL, 0, 8); 153 static A9_COMP_GATE(pwm_b, AO_PWM_CLK_B_CTRL, 8); 154 155 static A9_COMP_SEL(pwm_c, AO_PWM_CLK_C_CTRL, 9, 0x7, a9_ao_pwm_parents); 156 static A9_COMP_DIV(pwm_c, AO_PWM_CLK_C_CTRL, 0, 8); 157 static A9_COMP_GATE(pwm_c, AO_PWM_CLK_C_CTRL, 8); 158 159 static A9_COMP_SEL(pwm_d, AO_PWM_CLK_D_CTRL, 9, 0x7, a9_ao_pwm_parents); 160 static A9_COMP_DIV(pwm_d, AO_PWM_CLK_D_CTRL, 0, 8); 161 static A9_COMP_GATE(pwm_d, AO_PWM_CLK_D_CTRL, 8); 162 163 static A9_COMP_SEL(pwm_e, AO_PWM_CLK_E_CTRL, 9, 0x7, a9_ao_pwm_parents); 164 static A9_COMP_DIV(pwm_e, AO_PWM_CLK_E_CTRL, 0, 8); 165 static A9_COMP_GATE(pwm_e, AO_PWM_CLK_E_CTRL, 8); 166 167 static A9_COMP_SEL(pwm_f, AO_PWM_CLK_F_CTRL, 9, 0x7, a9_ao_pwm_parents); 168 static A9_COMP_DIV(pwm_f, AO_PWM_CLK_F_CTRL, 0, 8); 169 static A9_COMP_GATE(pwm_f, AO_PWM_CLK_F_CTRL, 8); 170 171 static A9_COMP_SEL(pwm_g, AO_PWM_CLK_G_CTRL, 9, 0x7, a9_ao_pwm_parents); 172 static A9_COMP_DIV(pwm_g, AO_PWM_CLK_G_CTRL, 0, 8); 173 static A9_COMP_GATE(pwm_g, AO_PWM_CLK_G_CTRL, 8); 174 175 static struct clk_regmap a9_ao_rtc_dualdiv_in = { 176 .data = &(struct clk_regmap_gate_data){ 177 .offset = AO_RTC_BY_OSCIN_CTRL0, 178 .bit_idx = 31, 179 }, 180 .hw.init = &(struct clk_init_data) { 181 .name = "ao_rtc_dualdiv_in", 182 .ops = &clk_regmap_gate_ops, 183 .parent_hws = (const struct clk_hw *[]) { 184 &a9_ao_xtal.hw 185 }, 186 .num_parents = 1, 187 }, 188 }; 189 190 static const struct meson_clk_dualdiv_param a9_ao_dualdiv_table[] = { 191 { 733, 732, 8, 11, 1 }, 192 { /* sentinel */ } 193 }; 194 195 static struct clk_regmap a9_ao_rtc_dualdiv_div = { 196 .data = &(struct meson_clk_dualdiv_data){ 197 .n1 = { 198 .reg_off = AO_RTC_BY_OSCIN_CTRL0, 199 .shift = 0, 200 .width = 12, 201 }, 202 .n2 = { 203 .reg_off = AO_RTC_BY_OSCIN_CTRL0, 204 .shift = 12, 205 .width = 12, 206 }, 207 .m1 = { 208 .reg_off = AO_RTC_BY_OSCIN_CTRL1, 209 .shift = 0, 210 .width = 12, 211 }, 212 .m2 = { 213 .reg_off = AO_RTC_BY_OSCIN_CTRL1, 214 .shift = 12, 215 .width = 12, 216 }, 217 .dual = { 218 .reg_off = AO_RTC_BY_OSCIN_CTRL0, 219 .shift = 28, 220 .width = 1, 221 }, 222 .table = a9_ao_dualdiv_table, 223 }, 224 .hw.init = &(struct clk_init_data){ 225 .name = "a9_ao_rtc_dualdiv_div", 226 .ops = &meson_clk_dualdiv_ops, 227 .parent_hws = (const struct clk_hw *[]) { 228 &a9_ao_rtc_dualdiv_in.hw 229 }, 230 .num_parents = 1, 231 }, 232 }; 233 234 static struct clk_regmap a9_ao_rtc_dualdiv_sel = { 235 .data = &(struct clk_regmap_mux_data) { 236 .offset = AO_RTC_BY_OSCIN_CTRL1, 237 .mask = 0x1, 238 .shift = 24, 239 }, 240 .hw.init = &(struct clk_init_data){ 241 .name = "ao_rtc_dualdiv_sel", 242 .ops = &clk_regmap_mux_ops, 243 .parent_hws = (const struct clk_hw *[]) { 244 &a9_ao_rtc_dualdiv_div.hw, 245 &a9_ao_rtc_dualdiv_in.hw, 246 }, 247 .num_parents = 2, 248 .flags = CLK_SET_RATE_PARENT, 249 }, 250 }; 251 252 static struct clk_regmap a9_ao_rtc_dualdiv = { 253 .data = &(struct clk_regmap_gate_data){ 254 .offset = AO_RTC_BY_OSCIN_CTRL0, 255 .bit_idx = 30, 256 }, 257 .hw.init = &(struct clk_init_data) { 258 .name = "ao_rtc_dualdiv", 259 .ops = &clk_regmap_gate_ops, 260 .parent_hws = (const struct clk_hw *[]) { 261 &a9_ao_rtc_dualdiv_sel.hw 262 }, 263 .num_parents = 1, 264 .flags = CLK_SET_RATE_PARENT, 265 }, 266 }; 267 268 static struct clk_regmap a9_ao_rtc = { 269 .data = &(struct clk_regmap_mux_data) { 270 .offset = AO_RTC_BY_OSCIN_CTRL1, 271 .mask = 0x1, 272 .shift = 30, 273 }, 274 .hw.init = &(struct clk_init_data){ 275 .name = "ao_rtc", 276 .ops = &clk_regmap_mux_ops, 277 .parent_hws = (const struct clk_hw *[]) { 278 &a9_ao_xtal.hw, 279 &a9_ao_rtc_dualdiv.hw, 280 }, 281 .num_parents = 2, 282 .flags = CLK_SET_RATE_PARENT, 283 }, 284 }; 285 286 static struct clk_regmap a9_ao_cec_dualdiv_in = { 287 .data = &(struct clk_regmap_gate_data){ 288 .offset = AO_CEC_CTRL0, 289 .bit_idx = 31, 290 }, 291 .hw.init = &(struct clk_init_data) { 292 .name = "ao_cec_dualdiv_in", 293 .ops = &clk_regmap_gate_ops, 294 .parent_hws = (const struct clk_hw *[]) { 295 &a9_ao_xtal.hw 296 }, 297 .num_parents = 1, 298 }, 299 }; 300 301 static struct clk_regmap a9_ao_cec_dualdiv_div = { 302 .data = &(struct meson_clk_dualdiv_data){ 303 .n1 = { 304 .reg_off = AO_CEC_CTRL0, 305 .shift = 0, 306 .width = 12, 307 }, 308 .n2 = { 309 .reg_off = AO_CEC_CTRL0, 310 .shift = 12, 311 .width = 12, 312 }, 313 .m1 = { 314 .reg_off = AO_CEC_CTRL1, 315 .shift = 0, 316 .width = 12, 317 }, 318 .m2 = { 319 .reg_off = AO_CEC_CTRL1, 320 .shift = 12, 321 .width = 12, 322 }, 323 .dual = { 324 .reg_off = AO_CEC_CTRL0, 325 .shift = 28, 326 .width = 1, 327 }, 328 .table = a9_ao_dualdiv_table, 329 }, 330 .hw.init = &(struct clk_init_data){ 331 .name = "ao_cec_dualdiv_div", 332 .ops = &meson_clk_dualdiv_ops, 333 .parent_hws = (const struct clk_hw *[]) { 334 &a9_ao_cec_dualdiv_in.hw 335 }, 336 .num_parents = 1, 337 }, 338 }; 339 340 static struct clk_regmap a9_ao_cec_dualdiv_sel = { 341 .data = &(struct clk_regmap_mux_data) { 342 .offset = AO_CEC_CTRL1, 343 .mask = 0x1, 344 .shift = 24, 345 }, 346 .hw.init = &(struct clk_init_data){ 347 .name = "ao_cec_dualdiv_sel", 348 .ops = &clk_regmap_mux_ops, 349 .parent_hws = (const struct clk_hw *[]) { 350 &a9_ao_cec_dualdiv_div.hw, 351 &a9_ao_cec_dualdiv_in.hw, 352 }, 353 .num_parents = 2, 354 .flags = CLK_SET_RATE_PARENT, 355 }, 356 }; 357 358 static struct clk_regmap a9_ao_cec_dualdiv = { 359 .data = &(struct clk_regmap_gate_data){ 360 .offset = AO_CEC_CTRL0, 361 .bit_idx = 30, 362 }, 363 .hw.init = &(struct clk_init_data){ 364 .name = "ao_cec_dualdiv", 365 .ops = &clk_regmap_gate_ops, 366 .parent_hws = (const struct clk_hw *[]) { 367 &a9_ao_cec_dualdiv_sel.hw 368 }, 369 .num_parents = 1, 370 .flags = CLK_SET_RATE_PARENT, 371 }, 372 }; 373 374 static struct clk_regmap a9_ao_cec = { 375 .data = &(struct clk_regmap_mux_data) { 376 .offset = AO_CEC_CTRL1, 377 .mask = 0x1, 378 .shift = 30, 379 }, 380 .hw.init = &(struct clk_init_data){ 381 .name = "ao_cec", 382 .ops = &clk_regmap_mux_ops, 383 .parent_hws = (const struct clk_hw *[]) { 384 &a9_ao_cec_dualdiv.hw, 385 &a9_ao_rtc.hw, 386 }, 387 .num_parents = 2, 388 .flags = CLK_SET_RATE_PARENT, 389 }, 390 }; 391 392 static struct clk_hw *a9_ao_hw_clks[] = { 393 [CLKID_AO_XTAL_IN] = &a9_ao_xtal_in.hw, 394 [CLKID_AO_XTAL] = &a9_ao_xtal.hw, 395 [CLKID_AO_SYS] = &a9_ao_sys.hw, 396 [CLKID_AO_SYS_I3C] = &a9_ao_sys_i3c.hw, 397 [CLKID_AO_SYS_RTC_REG] = &a9_ao_sys_rtc_reg.hw, 398 [CLKID_AO_SYS_CLKTREE] = &a9_ao_sys_clktree.hw, 399 [CLKID_AO_SYS_RST_CTRL] = &a9_ao_sys_rst_ctrl.hw, 400 [CLKID_AO_SYS_PAD] = &a9_ao_sys_pad.hw, 401 [CLKID_AO_SYS_RTC_DIG] = &a9_ao_sys_rtc_dig.hw, 402 [CLKID_AO_SYS_IRQ] = &a9_ao_sys_irq.hw, 403 [CLKID_AO_SYS_PWRCTRL] = &a9_ao_sys_pwrctrl.hw, 404 [CLKID_AO_SYS_PWM_A] = &a9_ao_sys_pwm_a.hw, 405 [CLKID_AO_SYS_PWM_B] = &a9_ao_sys_pwm_b.hw, 406 [CLKID_AO_SYS_PWM_C] = &a9_ao_sys_pwm_c.hw, 407 [CLKID_AO_SYS_PWM_D] = &a9_ao_sys_pwm_d.hw, 408 [CLKID_AO_SYS_PWM_E] = &a9_ao_sys_pwm_e.hw, 409 [CLKID_AO_SYS_PWM_F] = &a9_ao_sys_pwm_f.hw, 410 [CLKID_AO_SYS_PWM_G] = &a9_ao_sys_pwm_g.hw, 411 [CLKID_AO_SYS_I2C_A] = &a9_ao_sys_i2c_a.hw, 412 [CLKID_AO_SYS_I2C_B] = &a9_ao_sys_i2c_b.hw, 413 [CLKID_AO_SYS_I2C_C] = &a9_ao_sys_i2c_c.hw, 414 [CLKID_AO_SYS_I2C_D] = &a9_ao_sys_i2c_d.hw, 415 [CLKID_AO_SYS_SED] = &a9_ao_sys_sed.hw, 416 [CLKID_AO_SYS_IR_CTRL] = &a9_ao_sys_ir_ctrl.hw, 417 [CLKID_AO_SYS_UART_B] = &a9_ao_sys_uart_b.hw, 418 [CLKID_AO_SYS_UART_C] = &a9_ao_sys_uart_c.hw, 419 [CLKID_AO_SYS_UART_D] = &a9_ao_sys_uart_d.hw, 420 [CLKID_AO_SYS_UART_E] = &a9_ao_sys_uart_e.hw, 421 [CLKID_AO_SYS_SPISG_0] = &a9_ao_sys_spisg_0.hw, 422 [CLKID_AO_SYS_RTC_SECURE] = &a9_ao_sys_rtc_secure.hw, 423 [CLKID_AO_SYS_CEC] = &a9_ao_sys_cec.hw, 424 [CLKID_AO_SYS_AOCPU] = &a9_ao_sys_aocpu.hw, 425 [CLKID_AO_SYS_SRAM] = &a9_ao_sys_sram.hw, 426 [CLKID_AO_SYS_SPISG_1] = &a9_ao_sys_spisg_1.hw, 427 [CLKID_AO_SYS_SPISG_2] = &a9_ao_sys_spisg_2.hw, 428 [CLKID_AO_PWM_A_SEL] = &a9_ao_pwm_a_sel.hw, 429 [CLKID_AO_PWM_A_DIV] = &a9_ao_pwm_a_div.hw, 430 [CLKID_AO_PWM_A] = &a9_ao_pwm_a.hw, 431 [CLKID_AO_PWM_B_SEL] = &a9_ao_pwm_b_sel.hw, 432 [CLKID_AO_PWM_B_DIV] = &a9_ao_pwm_b_div.hw, 433 [CLKID_AO_PWM_B] = &a9_ao_pwm_b.hw, 434 [CLKID_AO_PWM_C_SEL] = &a9_ao_pwm_c_sel.hw, 435 [CLKID_AO_PWM_C_DIV] = &a9_ao_pwm_c_div.hw, 436 [CLKID_AO_PWM_C] = &a9_ao_pwm_c.hw, 437 [CLKID_AO_PWM_D_SEL] = &a9_ao_pwm_d_sel.hw, 438 [CLKID_AO_PWM_D_DIV] = &a9_ao_pwm_d_div.hw, 439 [CLKID_AO_PWM_D] = &a9_ao_pwm_d.hw, 440 [CLKID_AO_PWM_E_SEL] = &a9_ao_pwm_e_sel.hw, 441 [CLKID_AO_PWM_E_DIV] = &a9_ao_pwm_e_div.hw, 442 [CLKID_AO_PWM_E] = &a9_ao_pwm_e.hw, 443 [CLKID_AO_PWM_F_SEL] = &a9_ao_pwm_f_sel.hw, 444 [CLKID_AO_PWM_F_DIV] = &a9_ao_pwm_f_div.hw, 445 [CLKID_AO_PWM_F] = &a9_ao_pwm_f.hw, 446 [CLKID_AO_PWM_G_SEL] = &a9_ao_pwm_g_sel.hw, 447 [CLKID_AO_PWM_G_DIV] = &a9_ao_pwm_g_div.hw, 448 [CLKID_AO_PWM_G] = &a9_ao_pwm_g.hw, 449 [CLKID_AO_RTC_DUALDIV_IN] = &a9_ao_rtc_dualdiv_in.hw, 450 [CLKID_AO_RTC_DUALDIV_DIV] = &a9_ao_rtc_dualdiv_div.hw, 451 [CLKID_AO_RTC_DUALDIV_SEL] = &a9_ao_rtc_dualdiv_sel.hw, 452 [CLKID_AO_RTC_DUALDIV] = &a9_ao_rtc_dualdiv.hw, 453 [CLKID_AO_RTC] = &a9_ao_rtc.hw, 454 [CLKID_AO_CEC_DUALDIV_IN] = &a9_ao_cec_dualdiv_in.hw, 455 [CLKID_AO_CEC_DUALDIV_DIV] = &a9_ao_cec_dualdiv_div.hw, 456 [CLKID_AO_CEC_DUALDIV_SEL] = &a9_ao_cec_dualdiv_sel.hw, 457 [CLKID_AO_CEC_DUALDIV] = &a9_ao_cec_dualdiv.hw, 458 [CLKID_AO_CEC] = &a9_ao_cec.hw, 459 }; 460 461 static const struct meson_clkc_data a9_ao_clkc_data = { 462 .hw_clks = { 463 .hws = a9_ao_hw_clks, 464 .num = ARRAY_SIZE(a9_ao_hw_clks), 465 }, 466 }; 467 468 static const struct of_device_id a9_ao_clkc_match_table[] = { 469 { 470 .compatible = "amlogic,a9-aoclkc", 471 .data = &a9_ao_clkc_data, 472 }, 473 { } 474 }; 475 MODULE_DEVICE_TABLE(of, a9_ao_clkc_match_table); 476 477 static struct platform_driver a9_ao_clkc_driver = { 478 .probe = meson_clkc_mmio_probe, 479 .driver = { 480 .name = "a9-aoclkc", 481 .of_match_table = a9_ao_clkc_match_table, 482 }, 483 }; 484 module_platform_driver(a9_ao_clkc_driver); 485 486 MODULE_DESCRIPTION("Amlogic A9 Always-ON Clock Controller driver"); 487 MODULE_AUTHOR("Jian Hu <jian.hu@amlogic.com>"); 488 MODULE_LICENSE("GPL"); 489 MODULE_IMPORT_NS("CLK_MESON"); 490