1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Kendryte Canaan K230 Clock Drivers
4 *
5 * Author: Xukai Wang <kingxukai@zohomail.com>
6 * Author: Troy Mitchell <troymitchell988@gmail.com>
7 */
8
9 #include <linux/bitfield.h>
10 #include <linux/clk.h>
11 #include <linux/clkdev.h>
12 #include <linux/clk-provider.h>
13 #include <linux/iopoll.h>
14 #include <linux/platform_device.h>
15 #include <linux/rational.h>
16 #include <linux/spinlock.h>
17
18 #include <dt-bindings/clock/canaan,k230-clk.h>
19
20 /* PLL control register bits. */
21 #define K230_PLL_BYPASS_ENABLE BIT(19)
22 #define K230_PLL_GATE_ENABLE BIT(2)
23 #define K230_PLL_GATE_WRITE_ENABLE BIT(18)
24 #define K230_PLL_OD_MASK GENMASK(27, 24)
25 #define K230_PLL_R_MASK GENMASK(21, 16)
26 #define K230_PLL_F_MASK GENMASK(12, 0)
27 #define K230_PLL_DIV_REG_OFFSET 0x00
28 #define K230_PLL_BYPASS_REG_OFFSET 0x04
29 #define K230_PLL_GATE_REG_OFFSET 0x08
30 #define K230_PLL_LOCK_REG_OFFSET 0x0C
31
32 /* PLL lock register */
33 #define K230_PLL_LOCK_STATUS_MASK BIT(0)
34 #define K230_PLL_LOCK_TIME_DELAY 400
35 #define K230_PLL_LOCK_TIMEOUT 0
36
37 /* K230 CLK registers offset */
38 #define K230_CLK_AUDIO_CLKDIV_OFFSET 0x34
39 #define K230_CLK_PDM_CLKDIV_OFFSET 0x40
40 #define K230_CLK_CODEC_ADC_MCLKDIV_OFFSET 0x38
41 #define K230_CLK_CODEC_DAC_MCLKDIV_OFFSET 0x3c
42
43 #define K230_PLLX_DIV_ADDR(base, idx) \
44 (K230_PLL_DIV_REG_OFFSET + (base) + (idx) * 0x10)
45
46 #define K230_PLLX_BYPASS_ADDR(base, idx) \
47 (K230_PLL_BYPASS_REG_OFFSET + (base) + (idx) * 0x10)
48
49 #define K230_PLLX_GATE_ADDR(base, idx) \
50 (K230_PLL_GATE_REG_OFFSET + (base) + (idx) * 0x10)
51
52 #define K230_PLLX_LOCK_ADDR(base, idx) \
53 (K230_PLL_LOCK_REG_OFFSET + (base) + (idx) * 0x10)
54
55 #define K230_CLK_RATE_FORMAT_PNAME(_var, _id, \
56 _mul_min, _mul_max, _mul_shift, _mul_mask, \
57 _div_min, _div_max, _div_shift, _div_mask, \
58 _reg, _bit, _method, _reg2, \
59 _read_only, _flags, \
60 _pname) \
61 static struct k230_clk_rate _var = { \
62 .div_reg_off = _reg, \
63 .mul_reg_off = _reg2, \
64 .id = _id, \
65 .clk = { \
66 .write_enable_bit = _bit, \
67 .mul_min = _mul_min, \
68 .mul_max = _mul_max, \
69 .mul_shift = _mul_shift, \
70 .mul_mask = _mul_mask, \
71 .div_min = _div_min, \
72 .div_max = _div_max, \
73 .div_shift = _div_shift, \
74 .div_mask = _div_mask, \
75 .read_only = _read_only, \
76 .hw.init = CLK_HW_INIT_FW_NAME(#_var, \
77 _pname, &k230_clk_ops_##_method, \
78 _flags), \
79 }, \
80 }
81
82 #define K230_CLK_RATE_FORMAT(_var, _id, \
83 _mul_min, _mul_max, _mul_shift, _mul_mask, \
84 _div_min, _div_max, _div_shift, _div_mask, \
85 _reg, _bit, _method, _reg2, \
86 _read_only, _flags, \
87 _phw) \
88 static struct k230_clk_rate _var = { \
89 .div_reg_off = _reg, \
90 .mul_reg_off = _reg2, \
91 .id = _id, \
92 .clk = { \
93 .write_enable_bit = _bit, \
94 .mul_min = _mul_min, \
95 .mul_max = _mul_max, \
96 .mul_shift = _mul_shift, \
97 .mul_mask = _mul_mask, \
98 .div_min = _div_min, \
99 .div_max = _div_max, \
100 .div_shift = _div_shift, \
101 .div_mask = _div_mask, \
102 .read_only = _read_only, \
103 .hw.init = CLK_HW_INIT_HW(#_var, \
104 _phw, &k230_clk_ops_##_method, \
105 _flags), \
106 }, \
107 }
108
109 #define K230_CLK_GATE_FORMAT_PNAME(_var, _id, \
110 _reg, _bit, _flags, _gate_flags, \
111 _pname) \
112 static struct k230_clk_gate _var = { \
113 .reg_off = _reg, \
114 .id = _id, \
115 .clk = { \
116 .bit_idx = _bit, \
117 .flags = _gate_flags, \
118 .hw.init = CLK_HW_INIT_FW_NAME(#_var, \
119 _pname, &clk_gate_ops, _flags), \
120 }, \
121 }
122
123 #define K230_CLK_GATE_FORMAT(_var, _id, \
124 _reg, _bit, _flags, _gate_flags, \
125 _phw) \
126 static struct k230_clk_gate _var = { \
127 .reg_off = _reg, \
128 .id = _id, \
129 .clk = { \
130 .bit_idx = _bit, \
131 .flags = _gate_flags, \
132 .hw.init = CLK_HW_INIT_HW(#_var, \
133 _phw, &clk_gate_ops, _flags), \
134 }, \
135 }
136
137 #define K230_CLK_MUX_FORMAT(_var, _id, \
138 _reg, _shift, _mask, _flags, _mux_flags, _pdata) \
139 static struct k230_clk_mux _var = { \
140 .reg_off = _reg, \
141 .id = _id, \
142 .clk = { \
143 .flags = _mux_flags, \
144 .shift = _shift, \
145 .mask = _mask, \
146 .hw.init = CLK_HW_INIT_PARENTS_DATA(#_var, \
147 _pdata, &clk_mux_ops, _flags), \
148 }, \
149 }
150
151 #define K230_CLK_FIXED_FACTOR_FORMAT(_var, \
152 _mul, _div, _flags, \
153 _phw) \
154 static struct clk_fixed_factor _var = { \
155 .mult = _mul, \
156 .div = _div, \
157 .hw.init = CLK_HW_INIT_HW(#_var, \
158 _phw, &clk_fixed_factor_ops, _flags), \
159 }
160
161 #define K230_CLK_PLL_FORMAT(_var, _id, _flags, _pname) \
162 static struct k230_pll _var = { \
163 .hw.init = CLK_HW_INIT_FW_NAME(#_var, \
164 _pname, &k230_pll_ops, _flags), \
165 .id = _id, \
166 }
167
168 struct k230_pll {
169 struct clk_hw hw;
170 void __iomem *reg;
171 /* ensures mutual exclusion for concurrent register access. */
172 spinlock_t *lock;
173 int id;
174 };
175
176 #define hw_to_k230_pll(_hw) container_of(_hw, struct k230_pll, hw)
177
178 struct k230_clk_rate_self {
179 struct clk_hw hw;
180 void __iomem *reg;
181 bool read_only;
182 u32 write_enable_bit;
183 u32 mul_min;
184 u32 mul_max;
185 u32 mul_shift;
186 u32 mul_mask;
187 u32 div_min;
188 u32 div_max;
189 u32 div_shift;
190 u32 div_mask;
191 /* ensures mutual exclusion for concurrent register access. */
192 spinlock_t *lock;
193 };
194
195 #define hw_to_k230_clk_rate_self(_hw) container_of(_hw, \
196 struct k230_clk_rate_self, hw)
197
198 struct k230_clk_rate {
199 u32 mul_reg_off;
200 u32 div_reg_off;
201 struct k230_clk_rate_self clk;
202 int id;
203 };
204
hw_to_k230_clk_rate(struct clk_hw * hw)205 static inline struct k230_clk_rate *hw_to_k230_clk_rate(struct clk_hw *hw)
206 {
207 return container_of(hw_to_k230_clk_rate_self(hw), struct k230_clk_rate,
208 clk);
209 }
210
211 struct k230_clk_gate {
212 u32 reg_off;
213 struct clk_gate clk;
214 int id;
215 };
216
217 struct k230_clk_mux {
218 u32 reg_off;
219 struct clk_mux clk;
220 int id;
221 };
222
223 static int k230_pll_prepare(struct clk_hw *hw);
224 static int k230_pll_enable(struct clk_hw *hw);
225 static void k230_pll_disable(struct clk_hw *hw);
226 static int k230_pll_is_enabled(struct clk_hw *hw);
227 static unsigned long k230_pll_get_rate(struct clk_hw *hw, unsigned long parent_rate);
228 static int k230_clk_set_rate_mul(struct clk_hw *hw, unsigned long rate,
229 unsigned long parent_rate);
230 static int k230_clk_determine_rate_mul(struct clk_hw *hw, struct clk_rate_request *req);
231 static unsigned long k230_clk_get_rate_mul(struct clk_hw *hw,
232 unsigned long parent_rate);
233 static int k230_clk_set_rate_div(struct clk_hw *hw, unsigned long rate,
234 unsigned long parent_rate);
235 static int k230_clk_determine_rate_div(struct clk_hw *hw, struct clk_rate_request *req);
236 static unsigned long k230_clk_get_rate_div(struct clk_hw *hw,
237 unsigned long parent_rate);
238 static int k230_clk_set_rate_mul_div(struct clk_hw *hw, unsigned long rate,
239 unsigned long parent_rate);
240 static int k230_clk_determine_rate_mul_div(struct clk_hw *hw, struct clk_rate_request *req);
241 static unsigned long k230_clk_get_rate_mul_div(struct clk_hw *hw,
242 unsigned long parent_rate);
243
244 static const struct clk_ops k230_pll_ops = {
245 .prepare = k230_pll_prepare,
246 .enable = k230_pll_enable,
247 .disable = k230_pll_disable,
248 .is_enabled = k230_pll_is_enabled,
249 .recalc_rate = k230_pll_get_rate,
250 };
251
252 /* clk_ops for clocks whose rate is determined by a configurable multiplier */
253 static const struct clk_ops k230_clk_ops_mul = {
254 .set_rate = k230_clk_set_rate_mul,
255 .determine_rate = k230_clk_determine_rate_mul,
256 .recalc_rate = k230_clk_get_rate_mul,
257 };
258
259 /* clk_ops for clocks whose rate is determined by a configurable divider */
260 static const struct clk_ops k230_clk_ops_div = {
261 .set_rate = k230_clk_set_rate_div,
262 .determine_rate = k230_clk_determine_rate_div,
263 .recalc_rate = k230_clk_get_rate_div,
264 };
265
266 /* clk_ops for clocks whose rate is determined by both a multiplier and a divider */
267 static const struct clk_ops k230_clk_ops_mul_div = {
268 .set_rate = k230_clk_set_rate_mul_div,
269 .determine_rate = k230_clk_determine_rate_mul_div,
270 .recalc_rate = k230_clk_get_rate_mul_div,
271 };
272
273 K230_CLK_PLL_FORMAT(pll0, 0, CLK_IS_CRITICAL, NULL);
274 K230_CLK_PLL_FORMAT(pll1, 1, CLK_IS_CRITICAL, NULL);
275 K230_CLK_PLL_FORMAT(pll2, 2, CLK_IS_CRITICAL, NULL);
276 K230_CLK_PLL_FORMAT(pll3, 3, CLK_IS_CRITICAL, NULL);
277
278 static struct k230_pll *k230_plls[] = {
279 &pll0,
280 &pll1,
281 &pll2,
282 &pll3,
283 };
284
285 K230_CLK_FIXED_FACTOR_FORMAT(pll0_div2, 1, 2, 0, &pll0.hw);
286 K230_CLK_FIXED_FACTOR_FORMAT(pll0_div3, 1, 3, 0, &pll0.hw);
287 K230_CLK_FIXED_FACTOR_FORMAT(pll0_div4, 1, 4, 0, &pll0.hw);
288 K230_CLK_FIXED_FACTOR_FORMAT(pll0_div16, 1, 16, 0, &pll0.hw);
289 K230_CLK_FIXED_FACTOR_FORMAT(pll1_div2, 1, 2, 0, &pll1.hw);
290 K230_CLK_FIXED_FACTOR_FORMAT(pll1_div3, 1, 3, 0, &pll1.hw);
291 K230_CLK_FIXED_FACTOR_FORMAT(pll1_div4, 1, 4, 0, &pll1.hw);
292 K230_CLK_FIXED_FACTOR_FORMAT(pll2_div2, 1, 2, 0, &pll2.hw);
293 K230_CLK_FIXED_FACTOR_FORMAT(pll2_div3, 1, 3, 0, &pll2.hw);
294 K230_CLK_FIXED_FACTOR_FORMAT(pll2_div4, 1, 4, 0, &pll2.hw);
295 K230_CLK_FIXED_FACTOR_FORMAT(pll3_div2, 1, 2, 0, &pll3.hw);
296 K230_CLK_FIXED_FACTOR_FORMAT(pll3_div3, 1, 3, 0, &pll3.hw);
297 K230_CLK_FIXED_FACTOR_FORMAT(pll3_div4, 1, 4, 0, &pll3.hw);
298
299 static struct clk_fixed_factor *k230_pll_divs[] = {
300 &pll0_div2,
301 &pll0_div3,
302 &pll0_div4,
303 &pll0_div16,
304 &pll1_div2,
305 &pll1_div3,
306 &pll1_div4,
307 &pll2_div2,
308 &pll2_div3,
309 &pll2_div4,
310 &pll3_div2,
311 &pll3_div3,
312 &pll3_div4,
313 };
314
315 K230_CLK_GATE_FORMAT(cpu0_src_gate,
316 K230_CPU0_SRC_GATE,
317 0, 0, CLK_IS_CRITICAL, 0,
318 &pll0_div2.hw);
319
320 K230_CLK_RATE_FORMAT(cpu0_src_rate,
321 K230_CPU0_SRC_RATE,
322 1, 16, 1, 0xF,
323 16, 16, 0, 0x0,
324 0x0, 31, mul, 0x0,
325 false, 0,
326 &cpu0_src_gate.clk.hw);
327
328 K230_CLK_RATE_FORMAT(cpu0_axi_rate,
329 K230_CPU0_AXI_RATE,
330 1, 1, 0, 0,
331 1, 8, 6, 0x7,
332 0x0, 31, div, 0x0,
333 0, 0,
334 &cpu0_src_rate.clk.hw);
335
336 K230_CLK_GATE_FORMAT(cpu0_plic_gate,
337 K230_CPU0_PLIC_GATE,
338 0x0, 9, CLK_IS_CRITICAL, 0,
339 &cpu0_src_rate.clk.hw);
340
341 K230_CLK_RATE_FORMAT(cpu0_plic_rate,
342 K230_CPU0_PLIC_RATE,
343 1, 1, 0, 0,
344 1, 8, 10, 0x7,
345 0x0, 31, div, 0x0,
346 false, 0,
347 &cpu0_plic_gate.clk.hw);
348
349 K230_CLK_GATE_FORMAT(cpu0_noc_ddrcp4_gate,
350 K230_CPU0_NOC_DDRCP4_GATE,
351 0x60, 7, CLK_IS_CRITICAL, 0,
352 &cpu0_src_rate.clk.hw);
353
354 K230_CLK_GATE_FORMAT(cpu0_apb_gate,
355 K230_CPU0_APB_GATE,
356 0x0, 13, CLK_IS_CRITICAL, 0,
357 &pll0_div4.hw);
358
359 K230_CLK_RATE_FORMAT(cpu0_apb_rate,
360 K230_CPU0_APB_RATE,
361 1, 1, 0, 0,
362 1, 8, 15, 0x7,
363 0x0, 31, div, 0x0,
364 false, 0,
365 &cpu0_apb_gate.clk.hw);
366
367 static const struct clk_parent_data k230_cpu1_src_mux_pdata[] = {
368 { .hw = &pll1_div2.hw, },
369 { .hw = &pll3.hw, },
370 { .hw = &pll0.hw, },
371 };
372
373 K230_CLK_MUX_FORMAT(cpu1_src_mux,
374 K230_CPU1_SRC_MUX,
375 0x4, 1, 0x3,
376 0, 0,
377 k230_cpu1_src_mux_pdata);
378
379 K230_CLK_GATE_FORMAT(cpu1_src_gate,
380 K230_CPU1_SRC_GATE,
381 0x4, 0, CLK_IS_CRITICAL, 0,
382 &cpu1_src_mux.clk.hw);
383
384 K230_CLK_RATE_FORMAT(cpu1_src_rate,
385 K230_CPU1_SRC_RATE,
386 1, 1, 0, 0,
387 1, 8, 3, 0x7,
388 0x4, 31, div, 0x0,
389 false, 0,
390 &cpu1_src_gate.clk.hw);
391
392 K230_CLK_RATE_FORMAT(cpu1_axi_rate,
393 K230_CPU1_AXI_RATE,
394 1, 1, 0, 0,
395 1, 8, 12, 0x7,
396 0x4, 31, div, 0x0,
397 false, 0,
398 &cpu1_src_rate.clk.hw);
399
400 K230_CLK_GATE_FORMAT(cpu1_plic_gate,
401 K230_CPU1_PLIC_GATE,
402 0x4, 15, CLK_IS_CRITICAL, 0,
403 &cpu1_src_rate.clk.hw);
404
405 K230_CLK_RATE_FORMAT(cpu1_plic_rate,
406 K230_CPU1_PLIC_RATE,
407 1, 1, 0, 0,
408 1, 8, 16, 0x7,
409 0x4, 31, div, 0x0,
410 false, 0,
411 &cpu1_plic_gate.clk.hw);
412
413 K230_CLK_GATE_FORMAT(cpu1_apb_gate,
414 K230_CPU1_APB_GATE,
415 0x4, 19, CLK_IS_CRITICAL, 0,
416 &pll0_div4.hw);
417
418 K230_CLK_GATE_FORMAT_PNAME(pmu_apb_gate,
419 K230_PMU_APB_GATE,
420 0x10, 0, 0, 0,
421 "osc24m");
422
423 K230_CLK_GATE_FORMAT(hs_hclk_high_gate,
424 K230_HS_HCLK_HIGH_GATE,
425 0x18, 1, 0, 0,
426 &pll0_div4.hw);
427
428 K230_CLK_RATE_FORMAT(hs_hclk_high_rate,
429 K230_HS_HCLK_HIGH_RATE,
430 1, 1, 0, 0,
431 1, 8, 0, 0x7,
432 0x1C, 31, div, 0x0,
433 false, 0,
434 &hs_hclk_high_gate.clk.hw);
435
436 K230_CLK_GATE_FORMAT(hs_hclk_gate,
437 K230_HS_HCLK_GATE,
438 0x18, 0, 0, 0,
439 &hs_hclk_high_rate.clk.hw);
440
441 K230_CLK_RATE_FORMAT(hs_hclk_rate,
442 K230_HS_HCLK_RATE,
443 1, 1, 0, 0,
444 1, 8, 3, 0x7,
445 0x1C, 31, div, 0x0,
446 false, 0,
447 &hs_hclk_gate.clk.hw);
448
449 K230_CLK_GATE_FORMAT(hs_sd0_ahb_gate,
450 K230_HS_SD0_AHB_GATE,
451 0x18, 2, 0, 0,
452 &hs_hclk_rate.clk.hw);
453
454 K230_CLK_GATE_FORMAT(hs_sd1_ahb_gate,
455 K230_HS_SD1_AHB_GATE,
456 0x18, 3, 0, 0,
457 &hs_hclk_rate.clk.hw);
458
459 K230_CLK_GATE_FORMAT(hs_ssi1_ahb_gate,
460 K230_HS_SSI1_AHB_GATE,
461 0x18, 7, 0, 0,
462 &hs_hclk_rate.clk.hw);
463
464 K230_CLK_GATE_FORMAT(hs_ssi2_ahb_gate,
465 K230_HS_SSI2_AHB_GATE,
466 0x18, 8, 0, 0,
467 &hs_hclk_rate.clk.hw);
468
469 K230_CLK_GATE_FORMAT(hs_usb0_ahb_gate,
470 K230_HS_USB0_AHB_GATE,
471 0x18, 4, 0, 0,
472 &hs_hclk_rate.clk.hw);
473
474 K230_CLK_GATE_FORMAT(hs_usb1_ahb_gate,
475 K230_HS_USB1_AHB_GATE,
476 0x18, 5, 0, 0,
477 &hs_hclk_rate.clk.hw);
478
479 K230_CLK_GATE_FORMAT(hs_ssi0_axi_gate,
480 K230_HS_SSI0_AXI_GATE,
481 0x18, 27, 0, 0,
482 &pll0_div4.hw);
483
484 K230_CLK_RATE_FORMAT(hs_ssi0_axi_rate,
485 K230_HS_SSI0_AXI_RATE,
486 1, 1, 0, 0,
487 1, 8, 9, 0x7,
488 0x20, 31, div, 0x0,
489 false, 0,
490 &hs_ssi0_axi_gate.clk.hw);
491
492 K230_CLK_GATE_FORMAT(hs_ssi1_gate,
493 K230_HS_SSI1_GATE,
494 0x18, 25, 0, 0,
495 &pll0_div4.hw);
496
497 K230_CLK_RATE_FORMAT(hs_ssi1_rate,
498 K230_HS_SSI1_RATE,
499 1, 1, 0, 0,
500 1, 8, 3, 0x7,
501 0x20, 31, div, 0x0,
502 false, 0,
503 &hs_ssi1_gate.clk.hw);
504
505 K230_CLK_GATE_FORMAT(hs_ssi2_gate,
506 K230_HS_SSI2_GATE,
507 0x18, 26, 0, 0,
508 &pll0_div4.hw);
509
510 K230_CLK_RATE_FORMAT(hs_ssi2_rate,
511 K230_HS_SSI2_RATE,
512 1, 1, 0, 0,
513 1, 8, 6, 0x7,
514 0x20, 31, div, 0x0,
515 false, 0,
516 &hs_ssi2_gate.clk.hw);
517
518 K230_CLK_GATE_FORMAT(hs_qspi_axi_src_gate,
519 K230_HS_QSPI_AXI_SRC_GATE,
520 0x18, 28, 0, 0,
521 &pll0_div4.hw);
522
523 K230_CLK_RATE_FORMAT(hs_qspi_axi_src_rate,
524 K230_HS_QSPI_AXI_SRC_RATE,
525 1, 1, 0, 0,
526 1, 8, 12, 0x7,
527 0x20, 31, div, 0x0,
528 false, 0,
529 &hs_qspi_axi_src_gate.clk.hw);
530
531 K230_CLK_GATE_FORMAT(hs_ssi1_axi_gate,
532 K230_HS_SSI1_AXI_GATE,
533 0x18, 29, 0, 0,
534 &hs_qspi_axi_src_rate.clk.hw);
535
536 K230_CLK_GATE_FORMAT(hs_ssi2_axi_gate,
537 K230_HS_SSI2_AXI_GATE,
538 0x18, 30, 0, 0,
539 &hs_qspi_axi_src_rate.clk.hw);
540
541 K230_CLK_GATE_FORMAT(hs_sd_card_src_gate,
542 K230_HS_SD_CARD_SRC_GATE,
543 0x18, 11, 0, 0,
544 &pll0_div4.hw);
545
546 K230_CLK_RATE_FORMAT(hs_sd_card_src_rate,
547 K230_HS_SD_CARD_SRC_RATE,
548 1, 1, 0, 0,
549 2, 8, 12, 0x7,
550 0x1C, 31, div, 0x0,
551 false, 0,
552 &hs_sd_card_src_gate.clk.hw);
553
554 K230_CLK_GATE_FORMAT(hs_sd0_card_gate,
555 K230_HS_SD0_CARD_GATE,
556 0x18, 15, 0, 0,
557 &hs_sd_card_src_rate.clk.hw);
558
559 K230_CLK_GATE_FORMAT(hs_sd1_card_gate,
560 K230_HS_SD1_CARD_GATE,
561 0x18, 19, 0, 0,
562 &hs_sd_card_src_rate.clk.hw);
563
564 K230_CLK_GATE_FORMAT(hs_sd_axi_src_gate,
565 K230_HS_SD_AXI_SRC_GATE,
566 0x18, 9, 0, 0,
567 &pll2_div4.hw);
568
569 K230_CLK_RATE_FORMAT(hs_sd_axi_src_rate,
570 K230_HS_SD_AXI_SRC_RATE,
571 1, 1, 0, 0,
572 1, 8, 6, 0x7,
573 0x1C, 31, div, 0x0,
574 false, 0,
575 &hs_sd_axi_src_gate.clk.hw);
576
577 K230_CLK_GATE_FORMAT(hs_sd0_axi_gate,
578 K230_HS_SD0_AXI_GATE,
579 0x18, 13, 0, 0,
580 &hs_sd_axi_src_rate.clk.hw);
581
582 K230_CLK_GATE_FORMAT(hs_sd1_axi_gate,
583 K230_HS_SD1_AXI_GATE,
584 0x18, 17, 0, 0,
585 &hs_sd_axi_src_rate.clk.hw);
586
587 K230_CLK_GATE_FORMAT(hs_sd0_base_gate,
588 K230_HS_SD0_BASE_GATE,
589 0x18, 14, 0, 0,
590 &hs_sd_axi_src_rate.clk.hw);
591
592 K230_CLK_GATE_FORMAT(hs_sd1_base_gate,
593 K230_HS_SD1_BASE_GATE,
594 0x18, 18, 0, 0,
595 &hs_sd_axi_src_rate.clk.hw);
596
597 static const struct clk_parent_data k230_hs_ssi0_mux_pdata[] = {
598 { .hw = &pll0_div2.hw, },
599 { .hw = &pll2_div4.hw, },
600 };
601
602 K230_CLK_MUX_FORMAT(hs_ssi0_mux,
603 K230_HS_SSI0_MUX,
604 0x20, 18, 0x1,
605 0, 0,
606 k230_hs_ssi0_mux_pdata);
607
608 K230_CLK_GATE_FORMAT(hs_ssi0_gate,
609 K230_HS_SSI0_GATE,
610 0x18, 24, CLK_IGNORE_UNUSED, 0,
611 &hs_ssi0_mux.clk.hw);
612
613 K230_CLK_RATE_FORMAT(hs_usb_ref_50m_rate,
614 K230_HS_USB_REF_50M_RATE,
615 1, 1, 0, 0,
616 1, 8, 15, 0x7,
617 0x20, 31, div, 0x0,
618 false, 0,
619 &pll0_div16.hw);
620
621 K230_CLK_GATE_FORMAT_PNAME(hs_sd_timer_src_gate,
622 K230_HS_SD_TIMER_SRC_GATE,
623 0x18, 12, 0, 0,
624 "osc24m");
625
626 K230_CLK_RATE_FORMAT(hs_sd_timer_src_rate,
627 K230_HS_SD_TIMER_SRC_RATE,
628 1, 1, 0, 0,
629 24, 32, 15, 0x1F,
630 0x1C, 31, div, 0x0,
631 false, 0,
632 &hs_sd_timer_src_gate.clk.hw);
633
634 K230_CLK_GATE_FORMAT(hs_sd0_timer_gate,
635 K230_HS_SD0_TIMER_GATE,
636 0x18, 16, 0, 0,
637 &hs_sd_timer_src_rate.clk.hw);
638
639 K230_CLK_GATE_FORMAT(hs_sd1_timer_gate,
640 K230_HS_SD1_TIMER_GATE,
641 0x18, 20, 0, 0,
642 &hs_sd_timer_src_rate.clk.hw);
643
644 static const struct clk_parent_data k230_hs_usb_ref_mux_pdata[] = {
645 { .fw_name = "osc24m", },
646 { .hw = &hs_usb_ref_50m_rate.clk.hw, },
647 };
648
649 K230_CLK_MUX_FORMAT(hs_usb_ref_mux,
650 K230_HS_USB_REF_MUX,
651 0x18, 23, 0x1,
652 0, 0,
653 k230_hs_usb_ref_mux_pdata);
654
655 K230_CLK_GATE_FORMAT(hs_usb0_ref_gate,
656 K230_HS_USB0_REF_GATE,
657 0x18, 21, CLK_IGNORE_UNUSED, 0,
658 &hs_usb_ref_mux.clk.hw);
659
660 K230_CLK_GATE_FORMAT(hs_usb1_ref_gate,
661 K230_HS_USB1_REF_GATE,
662 0x18, 22, CLK_IGNORE_UNUSED, 0,
663 &hs_usb_ref_mux.clk.hw);
664
665 K230_CLK_GATE_FORMAT(ls_apb_src_gate,
666 K230_LS_APB_SRC_GATE,
667 0x24, 0, CLK_IS_CRITICAL, 0,
668 &pll0_div4.hw);
669
670 K230_CLK_RATE_FORMAT(ls_apb_src_rate,
671 K230_LS_APB_SRC_RATE,
672 1, 1, 0, 0,
673 1, 8, 0, 0x7,
674 0x30, 31, div, 0x0,
675 false, 0,
676 &ls_apb_src_gate.clk.hw);
677
678 K230_CLK_GATE_FORMAT(ls_uart0_apb_gate,
679 K230_LS_UART0_APB_GATE,
680 0x24, 1, CLK_IS_CRITICAL, 0,
681 &ls_apb_src_rate.clk.hw);
682
683 K230_CLK_GATE_FORMAT(ls_uart1_apb_gate,
684 K230_LS_UART1_APB_GATE,
685 0x24, 2, CLK_IS_CRITICAL, 0,
686 &ls_apb_src_rate.clk.hw);
687
688 K230_CLK_GATE_FORMAT(ls_uart2_apb_gate,
689 K230_LS_UART2_APB_GATE,
690 0x24, 3, CLK_IS_CRITICAL, 0,
691 &ls_apb_src_rate.clk.hw);
692
693 K230_CLK_GATE_FORMAT(ls_uart3_apb_gate,
694 K230_LS_UART3_APB_GATE,
695 0x24, 4, CLK_IS_CRITICAL, 0,
696 &ls_apb_src_rate.clk.hw);
697
698 K230_CLK_GATE_FORMAT(ls_uart4_apb_gate,
699 K230_LS_UART4_APB_GATE,
700 0x24, 5, CLK_IS_CRITICAL, 0,
701 &ls_apb_src_rate.clk.hw);
702
703 K230_CLK_GATE_FORMAT(ls_i2c0_apb_gate,
704 K230_LS_I2C0_APB_GATE,
705 0x24, 6, 0, 0,
706 &ls_apb_src_rate.clk.hw);
707
708 K230_CLK_GATE_FORMAT(ls_i2c1_apb_gate,
709 K230_LS_I2C1_APB_GATE,
710 0x24, 7, 0, 0,
711 &ls_apb_src_rate.clk.hw);
712
713 K230_CLK_GATE_FORMAT(ls_i2c2_apb_gate,
714 K230_LS_I2C2_APB_GATE,
715 0x24, 8, 0, 0,
716 &ls_apb_src_rate.clk.hw);
717
718 K230_CLK_GATE_FORMAT(ls_i2c3_apb_gate,
719 K230_LS_I2C3_APB_GATE,
720 0x24, 9, 0, 0,
721 &ls_apb_src_rate.clk.hw);
722
723 K230_CLK_GATE_FORMAT(ls_i2c4_apb_gate,
724 K230_LS_I2C4_APB_GATE,
725 0x24, 10, 0, 0,
726 &ls_apb_src_rate.clk.hw);
727
728 K230_CLK_GATE_FORMAT(ls_gpio_apb_gate,
729 K230_LS_GPIO_APB_GATE,
730 0x24, 11, 0, 0,
731 &ls_apb_src_rate.clk.hw);
732
733 K230_CLK_GATE_FORMAT(ls_pwm_apb_gate,
734 K230_LS_PWM_APB_GATE,
735 0x24, 12, 0, 0,
736 &ls_apb_src_rate.clk.hw);
737
738 K230_CLK_GATE_FORMAT(ls_jamlink0_apb_gate,
739 K230_LS_JAMLINK0_APB_GATE,
740 0x28, 4, 0, 0,
741 &ls_apb_src_rate.clk.hw);
742
743 K230_CLK_GATE_FORMAT(ls_jamlink1_apb_gate,
744 K230_LS_JAMLINK1_APB_GATE,
745 0x28, 5, 0, 0,
746 &ls_apb_src_rate.clk.hw);
747
748 K230_CLK_GATE_FORMAT(ls_jamlink2_apb_gate,
749 K230_LS_JAMLINK2_APB_GATE,
750 0x28, 6, 0, 0,
751 &ls_apb_src_rate.clk.hw);
752
753 K230_CLK_GATE_FORMAT(ls_jamlink3_apb_gate,
754 K230_LS_JAMLINK3_APB_GATE,
755 0x28, 7, 0, 0,
756 &ls_apb_src_rate.clk.hw);
757
758 K230_CLK_GATE_FORMAT(ls_audio_apb_gate,
759 K230_LS_AUDIO_APB_GATE,
760 0x24, 13, 0, 0,
761 &ls_apb_src_rate.clk.hw);
762
763 K230_CLK_GATE_FORMAT(ls_adc_apb_gate,
764 K230_LS_ADC_APB_GATE,
765 0x24, 15, 0, 0,
766 &ls_apb_src_rate.clk.hw);
767
768 K230_CLK_GATE_FORMAT(ls_codec_apb_gate,
769 K230_LS_CODEC_APB_GATE,
770 0x24, 14, 0, 0,
771 &ls_apb_src_rate.clk.hw);
772
773 K230_CLK_GATE_FORMAT(ls_i2c0_gate,
774 K230_LS_I2C0_GATE,
775 0x24, 21, 0, 0,
776 &pll0_div4.hw);
777
778 K230_CLK_RATE_FORMAT(ls_i2c0_rate,
779 K230_LS_I2C0_RATE,
780 1, 1, 0, 0,
781 1, 8, 15, 0x7,
782 0x2C, 31, div, 0x0,
783 false, 0,
784 &ls_i2c0_gate.clk.hw);
785
786 K230_CLK_GATE_FORMAT(ls_i2c1_gate,
787 K230_LS_I2C1_GATE,
788 0x24, 22, 0, 0,
789 &pll0_div4.hw);
790
791 K230_CLK_RATE_FORMAT(ls_i2c1_rate,
792 K230_LS_I2C1_RATE,
793 1, 1, 0, 0,
794 1, 8, 18, 0x7,
795 0x2C, 31, div, 0x0,
796 false, 0,
797 &ls_i2c1_gate.clk.hw);
798
799 K230_CLK_GATE_FORMAT(ls_i2c2_gate,
800 K230_LS_I2C2_GATE,
801 0x24, 23, 0, 0,
802 &pll0_div4.hw);
803
804 K230_CLK_RATE_FORMAT(ls_i2c2_rate,
805 K230_LS_I2C2_RATE,
806 1, 1, 0, 0,
807 1, 8, 21, 0x7,
808 0x2C, 31, div, 0x0,
809 false, 0,
810 &ls_i2c2_gate.clk.hw);
811
812 K230_CLK_GATE_FORMAT(ls_i2c3_gate,
813 K230_LS_I2C3_GATE,
814 0x24, 24, 0, 0,
815 &pll0_div4.hw);
816
817 K230_CLK_RATE_FORMAT(ls_i2c3_rate,
818 K230_LS_I2C3_RATE,
819 1, 1, 0, 0,
820 1, 8, 24, 0x7,
821 0x2C, 31, div, 0x0,
822 false, 0,
823 &ls_i2c3_gate.clk.hw);
824
825 K230_CLK_GATE_FORMAT(ls_i2c4_gate,
826 K230_LS_I2C4_GATE,
827 0x24, 25, 0, 0,
828 &pll0_div4.hw);
829
830 K230_CLK_RATE_FORMAT(ls_i2c4_rate,
831 K230_LS_I2C4_RATE,
832 1, 1, 0, 0,
833 1, 8, 27, 0x7,
834 0x2C, 31, div, 0x0,
835 false, 0,
836 &ls_i2c4_gate.clk.hw);
837
838 K230_CLK_GATE_FORMAT(ls_codec_adc_gate,
839 K230_LS_CODEC_ADC_GATE,
840 0x24, 29, 0, 0,
841 &pll0_div4.hw);
842
843 K230_CLK_RATE_FORMAT(ls_codec_adc_rate,
844 K230_LS_CODEC_ADC_RATE,
845 0x10, 0x1B9, 14, 0x1FFF,
846 0xC35, 0x3D09, 0, 0x3FFF,
847 0x38, 31, mul_div, 0x38,
848 false, 0,
849 &ls_codec_adc_gate.clk.hw);
850
851 K230_CLK_GATE_FORMAT(ls_codec_dac_gate,
852 K230_LS_CODEC_DAC_GATE,
853 0x24, 30, 0, 0,
854 &pll0_div4.hw);
855
856 K230_CLK_RATE_FORMAT(ls_codec_dac_rate,
857 K230_LS_CODEC_DAC_RATE,
858 0x10, 0x1B9, 14, 0x1FFF,
859 0xC35, 0x3D09, 0, 0x3FFF,
860 0x3C, 31, mul_div, 0x3C,
861 false, 0,
862 &ls_codec_dac_gate.clk.hw);
863
864 K230_CLK_GATE_FORMAT(ls_audio_dev_gate,
865 K230_LS_AUDIO_DEV_GATE,
866 0x24, 28, 0, 0,
867 &pll0_div4.hw);
868
869 K230_CLK_RATE_FORMAT(ls_audio_dev_rate,
870 K230_LS_AUDIO_DEV_RATE,
871 0x4, 0x1B9, 16, 0x7FFF,
872 0xC35, 0xF424, 0, 0xFFFF,
873 0x34, 31, mul_div, 0x34,
874 false, 0,
875 &ls_audio_dev_gate.clk.hw);
876
877 K230_CLK_GATE_FORMAT(ls_pdm_gate,
878 K230_LS_PDM_GATE,
879 0x24, 31, 0, 0,
880 &pll0_div4.hw);
881
882 K230_CLK_RATE_FORMAT(ls_pdm_rate,
883 K230_LS_PDM_RATE,
884 0x2, 0x1B9, 0, 0xFFFF,
885 0xC35, 0x1E848, 0, 0x1FFFF,
886 0x40, 0, mul_div, 0x44,
887 false, 0,
888 &ls_pdm_gate.clk.hw);
889
890 K230_CLK_GATE_FORMAT(ls_adc_gate,
891 K230_LS_ADC_GATE,
892 0x24, 26, 0, 0,
893 &pll0_div4.hw);
894
895 K230_CLK_RATE_FORMAT(ls_adc_rate,
896 K230_LS_ADC_RATE,
897 1, 1, 0, 0,
898 1, 1024, 3, 0x3FF,
899 0x30, 31, div, 0x0,
900 false, 0,
901 &ls_adc_gate.clk.hw);
902
903 K230_CLK_GATE_FORMAT(ls_uart0_gate,
904 K230_LS_UART0_GATE,
905 0x24, 16, CLK_IS_CRITICAL, 0,
906 &pll0_div16.hw);
907
908 K230_CLK_RATE_FORMAT(ls_uart0_rate,
909 K230_LS_UART0_RATE,
910 1, 1, 0, 0,
911 1, 8, 0, 0x7,
912 0x2C, 31, div, 0x0,
913 false, 0,
914 &ls_uart0_gate.clk.hw);
915
916 K230_CLK_GATE_FORMAT(ls_uart1_gate,
917 K230_LS_UART1_GATE,
918 0x24, 17, CLK_IS_CRITICAL, 0,
919 &pll0_div16.hw);
920
921 K230_CLK_RATE_FORMAT(ls_uart1_rate,
922 K230_LS_UART1_RATE,
923 1, 1, 0, 0,
924 1, 8, 3, 0x7,
925 0x2C, 31, div, 0x0,
926 false, 0,
927 &ls_uart1_gate.clk.hw);
928
929 K230_CLK_GATE_FORMAT(ls_uart2_gate,
930 K230_LS_UART2_GATE,
931 0x24, 18, CLK_IS_CRITICAL, 0,
932 &pll0_div16.hw);
933
934 K230_CLK_RATE_FORMAT(ls_uart2_rate,
935 K230_LS_UART2_RATE,
936 1, 1, 0, 0,
937 1, 8, 6, 0x7,
938 0x2C, 31, div, 0x0,
939 false, 0,
940 &ls_uart2_gate.clk.hw);
941
942 K230_CLK_GATE_FORMAT(ls_uart3_gate,
943 K230_LS_UART3_GATE,
944 0x24, 19, CLK_IS_CRITICAL, 0,
945 &pll0_div16.hw);
946
947 K230_CLK_RATE_FORMAT(ls_uart3_rate,
948 K230_LS_UART3_RATE,
949 1, 1, 0, 0,
950 1, 8, 9, 0x7,
951 0x2C, 31, div, 0x0,
952 false, 0,
953 &ls_uart3_gate.clk.hw);
954
955 K230_CLK_GATE_FORMAT(ls_uart4_gate,
956 K230_LS_UART4_GATE,
957 0x24, 20, CLK_IS_CRITICAL, 0,
958 &pll0_div16.hw);
959
960 K230_CLK_RATE_FORMAT(ls_uart4_rate,
961 K230_LS_UART4_RATE,
962 1, 1, 0, 0,
963 1, 8, 12, 0x7,
964 0x2C, 31, div, 0x0,
965 false, 0,
966 &ls_uart4_gate.clk.hw);
967
968 K230_CLK_RATE_FORMAT(ls_jamlinkco_src_rate,
969 K230_LS_JAMLINKCO_SRC_RATE,
970 1, 1, 0, 0,
971 2, 512, 23, 0xFF,
972 0x30, 31, div, 0x0,
973 false, 0,
974 &pll0_div16.hw);
975
976 K230_CLK_GATE_FORMAT(ls_jamlink0co_gate,
977 K230_LS_JAMLINK0CO_GATE,
978 0x28, 0, 0, 0,
979 &ls_jamlinkco_src_rate.clk.hw);
980
981 K230_CLK_GATE_FORMAT(ls_jamlink1co_gate,
982 K230_LS_JAMLINK1CO_GATE,
983 0x28, 1, 0, 0,
984 &ls_jamlinkco_src_rate.clk.hw);
985
986 K230_CLK_GATE_FORMAT(ls_jamlink2co_gate,
987 K230_LS_JAMLINK2CO_GATE,
988 0x28, 2, 0, 0,
989 &ls_jamlinkco_src_rate.clk.hw);
990
991 K230_CLK_GATE_FORMAT(ls_jamlink3co_gate,
992 K230_LS_JAMLINK3CO_GATE,
993 0x28, 3, 0, 0,
994 &ls_jamlinkco_src_rate.clk.hw);
995
996 K230_CLK_GATE_FORMAT_PNAME(ls_gpio_debounce_gate,
997 K230_LS_GPIO_DEBOUNCE_GATE,
998 0x24, 27, 0, 0,
999 "osc24m");
1000
1001 K230_CLK_RATE_FORMAT(ls_gpio_debounce_rate,
1002 K230_LS_GPIO_DEBOUNCE_RATE,
1003 1, 1, 0, 0,
1004 1, 1024, 13, 0x3FF,
1005 0x30, 31, div, 0x0,
1006 false, 0,
1007 &ls_gpio_debounce_gate.clk.hw);
1008
1009 K230_CLK_GATE_FORMAT(sysctl_wdt0_apb_gate,
1010 K230_SYSCTL_WDT0_APB_GATE,
1011 0x50, 1, 0, 0,
1012 &pll0_div16.hw);
1013
1014 K230_CLK_GATE_FORMAT(sysctl_wdt1_apb_gate,
1015 K230_SYSCTL_WDT1_APB_GATE,
1016 0x50, 2, 0, 0,
1017 &pll0_div16.hw);
1018
1019 K230_CLK_GATE_FORMAT(sysctl_timer_apb_gate,
1020 K230_SYSCTL_TIMER_APB_GATE,
1021 0x50, 3, 0, 0,
1022 &pll0_div16.hw);
1023
1024 K230_CLK_GATE_FORMAT(sysctl_iomux_apb_gate,
1025 K230_SYSCTL_IOMUX_APB_GATE,
1026 0x50, 20, 0, 0,
1027 &pll0_div16.hw);
1028
1029 K230_CLK_GATE_FORMAT(sysctl_mailbox_apb_gate,
1030 K230_SYSCTL_MAILBOX_APB_GATE,
1031 0x50, 4, 0, 0,
1032 &pll0_div16.hw);
1033
1034 K230_CLK_GATE_FORMAT(sysctl_hdi_gate,
1035 K230_SYSCTL_HDI_GATE,
1036 0x50, 21, 0, 0,
1037 &pll0_div4.hw);
1038
1039 K230_CLK_RATE_FORMAT(sysctl_hdi_rate,
1040 K230_SYSCTL_HDI_RATE,
1041 1, 1, 0, 0,
1042 1, 8, 28, 0x7,
1043 0x58, 31, div, 0x0,
1044 false, 0,
1045 &sysctl_hdi_gate.clk.hw);
1046
1047 K230_CLK_GATE_FORMAT(sysctl_time_stamp_gate,
1048 K230_SYSCTL_TIME_STAMP_GATE,
1049 0x50, 19, CLK_IS_CRITICAL, 0,
1050 &pll1_div4.hw);
1051
1052 K230_CLK_RATE_FORMAT(sysctl_time_stamp_rate,
1053 K230_SYSCTL_TIME_STAMP_RATE,
1054 1, 1, 0, 0,
1055 1, 32, 15, 0x1F,
1056 0x58, 31, div, 0x0,
1057 false, 0,
1058 &sysctl_time_stamp_gate.clk.hw);
1059
1060 K230_CLK_RATE_FORMAT_PNAME(sysctl_temp_sensor_rate,
1061 K230_SYSCTL_TEMP_SENSOR_RATE,
1062 1, 1, 0, 0,
1063 1, 256, 20, 0xFF,
1064 0x58, 31, div, 0x0,
1065 false, 0,
1066 "osc24m");
1067
1068 K230_CLK_GATE_FORMAT_PNAME(sysctl_wdt0_gate,
1069 K230_SYSCTL_WDT0_GATE,
1070 0x50, 5, 0, 0,
1071 "osc24m");
1072
1073 K230_CLK_RATE_FORMAT(sysctl_wdt0_rate,
1074 K230_SYSCTL_WDT0_RATE,
1075 1, 1, 0, 0,
1076 1, 64, 3, 0x3F,
1077 0x58, 31, div, 0x0,
1078 false, 0,
1079 &sysctl_wdt0_gate.clk.hw);
1080
1081 K230_CLK_GATE_FORMAT_PNAME(sysctl_wdt1_gate,
1082 K230_SYSCTL_WDT1_GATE,
1083 0x50, 6, 0, 0,
1084 "osc24m");
1085
1086 K230_CLK_RATE_FORMAT(sysctl_wdt1_rate,
1087 K230_SYSCTL_WDT1_RATE,
1088 1, 1, 0, 0,
1089 1, 64, 9, 0x3F,
1090 0x58, 31, div, 0x0,
1091 false, 0,
1092 &sysctl_wdt1_gate.clk.hw);
1093
1094 K230_CLK_RATE_FORMAT(timer0_src_rate,
1095 K230_TIMER0_SRC_RATE,
1096 1, 1, 0, 0,
1097 1, 8, 0, 0x7,
1098 0x54, 31, div, 0x0,
1099 false, 0,
1100 &pll0_div16.hw);
1101
1102 K230_CLK_RATE_FORMAT(timer1_src_rate,
1103 K230_TIMER1_SRC_RATE,
1104 1, 1, 0, 0,
1105 1, 8, 3, 0x7,
1106 0x54, 31, div, 0x0,
1107 false, 0,
1108 &pll0_div16.hw);
1109
1110 K230_CLK_RATE_FORMAT(timer2_src_rate,
1111 K230_TIMER2_SRC_RATE,
1112 1, 1, 0, 0,
1113 1, 8, 6, 0x7,
1114 0x54, 31, div, 0x0,
1115 false, 0,
1116 &pll0_div16.hw);
1117
1118 K230_CLK_RATE_FORMAT(timer3_src_rate,
1119 K230_TIMER3_SRC_RATE,
1120 1, 1, 0, 0,
1121 1, 8, 9, 0x7,
1122 0x54, 31, div, 0x0,
1123 false, 0,
1124 &pll0_div16.hw);
1125
1126 K230_CLK_RATE_FORMAT(timer4_src_rate,
1127 K230_TIMER4_SRC_RATE,
1128 1, 1, 0, 0,
1129 1, 8, 12, 0x7,
1130 0x54, 31, div, 0x0,
1131 false, 0,
1132 &pll0_div16.hw);
1133
1134 K230_CLK_RATE_FORMAT(timer5_src_rate,
1135 K230_TIMER5_SRC_RATE,
1136 1, 1, 0, 0,
1137 1, 8, 15, 0x7,
1138 0x54, 31, div, 0x0,
1139 false, 0,
1140 &pll0_div16.hw);
1141
1142 static const struct clk_parent_data k230_timer0_mux_pdata[] = {
1143 { .fw_name = "timer-pulse-in", },
1144 { .hw = &timer0_src_rate.clk.hw, },
1145 };
1146
1147 K230_CLK_MUX_FORMAT(timer0_mux,
1148 K230_TIMER0_MUX,
1149 0x50, 7, 0x1,
1150 0, 0,
1151 k230_timer0_mux_pdata);
1152
1153 K230_CLK_GATE_FORMAT(timer0_gate,
1154 K230_TIMER0_GATE,
1155 0x50, 13, CLK_IGNORE_UNUSED, 0,
1156 &timer0_mux.clk.hw);
1157
1158 static const struct clk_parent_data k230_timer1_mux_pdata[] = {
1159 { .fw_name = "timer-pulse-in", },
1160 { .hw = &timer1_src_rate.clk.hw, },
1161 };
1162
1163 K230_CLK_MUX_FORMAT(timer1_mux,
1164 K230_TIMER1_MUX,
1165 0x50, 8, 0x1,
1166 0, 0,
1167 k230_timer1_mux_pdata);
1168
1169 K230_CLK_GATE_FORMAT(timer1_gate,
1170 K230_TIMER1_GATE,
1171 0x50, 14, CLK_IGNORE_UNUSED, 0,
1172 &timer1_mux.clk.hw);
1173
1174 static const struct clk_parent_data k230_timer2_mux_pdata[] = {
1175 { .fw_name = "timer-pulse-in", },
1176 { .hw = &timer2_src_rate.clk.hw, },
1177 };
1178
1179 K230_CLK_MUX_FORMAT(timer2_mux,
1180 K230_TIMER2_MUX,
1181 0x50, 9, 0x1,
1182 0, 0,
1183 k230_timer2_mux_pdata);
1184
1185 K230_CLK_GATE_FORMAT(timer2_gate,
1186 K230_TIMER2_GATE,
1187 0x50, 15, CLK_IGNORE_UNUSED, 0,
1188 &timer2_mux.clk.hw);
1189
1190 static const struct clk_parent_data k230_timer3_mux_pdata[] = {
1191 { .fw_name = "timer-pulse-in", },
1192 { .hw = &timer3_src_rate.clk.hw, },
1193 };
1194
1195 K230_CLK_MUX_FORMAT(timer3_mux,
1196 K230_TIMER3_MUX,
1197 0x50, 10, 0x1,
1198 0, 0,
1199 k230_timer3_mux_pdata);
1200
1201 K230_CLK_GATE_FORMAT(timer3_gate,
1202 K230_TIMER3_GATE,
1203 0x50, 16, CLK_IGNORE_UNUSED, 0,
1204 &timer3_mux.clk.hw);
1205
1206 static const struct clk_parent_data k230_timer4_mux_pdata[] = {
1207 { .fw_name = "timer-pulse-in", },
1208 { .hw = &timer4_src_rate.clk.hw, },
1209 };
1210
1211 K230_CLK_MUX_FORMAT(timer4_mux,
1212 K230_TIMER4_MUX,
1213 0x50, 11, 0x1,
1214 0, 0,
1215 k230_timer4_mux_pdata);
1216
1217 K230_CLK_GATE_FORMAT(timer4_gate,
1218 K230_TIMER4_GATE,
1219 0x50, 17, CLK_IGNORE_UNUSED, 0,
1220 &timer4_mux.clk.hw);
1221
1222 static const struct clk_parent_data k230_timer5_mux_pdata[] = {
1223 { .fw_name = "timer-pulse-in", },
1224 { .hw = &timer5_src_rate.clk.hw, },
1225 };
1226
1227 K230_CLK_MUX_FORMAT(timer5_mux,
1228 K230_TIMER5_MUX,
1229 0x50, 12, 0x1,
1230 0, 0,
1231 k230_timer5_mux_pdata);
1232
1233 K230_CLK_GATE_FORMAT(timer5_gate,
1234 K230_TIMER5_GATE,
1235 0x50, 18, CLK_IGNORE_UNUSED, 0,
1236 &timer5_mux.clk.hw);
1237
1238 K230_CLK_GATE_FORMAT(shrm_apb_gate,
1239 K230_SHRM_APB_GATE,
1240 0x5C, 0, 0, 0,
1241 &pll0_div4.hw);
1242
1243 K230_CLK_RATE_FORMAT(shrm_apb_rate,
1244 K230_SHRM_APB_RATE,
1245 1, 1, 0, 0,
1246 1, 8, 18, 0x7,
1247 0x5C, 31, div, 0x0,
1248 false, 0,
1249 &shrm_apb_gate.clk.hw);
1250
1251 static const struct clk_parent_data k230_shrm_sram_mux_pdata[] = {
1252 { .hw = &pll3_div2.hw, },
1253 { .hw = &pll0_div2.hw, },
1254 };
1255
1256 K230_CLK_MUX_FORMAT(shrm_sram_mux,
1257 K230_SHRM_SRAM_MUX,
1258 0x50, 14, 0x1,
1259 0, 0,
1260 k230_shrm_sram_mux_pdata);
1261
1262 K230_CLK_GATE_FORMAT(shrm_sram_gate,
1263 K230_SHRM_SRAM_GATE,
1264 0x5c, 10, CLK_IGNORE_UNUSED, 0,
1265 &shrm_sram_mux.clk.hw);
1266
1267 K230_CLK_FIXED_FACTOR_FORMAT(shrm_sram_div2,
1268 1, 2, 0,
1269 &shrm_sram_gate.clk.hw);
1270
1271 K230_CLK_GATE_FORMAT(shrm_axi_slave_gate,
1272 K230_SHRM_AXI_SLAVE_GATE,
1273 0x5C, 11, CLK_IGNORE_UNUSED, 0,
1274 &shrm_sram_div2.hw);
1275
1276 K230_CLK_GATE_FORMAT(shrm_axi_gate,
1277 K230_SHRM_AXI_GATE,
1278 0x5C, 12, 0, 0,
1279 &pll0_div4.hw);
1280
1281 K230_CLK_GATE_FORMAT(shrm_nonai2d_axi_gate,
1282 K230_SHRM_NONAI2D_AXI_GATE,
1283 0x5C, 9, 0, 0,
1284 &shrm_axi_gate.clk.hw);
1285
1286 K230_CLK_GATE_FORMAT(shrm_decompress_axi_gate,
1287 K230_SHRM_DECOMPRESS_AXI_GATE,
1288 0x5C, 7, CLK_IGNORE_UNUSED, 0,
1289 &shrm_sram_gate.clk.hw);
1290
1291 K230_CLK_GATE_FORMAT(shrm_sdma_axi_gate,
1292 K230_SHRM_SDMA_AXI_GATE,
1293 0x5C, 5, 0, 0,
1294 &shrm_axi_gate.clk.hw);
1295
1296 K230_CLK_GATE_FORMAT(shrm_pdma_axi_gate,
1297 K230_SHRM_PDMA_AXI_GATE,
1298 0x5C, 3, 0, 0,
1299 &shrm_axi_gate.clk.hw);
1300
1301 static const struct clk_parent_data k230_ddrc_src_mux_pdata[] = {
1302 { .hw = &pll0_div2.hw, },
1303 { .hw = &pll0_div3.hw, },
1304 { .hw = &pll2_div4.hw, },
1305 };
1306
1307 K230_CLK_MUX_FORMAT(ddrc_src_mux,
1308 K230_DDRC_SRC_MUX,
1309 0x60, 0, 0x3,
1310 0, 0,
1311 k230_ddrc_src_mux_pdata);
1312
1313 K230_CLK_GATE_FORMAT(ddrc_src_gate,
1314 K230_DDRC_SRC_GATE,
1315 0x60, 2, CLK_IGNORE_UNUSED, 0,
1316 &ddrc_src_mux.clk.hw);
1317
1318 K230_CLK_RATE_FORMAT(ddrc_src_rate,
1319 K230_DDRC_SRC_RATE,
1320 1, 1, 0, 0,
1321 1, 16, 10, 0xF,
1322 0x60, 31, div, 0x0,
1323 false, 0,
1324 &ddrc_src_gate.clk.hw);
1325
1326 K230_CLK_GATE_FORMAT(ddrc_bypass_gate,
1327 K230_DDRC_BYPASS_GATE,
1328 0x60, 8, 0, 0,
1329 &pll2_div4.hw);
1330
1331 K230_CLK_GATE_FORMAT(ddrc_apb_gate,
1332 K230_DDRC_APB_GATE,
1333 0x60, 9, 0, 0,
1334 &pll0_div4.hw);
1335
1336 K230_CLK_RATE_FORMAT(ddrc_apb_rate,
1337 K230_DDRC_APB_RATE,
1338 1, 1, 0, 0,
1339 1, 16, 14, 0xF,
1340 0x60, 31, div, 0x0,
1341 false, 0,
1342 &ddrc_apb_gate.clk.hw);
1343
1344 K230_CLK_GATE_FORMAT(display_ahb_gate,
1345 K230_DISPLAY_AHB_GATE,
1346 0x74, 0, 0, 0,
1347 &pll0_div4.hw);
1348
1349 K230_CLK_RATE_FORMAT(display_ahb_rate,
1350 K230_DISPLAY_AHB_RATE,
1351 1, 1, 0, 0,
1352 1, 8, 0, 0x7,
1353 0x78, 31, div, 0x0,
1354 false, 0,
1355 &display_ahb_gate.clk.hw);
1356
1357 K230_CLK_GATE_FORMAT(display_axi_gate,
1358 K230_DISPLAY_AXI_GATE,
1359 0x74, 1, 0, 0,
1360 &pll0_div4.hw);
1361
1362 K230_CLK_RATE_FORMAT(display_clkext_rate,
1363 K230_DISPLAY_CLKEXT_RATE,
1364 1, 1, 0, 0,
1365 1, 16, 16, 0xF,
1366 0x78, 31, div, 0x0,
1367 false, 0,
1368 &pll0_div3.hw);
1369
1370 K230_CLK_GATE_FORMAT(display_gpu_gate,
1371 K230_DISPLAY_GPU_GATE,
1372 0x74, 6, 0, 0,
1373 &pll0_div3.hw);
1374
1375 K230_CLK_RATE_FORMAT(display_gpu_rate,
1376 K230_DISPLAY_GPU_RATE,
1377 1, 1, 0, 0,
1378 1, 16, 20, 0xF,
1379 0x78, 31, div, 0x0,
1380 false, 0,
1381 &display_gpu_gate.clk.hw);
1382
1383 K230_CLK_GATE_FORMAT(display_dpip_gate,
1384 K230_DISPLAY_DPIP_GATE,
1385 0x74, 2, 0, 0,
1386 &pll1_div4.hw);
1387
1388 K230_CLK_RATE_FORMAT(display_dpip_rate,
1389 K230_DISPLAY_DPIP_RATE,
1390 1, 1, 0, 0,
1391 1, 256, 3, 0xFF,
1392 0x78, 31, div, 0x0,
1393 false, 0,
1394 &display_dpip_gate.clk.hw);
1395
1396 K230_CLK_GATE_FORMAT(display_cfg_gate,
1397 K230_DISPLAY_CFG_GATE,
1398 0x74, 4, 0, 0,
1399 &pll1_div4.hw);
1400
1401 K230_CLK_RATE_FORMAT(display_cfg_rate,
1402 K230_DISPLAY_CFG_RATE,
1403 1, 1, 0, 0,
1404 1, 32, 11, 0x1F,
1405 0x78, 31, div, 0x0,
1406 false, 0,
1407 &display_cfg_gate.clk.hw);
1408
1409 K230_CLK_GATE_FORMAT_PNAME(display_ref_gate,
1410 K230_DISPLAY_REF_GATE,
1411 0x74, 3, 0, 0,
1412 "osc24m");
1413
1414 K230_CLK_GATE_FORMAT(vpu_src_gate,
1415 K230_VPU_SRC_GATE,
1416 0xC, 0, 0, 0,
1417 &pll0_div2.hw);
1418
1419 K230_CLK_RATE_FORMAT(vpu_src_rate,
1420 K230_VPU_SRC_RATE,
1421 1, 16, 1, 0xF,
1422 16, 16, 0, 0,
1423 0x0, 31, mul, 0xC,
1424 false, 0,
1425 &vpu_src_gate.clk.hw);
1426
1427 K230_CLK_RATE_FORMAT(vpu_axi_src_rate,
1428 K230_VPU_AXI_SRC_RATE,
1429 1, 1, 0, 0,
1430 1, 16, 6, 0xF,
1431 0xC, 31, div, 0x0,
1432 false, 0,
1433 &vpu_src_rate.clk.hw);
1434
1435 K230_CLK_GATE_FORMAT(vpu_axi_gate,
1436 K230_VPU_AXI_GATE,
1437 0xC, 5, 0, 0,
1438 &vpu_axi_src_rate.clk.hw);
1439
1440 K230_CLK_GATE_FORMAT(vpu_ddrcp2_gate,
1441 K230_VPU_DDRCP2_GATE,
1442 0x60, 5, 0, 0,
1443 &vpu_axi_src_rate.clk.hw);
1444
1445 K230_CLK_GATE_FORMAT(vpu_cfg_gate,
1446 K230_VPU_CFG_GATE,
1447 0xC, 10, 0, 0,
1448 &pll0_div4.hw);
1449
1450 K230_CLK_RATE_FORMAT(vpu_cfg_rate,
1451 K230_VPU_CFG_RATE,
1452 1, 1, 0, 0,
1453 1, 16, 11, 0xF,
1454 0xC, 31, div, 0x0,
1455 false, 0,
1456 &vpu_cfg_gate.clk.hw);
1457
1458 K230_CLK_GATE_FORMAT(sec_apb_gate,
1459 K230_SEC_APB_GATE,
1460 0x80, 0, 0, 0,
1461 &pll1_div4.hw);
1462
1463 K230_CLK_RATE_FORMAT(sec_apb_rate,
1464 K230_SEC_APB_RATE,
1465 1, 1, 0, 0,
1466 1, 8, 1, 0x7,
1467 0x80, 31, div, 0x0,
1468 false, 0,
1469 &sec_apb_gate.clk.hw);
1470
1471 K230_CLK_GATE_FORMAT(sec_fix_gate,
1472 K230_SEC_FIX_GATE,
1473 0x80, 5, 0, 0,
1474 &pll1_div4.hw);
1475
1476 K230_CLK_RATE_FORMAT(sec_fix_rate,
1477 K230_SEC_FIX_RATE,
1478 1, 1, 0, 0,
1479 1, 32, 6, 0x1F,
1480 0x80, 31, div, 0x0,
1481 false, 0,
1482 &sec_fix_gate.clk.hw);
1483
1484 K230_CLK_GATE_FORMAT(sec_axi_gate,
1485 K230_SEC_AXI_GATE,
1486 0x80, 4, 0, 0,
1487 &pll1_div4.hw);
1488
1489 K230_CLK_RATE_FORMAT(sec_axi_rate,
1490 K230_SEC_AXI_RATE,
1491 1, 1, 0, 0,
1492 1, 8, 11, 0x3,
1493 0x80, 31, div, 0,
1494 false, 0,
1495 &sec_axi_gate.clk.hw);
1496
1497 K230_CLK_GATE_FORMAT(usb_480m_gate,
1498 K230_USB_480M_GATE,
1499 0x100, 0, 0, 0,
1500 &pll1.hw);
1501
1502 K230_CLK_RATE_FORMAT(usb_480m_rate,
1503 K230_USB_480M_RATE,
1504 1, 1, 0, 0,
1505 1, 8, 1, 0x7,
1506 0x100, 31, div, 0,
1507 false, 0,
1508 &usb_480m_gate.clk.hw);
1509
1510 K230_CLK_GATE_FORMAT(usb_100m_gate,
1511 K230_USB_100M_GATE,
1512 0x100, 0, 0, 0,
1513 &pll0_div4.hw);
1514
1515 K230_CLK_RATE_FORMAT(usb_100m_rate,
1516 K230_USB_100M_RATE,
1517 1, 1, 0, 0,
1518 1, 8, 4, 0x7,
1519 0x100, 31, div, 0,
1520 false, 0,
1521 &usb_100m_gate.clk.hw);
1522
1523 K230_CLK_GATE_FORMAT(dphy_dft_gate,
1524 K230_DPHY_DFT_GATE,
1525 0x100, 0, 0, 0,
1526 &pll0.hw);
1527
1528 K230_CLK_RATE_FORMAT(dphy_dft_rate,
1529 K230_DPHY_DFT_RATE,
1530 1, 1, 0, 0,
1531 1, 16, 1, 0xF,
1532 0x104, 31, div, 0,
1533 false, 0,
1534 &dphy_dft_gate.clk.hw);
1535
1536 K230_CLK_GATE_FORMAT(spi2axi_gate,
1537 K230_SPI2AXI_GATE,
1538 0x108, 0, 0, 0,
1539 &pll0_div4.hw);
1540
1541 K230_CLK_RATE_FORMAT(spi2axi_rate,
1542 K230_SPI2AXI_RATE,
1543 1, 1, 0, 0,
1544 1, 8, 1, 0x7,
1545 0x108, 31, div, 0x0,
1546 false, 0,
1547 &spi2axi_gate.clk.hw);
1548
1549 static const struct clk_parent_data k230_ai_src_mux_pdata[] = {
1550 { .hw = &pll0_div2.hw, },
1551 { .hw = &pll3_div2.hw, },
1552 };
1553
1554 K230_CLK_MUX_FORMAT(ai_src_mux,
1555 K230_AI_SRC_MUX,
1556 0x8, 2, 0x1,
1557 0, 0,
1558 k230_ai_src_mux_pdata);
1559
1560 K230_CLK_GATE_FORMAT(ai_src_gate,
1561 K230_AI_SRC_GATE,
1562 0x8, 0, CLK_IGNORE_UNUSED, 0,
1563 &ai_src_mux.clk.hw);
1564
1565 K230_CLK_RATE_FORMAT(ai_src_rate,
1566 K230_AI_SRC_RATE,
1567 1, 1, 0, 0,
1568 1, 8, 3, 0x7,
1569 0x8, 31, div, 0x0,
1570 false, 0,
1571 &ai_src_gate.clk.hw);
1572
1573 K230_CLK_GATE_FORMAT(ai_axi_gate,
1574 K230_AI_AXI_GATE,
1575 0x8, 10, 0, 0,
1576 &pll0_div4.hw);
1577
1578 static const struct clk_parent_data k230_camera0_mux_pdata[] = {
1579 { .hw = &pll1_div3.hw, },
1580 { .hw = &pll1_div4.hw, },
1581 { .hw = &pll0_div4.hw, },
1582 };
1583
1584 K230_CLK_MUX_FORMAT(camera0_mux,
1585 K230_CAMERA0_MUX,
1586 0x6C, 3, 0x3,
1587 0, 0,
1588 k230_camera0_mux_pdata);
1589
1590 K230_CLK_GATE_FORMAT(camera0_gate,
1591 K230_CAMERA0_GATE,
1592 0x6C, 0, CLK_IGNORE_UNUSED, 0,
1593 &camera0_mux.clk.hw);
1594
1595 K230_CLK_RATE_FORMAT(camera0_rate,
1596 K230_CAMERA0_RATE,
1597 1, 1, 0, 0,
1598 1, 32, 5, 0x1f,
1599 0x6C, 31, div, 0x0,
1600 false, 0,
1601 &camera0_gate.clk.hw);
1602
1603 static const struct clk_parent_data k230_camera1_mux_pdata[] = {
1604 { .hw = &pll1_div3.hw, },
1605 { .hw = &pll1_div4.hw, },
1606 { .hw = &pll0_div4.hw, },
1607 };
1608
1609 K230_CLK_MUX_FORMAT(camera1_mux,
1610 K230_CAMERA1_MUX,
1611 0x6C, 10, 0x3,
1612 0, 0,
1613 k230_camera1_mux_pdata);
1614
1615 K230_CLK_GATE_FORMAT(camera1_gate,
1616 K230_CAMERA1_GATE,
1617 0x6C, 1, CLK_IGNORE_UNUSED, 0,
1618 &camera1_mux.clk.hw);
1619
1620 K230_CLK_RATE_FORMAT(camera1_rate,
1621 K230_CAMERA1_RATE,
1622 1, 1, 0, 0,
1623 1, 32, 12, 0x1f,
1624 0x6C, 31, div, 0x0,
1625 false, 0,
1626 &camera1_gate.clk.hw);
1627
1628 static const struct clk_parent_data k230_camera2_mux_pdata[] = {
1629 { .hw = &pll1_div3.hw, },
1630 { .hw = &pll1_div4.hw, },
1631 { .hw = &pll0_div4.hw, },
1632 };
1633
1634 K230_CLK_MUX_FORMAT(camera2_mux,
1635 K230_CAMERA2_MUX,
1636 0x6C, 17, 0x3,
1637 0, 0,
1638 k230_camera2_mux_pdata);
1639
1640 K230_CLK_GATE_FORMAT(camera2_gate,
1641 K230_CAMERA2_GATE,
1642 0x6C, 2, CLK_IGNORE_UNUSED, 0,
1643 &camera2_mux.clk.hw);
1644
1645 K230_CLK_RATE_FORMAT(camera2_rate,
1646 K230_CAMERA2_RATE,
1647 1, 1, 0, 0,
1648 1, 32, 19, 0x1f,
1649 0x6C, 31, div, 0x0,
1650 false, 0,
1651 &camera2_gate.clk.hw);
1652
1653 static struct k230_clk_mux *k230_clk_muxs[] = {
1654 &hs_ssi0_mux,
1655 &hs_usb_ref_mux,
1656 &cpu1_src_mux,
1657 &timer0_mux,
1658 &timer1_mux,
1659 &timer2_mux,
1660 &timer3_mux,
1661 &timer4_mux,
1662 &timer5_mux,
1663 &shrm_sram_mux,
1664 &ddrc_src_mux,
1665 &ai_src_mux,
1666 &camera0_mux,
1667 &camera1_mux,
1668 &camera2_mux,
1669 };
1670
1671 #define K230_CLK_MUX_NUM ARRAY_SIZE(k230_clk_muxs)
1672
1673 static struct k230_clk_gate *k230_clk_gates[] = {
1674 &cpu0_src_gate,
1675 &cpu0_plic_gate,
1676 &cpu0_noc_ddrcp4_gate,
1677 &cpu0_apb_gate,
1678 &cpu1_src_gate,
1679 &cpu1_plic_gate,
1680 &cpu1_apb_gate,
1681 &pmu_apb_gate,
1682 &hs_hclk_high_gate,
1683 &hs_hclk_gate,
1684 &hs_sd0_ahb_gate,
1685 &hs_sd1_ahb_gate,
1686 &hs_ssi1_ahb_gate,
1687 &hs_ssi2_ahb_gate,
1688 &hs_usb0_ahb_gate,
1689 &hs_usb1_ahb_gate,
1690 &hs_ssi0_axi_gate,
1691 &hs_ssi1_gate,
1692 &hs_ssi2_gate,
1693 &hs_qspi_axi_src_gate,
1694 &hs_ssi1_axi_gate,
1695 &hs_ssi2_axi_gate,
1696 &hs_sd_card_src_gate,
1697 &hs_sd0_card_gate,
1698 &hs_sd1_card_gate,
1699 &hs_sd_axi_src_gate,
1700 &hs_sd0_axi_gate,
1701 &hs_sd1_axi_gate,
1702 &hs_sd0_base_gate,
1703 &hs_sd1_base_gate,
1704 &hs_ssi0_gate,
1705 &hs_sd_timer_src_gate,
1706 &hs_sd0_timer_gate,
1707 &hs_sd1_timer_gate,
1708 &hs_usb0_ref_gate,
1709 &hs_usb1_ref_gate,
1710 &ls_apb_src_gate,
1711 &ls_uart0_apb_gate,
1712 &ls_uart1_apb_gate,
1713 &ls_uart2_apb_gate,
1714 &ls_uart3_apb_gate,
1715 &ls_uart4_apb_gate,
1716 &ls_i2c0_apb_gate,
1717 &ls_i2c1_apb_gate,
1718 &ls_i2c2_apb_gate,
1719 &ls_i2c3_apb_gate,
1720 &ls_i2c4_apb_gate,
1721 &ls_gpio_apb_gate,
1722 &ls_pwm_apb_gate,
1723 &ls_jamlink0_apb_gate,
1724 &ls_jamlink1_apb_gate,
1725 &ls_jamlink2_apb_gate,
1726 &ls_jamlink3_apb_gate,
1727 &ls_audio_apb_gate,
1728 &ls_adc_apb_gate,
1729 &ls_codec_apb_gate,
1730 &ls_i2c0_gate,
1731 &ls_i2c1_gate,
1732 &ls_i2c2_gate,
1733 &ls_i2c3_gate,
1734 &ls_i2c4_gate,
1735 &ls_codec_adc_gate,
1736 &ls_codec_dac_gate,
1737 &ls_audio_dev_gate,
1738 &ls_pdm_gate,
1739 &ls_adc_gate,
1740 &ls_uart0_gate,
1741 &ls_uart1_gate,
1742 &ls_uart2_gate,
1743 &ls_uart3_gate,
1744 &ls_uart4_gate,
1745 &ls_jamlink0co_gate,
1746 &ls_jamlink1co_gate,
1747 &ls_jamlink2co_gate,
1748 &ls_jamlink3co_gate,
1749 &ls_gpio_debounce_gate,
1750 &sysctl_wdt0_apb_gate,
1751 &sysctl_wdt1_apb_gate,
1752 &sysctl_timer_apb_gate,
1753 &sysctl_iomux_apb_gate,
1754 &sysctl_mailbox_apb_gate,
1755 &sysctl_hdi_gate,
1756 &sysctl_time_stamp_gate,
1757 &sysctl_wdt0_gate,
1758 &sysctl_wdt1_gate,
1759 &timer0_gate,
1760 &timer1_gate,
1761 &timer2_gate,
1762 &timer3_gate,
1763 &timer4_gate,
1764 &timer5_gate,
1765 &shrm_apb_gate,
1766 &shrm_sram_gate,
1767 &shrm_axi_gate,
1768 &shrm_axi_slave_gate,
1769 &shrm_nonai2d_axi_gate,
1770 &shrm_decompress_axi_gate,
1771 &shrm_sdma_axi_gate,
1772 &shrm_pdma_axi_gate,
1773 &ddrc_src_gate,
1774 &ddrc_bypass_gate,
1775 &ddrc_apb_gate,
1776 &display_ahb_gate,
1777 &display_axi_gate,
1778 &display_gpu_gate,
1779 &display_dpip_gate,
1780 &display_cfg_gate,
1781 &display_ref_gate,
1782 &vpu_src_gate,
1783 &vpu_axi_gate,
1784 &vpu_ddrcp2_gate,
1785 &vpu_cfg_gate,
1786 &sec_apb_gate,
1787 &sec_fix_gate,
1788 &sec_axi_gate,
1789 &usb_480m_gate,
1790 &usb_100m_gate,
1791 &dphy_dft_gate,
1792 &spi2axi_gate,
1793 &ai_src_gate,
1794 &ai_axi_gate,
1795 &camera0_gate,
1796 &camera1_gate,
1797 &camera2_gate,
1798 };
1799
1800 #define K230_CLK_GATE_NUM ARRAY_SIZE(k230_clk_gates)
1801
1802 static struct k230_clk_rate *k230_clk_rates[] = {
1803 &cpu0_src_rate,
1804 &cpu0_axi_rate,
1805 &cpu0_plic_rate,
1806 &cpu0_apb_rate,
1807 &cpu1_src_rate,
1808 &cpu1_axi_rate,
1809 &cpu1_plic_rate,
1810 &hs_hclk_high_rate,
1811 &hs_hclk_rate,
1812 &hs_ssi0_axi_rate,
1813 &hs_ssi1_rate,
1814 &hs_ssi2_rate,
1815 &hs_qspi_axi_src_rate,
1816 &hs_sd_card_src_rate,
1817 &hs_sd_axi_src_rate,
1818 &hs_usb_ref_50m_rate,
1819 &hs_sd_timer_src_rate,
1820 &ls_apb_src_rate,
1821 &ls_gpio_debounce_rate,
1822 &ls_i2c0_rate,
1823 &ls_i2c1_rate,
1824 &ls_i2c2_rate,
1825 &ls_i2c3_rate,
1826 &ls_i2c4_rate,
1827 &ls_codec_adc_rate,
1828 &ls_codec_dac_rate,
1829 &ls_audio_dev_rate,
1830 &ls_pdm_rate,
1831 &ls_adc_rate,
1832 &ls_uart0_rate,
1833 &ls_uart1_rate,
1834 &ls_uart2_rate,
1835 &ls_uart3_rate,
1836 &ls_uart4_rate,
1837 &ls_jamlinkco_src_rate,
1838 &sysctl_hdi_rate,
1839 &sysctl_time_stamp_rate,
1840 &sysctl_temp_sensor_rate,
1841 &sysctl_wdt0_rate,
1842 &sysctl_wdt1_rate,
1843 &timer0_src_rate,
1844 &timer1_src_rate,
1845 &timer2_src_rate,
1846 &timer3_src_rate,
1847 &timer4_src_rate,
1848 &timer5_src_rate,
1849 &shrm_apb_rate,
1850 &ddrc_src_rate,
1851 &ddrc_apb_rate,
1852 &display_ahb_rate,
1853 &display_clkext_rate,
1854 &display_gpu_rate,
1855 &display_dpip_rate,
1856 &display_cfg_rate,
1857 &vpu_src_rate,
1858 &vpu_axi_src_rate,
1859 &vpu_cfg_rate,
1860 &sec_apb_rate,
1861 &sec_fix_rate,
1862 &sec_axi_rate,
1863 &usb_480m_rate,
1864 &usb_100m_rate,
1865 &dphy_dft_rate,
1866 &spi2axi_rate,
1867 &ai_src_rate,
1868 &camera0_rate,
1869 &camera1_rate,
1870 &camera2_rate,
1871 };
1872
1873 #define K230_CLK_RATE_NUM ARRAY_SIZE(k230_clk_rates)
1874
1875 #define K230_CLK_NUM (K230_CLK_MUX_NUM + K230_CLK_GATE_NUM + K230_CLK_RATE_NUM + 1)
1876
k230_pll_prepare(struct clk_hw * hw)1877 static int k230_pll_prepare(struct clk_hw *hw)
1878 {
1879 struct k230_pll *pll = hw_to_k230_pll(hw);
1880 u32 reg;
1881
1882 /* wait for PLL lock until it reaches lock status */
1883 return readl_poll_timeout(K230_PLLX_LOCK_ADDR(pll->reg, pll->id), reg,
1884 reg & K230_PLL_LOCK_STATUS_MASK,
1885 K230_PLL_LOCK_TIME_DELAY, K230_PLL_LOCK_TIMEOUT);
1886 }
1887
k230_pll_hw_is_enabled(struct k230_pll * pll)1888 static inline bool k230_pll_hw_is_enabled(struct k230_pll *pll)
1889 {
1890 return readl(K230_PLLX_GATE_ADDR(pll->reg, pll->id)) & K230_PLL_GATE_ENABLE;
1891 }
1892
k230_pll_enable_hw(struct k230_pll * pll)1893 static void k230_pll_enable_hw(struct k230_pll *pll)
1894 {
1895 u32 reg;
1896
1897 if (k230_pll_hw_is_enabled(pll))
1898 return;
1899
1900 reg = readl(K230_PLLX_GATE_ADDR(pll->reg, pll->id));
1901 reg |= K230_PLL_GATE_ENABLE | K230_PLL_GATE_WRITE_ENABLE;
1902 writel(reg, K230_PLLX_GATE_ADDR(pll->reg, pll->id));
1903 }
1904
k230_pll_enable(struct clk_hw * hw)1905 static int k230_pll_enable(struct clk_hw *hw)
1906 {
1907 struct k230_pll *pll = hw_to_k230_pll(hw);
1908
1909 guard(spinlock)(pll->lock);
1910
1911 k230_pll_enable_hw(pll);
1912
1913 return 0;
1914 }
1915
k230_pll_disable(struct clk_hw * hw)1916 static void k230_pll_disable(struct clk_hw *hw)
1917 {
1918 struct k230_pll *pll = hw_to_k230_pll(hw);
1919 u32 reg;
1920
1921 guard(spinlock)(pll->lock);
1922
1923 reg = readl(K230_PLLX_GATE_ADDR(pll->reg, pll->id));
1924 reg &= ~(K230_PLL_GATE_ENABLE);
1925 reg |= (K230_PLL_GATE_WRITE_ENABLE);
1926 writel(reg, K230_PLLX_GATE_ADDR(pll->reg, pll->id));
1927 }
1928
k230_pll_is_enabled(struct clk_hw * hw)1929 static int k230_pll_is_enabled(struct clk_hw *hw)
1930 {
1931 return k230_pll_hw_is_enabled(hw_to_k230_pll(hw));
1932 }
1933
k230_pll_get_rate(struct clk_hw * hw,unsigned long parent_rate)1934 static unsigned long k230_pll_get_rate(struct clk_hw *hw, unsigned long parent_rate)
1935 {
1936 struct k230_pll *pll = hw_to_k230_pll(hw);
1937 u32 reg;
1938 u32 r, f, od;
1939
1940 guard(spinlock)(pll->lock);
1941
1942 reg = readl(K230_PLLX_BYPASS_ADDR(pll->reg, pll->id));
1943 if (reg & K230_PLL_BYPASS_ENABLE)
1944 return parent_rate;
1945
1946 reg = readl(K230_PLLX_LOCK_ADDR(pll->reg, pll->id));
1947 if (!(reg & (K230_PLL_LOCK_STATUS_MASK)))
1948 return 0;
1949
1950 reg = readl(K230_PLLX_DIV_ADDR(pll->reg, pll->id));
1951 r = FIELD_GET(K230_PLL_R_MASK, reg) + 1;
1952 f = FIELD_GET(K230_PLL_F_MASK, reg) + 1;
1953 od = FIELD_GET(K230_PLL_OD_MASK, reg) + 1;
1954
1955 return mul_u64_u32_div(parent_rate, f, r * od);
1956 }
1957
k230_register_plls(struct platform_device * pdev,spinlock_t * lock,void __iomem * reg)1958 static int k230_register_plls(struct platform_device *pdev, spinlock_t *lock,
1959 void __iomem *reg)
1960 {
1961 int i, ret;
1962 struct k230_pll *pll;
1963
1964 for (i = 0; i < ARRAY_SIZE(k230_plls); i++) {
1965 const char *name;
1966
1967 pll = k230_plls[i];
1968
1969 name = pll->hw.init->name;
1970 pll->lock = lock;
1971 pll->reg = reg;
1972
1973 ret = devm_clk_hw_register(&pdev->dev, &pll->hw);
1974 if (ret)
1975 return ret;
1976
1977 ret = devm_clk_hw_register_clkdev(&pdev->dev, &pll->hw, name, NULL);
1978 if (ret)
1979 return ret;
1980 }
1981
1982 return 0;
1983 }
1984
k230_register_pll_divs(struct platform_device * pdev)1985 static int k230_register_pll_divs(struct platform_device *pdev)
1986 {
1987 struct clk_fixed_factor *pll_div;
1988 int ret;
1989
1990 for (int i = 0; i < ARRAY_SIZE(k230_pll_divs); i++) {
1991 const char *name;
1992
1993 pll_div = k230_pll_divs[i];
1994
1995 name = pll_div->hw.init->name;
1996
1997 ret = devm_clk_hw_register(&pdev->dev, &pll_div->hw);
1998 if (ret)
1999 return ret;
2000
2001 ret = devm_clk_hw_register_clkdev(&pdev->dev, &pll_div->hw,
2002 name, NULL);
2003 if (ret)
2004 return ret;
2005 }
2006
2007 return 0;
2008 }
2009
k230_clk_get_rate_mul(struct clk_hw * hw,unsigned long parent_rate)2010 static unsigned long k230_clk_get_rate_mul(struct clk_hw *hw,
2011 unsigned long parent_rate)
2012 {
2013 struct k230_clk_rate *clk = hw_to_k230_clk_rate(hw);
2014 struct k230_clk_rate_self *rate_self = &clk->clk;
2015 u32 mul, div;
2016
2017 guard(spinlock)(rate_self->lock);
2018
2019 div = rate_self->div_max;
2020 mul = (readl(rate_self->reg + clk->mul_reg_off) >> rate_self->mul_shift)
2021 & rate_self->mul_mask;
2022
2023 return mul_u64_u32_div(parent_rate, mul + 1, div);
2024 }
2025
k230_clk_get_rate_div(struct clk_hw * hw,unsigned long parent_rate)2026 static unsigned long k230_clk_get_rate_div(struct clk_hw *hw,
2027 unsigned long parent_rate)
2028 {
2029 struct k230_clk_rate *clk = hw_to_k230_clk_rate(hw);
2030 struct k230_clk_rate_self *rate_self = &clk->clk;
2031 u32 mul, div;
2032
2033 guard(spinlock)(rate_self->lock);
2034
2035 mul = rate_self->mul_max;
2036 div = (readl(rate_self->reg + clk->div_reg_off) >> rate_self->div_shift)
2037 & rate_self->div_mask;
2038
2039 return mul_u64_u32_div(parent_rate, mul, div + 1);
2040 }
2041
k230_clk_get_rate_mul_div(struct clk_hw * hw,unsigned long parent_rate)2042 static unsigned long k230_clk_get_rate_mul_div(struct clk_hw *hw,
2043 unsigned long parent_rate)
2044 {
2045 struct k230_clk_rate *clk = hw_to_k230_clk_rate(hw);
2046 struct k230_clk_rate_self *rate_self = &clk->clk;
2047 u32 mul, div;
2048
2049 guard(spinlock)(rate_self->lock);
2050
2051 div = (readl(rate_self->reg + clk->div_reg_off) >> rate_self->div_shift)
2052 & rate_self->div_mask;
2053 mul = (readl(rate_self->reg + clk->mul_reg_off) >> rate_self->mul_shift)
2054 & rate_self->mul_mask;
2055
2056 return mul_u64_u32_div(parent_rate, mul, div);
2057 }
2058
k230_clk_find_approximate_mul(u32 mul_min,u32 mul_max,u32 div_min,u32 div_max,unsigned long rate,unsigned long parent_rate,u32 * div,u32 * mul)2059 static int k230_clk_find_approximate_mul(u32 mul_min, u32 mul_max,
2060 u32 div_min, u32 div_max,
2061 unsigned long rate, unsigned long parent_rate,
2062 u32 *div, u32 *mul)
2063 {
2064 long abs_min;
2065 long abs_current;
2066 long perfect_divide;
2067
2068 if (!rate || !parent_rate || !mul_min)
2069 return -EINVAL;
2070
2071 perfect_divide = (long)((parent_rate * 1000) / rate);
2072 abs_min = abs(perfect_divide -
2073 (long)(((long)div_max * 1000) / (long)mul_min));
2074 *mul = mul_min;
2075
2076 for (u32 i = mul_min + 1; i <= mul_max; i++) {
2077 abs_current = abs(perfect_divide -
2078 (long)(((long)div_max * 1000) / (long)i));
2079
2080 if (abs_min > abs_current) {
2081 abs_min = abs_current;
2082 *mul = i;
2083 }
2084 }
2085
2086 *div = div_max;
2087
2088 return 0;
2089 }
2090
k230_clk_find_approximate_div(u32 mul_min,u32 mul_max,u32 div_min,u32 div_max,unsigned long rate,unsigned long parent_rate,u32 * div,u32 * mul)2091 static int k230_clk_find_approximate_div(u32 mul_min, u32 mul_max,
2092 u32 div_min, u32 div_max,
2093 unsigned long rate, unsigned long parent_rate,
2094 u32 *div, u32 *mul)
2095 {
2096 long abs_min;
2097 long abs_current;
2098 long perfect_divide;
2099
2100 if (!rate || !parent_rate || !mul_max)
2101 return -EINVAL;
2102
2103 perfect_divide = (long)((parent_rate * 1000) / rate);
2104 abs_min = abs(perfect_divide -
2105 (long)(((long)div_min * 1000) / (long)mul_max));
2106 *div = div_min;
2107
2108 for (u32 i = div_min + 1; i <= div_max; i++) {
2109 abs_current = abs(perfect_divide -
2110 (long)(((long)i * 1000) / (long)mul_max));
2111
2112 if (abs_min > abs_current) {
2113 abs_min = abs_current;
2114 *div = i;
2115 }
2116 }
2117
2118 *mul = mul_max;
2119
2120 return 0;
2121 }
2122
k230_clk_find_approximate_mul_div(u32 mul_min,u32 mul_max,u32 div_min,u32 div_max,unsigned long rate,unsigned long parent_rate,u32 * div,u32 * mul)2123 static int k230_clk_find_approximate_mul_div(u32 mul_min, u32 mul_max,
2124 u32 div_min, u32 div_max,
2125 unsigned long rate,
2126 unsigned long parent_rate,
2127 u32 *div, u32 *mul)
2128 {
2129 unsigned long best_mul, best_div;
2130
2131 if (!rate || !parent_rate || !mul_min)
2132 return -EINVAL;
2133
2134 rational_best_approximation(rate, parent_rate,
2135 (unsigned long)mul_max, (unsigned long)div_max,
2136 &best_mul, &best_div);
2137
2138 if (best_mul < mul_min)
2139 best_mul = mul_min;
2140
2141 if (best_div < div_min)
2142 best_div = div_min;
2143
2144 *mul = (u32)best_mul;
2145 *div = (u32)best_div;
2146
2147 return 0;
2148 }
2149
k230_clk_determine_rate_mul(struct clk_hw * hw,struct clk_rate_request * req)2150 static int k230_clk_determine_rate_mul(struct clk_hw *hw, struct clk_rate_request *req)
2151 {
2152 int ret;
2153 struct k230_clk_rate_self *rate_self = hw_to_k230_clk_rate_self(hw);
2154 unsigned long rate = req->rate;
2155 unsigned long parent_rate = req->best_parent_rate;
2156 u32 div, mul;
2157
2158 ret = k230_clk_find_approximate_mul(rate_self->mul_min, rate_self->mul_max,
2159 rate_self->div_min, rate_self->div_max,
2160 rate, parent_rate, &div, &mul);
2161 if (ret)
2162 return ret;
2163
2164 req->rate = mul_u64_u32_div(parent_rate, mul, div);
2165
2166 return 0;
2167 }
2168
k230_clk_determine_rate_div(struct clk_hw * hw,struct clk_rate_request * req)2169 static int k230_clk_determine_rate_div(struct clk_hw *hw, struct clk_rate_request *req)
2170 {
2171 int ret;
2172 struct k230_clk_rate_self *rate_self = hw_to_k230_clk_rate_self(hw);
2173 unsigned long rate = req->rate;
2174 unsigned long parent_rate = req->best_parent_rate;
2175 u32 div, mul;
2176
2177 ret = k230_clk_find_approximate_div(rate_self->mul_min, rate_self->mul_max,
2178 rate_self->div_min, rate_self->div_max,
2179 rate, parent_rate, &div, &mul);
2180 if (ret)
2181 return ret;
2182
2183 req->rate = mul_u64_u32_div(parent_rate, mul, div);
2184
2185 return 0;
2186 }
2187
k230_clk_determine_rate_mul_div(struct clk_hw * hw,struct clk_rate_request * req)2188 static int k230_clk_determine_rate_mul_div(struct clk_hw *hw, struct clk_rate_request *req)
2189 {
2190 int ret;
2191 struct k230_clk_rate_self *rate_self = hw_to_k230_clk_rate_self(hw);
2192 unsigned long rate = req->rate;
2193 unsigned long parent_rate = req->best_parent_rate;
2194 u32 div, mul;
2195
2196 ret = k230_clk_find_approximate_mul_div(rate_self->mul_min, rate_self->mul_max,
2197 rate_self->div_min, rate_self->div_max,
2198 rate, parent_rate, &div, &mul);
2199 if (ret)
2200 return ret;
2201
2202 req->rate = mul_u64_u32_div(parent_rate, mul, div);
2203
2204 return 0;
2205 }
2206
k230_clk_set_rate_mul(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)2207 static int k230_clk_set_rate_mul(struct clk_hw *hw, unsigned long rate,
2208 unsigned long parent_rate)
2209 {
2210 int ret;
2211 struct k230_clk_rate *clk = hw_to_k230_clk_rate(hw);
2212 struct k230_clk_rate_self *rate_self = &clk->clk;
2213 u32 div, mul, mul_reg;
2214
2215 if (rate > parent_rate)
2216 return -EINVAL;
2217
2218 if (rate_self->read_only)
2219 return 0;
2220
2221 ret = k230_clk_find_approximate_mul(rate_self->mul_min, rate_self->mul_max,
2222 rate_self->div_min, rate_self->div_max,
2223 rate, parent_rate, &div, &mul);
2224 if (ret)
2225 return ret;
2226
2227 guard(spinlock)(rate_self->lock);
2228
2229 mul_reg = readl(rate_self->reg + clk->mul_reg_off);
2230 mul_reg |= ((mul - 1) & rate_self->mul_mask) << (rate_self->mul_shift);
2231 mul_reg |= BIT(rate_self->write_enable_bit);
2232 writel(mul_reg, rate_self->reg + clk->mul_reg_off);
2233
2234 return 0;
2235 }
2236
k230_clk_set_rate_div(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)2237 static int k230_clk_set_rate_div(struct clk_hw *hw, unsigned long rate,
2238 unsigned long parent_rate)
2239 {
2240 int ret;
2241 struct k230_clk_rate *clk = hw_to_k230_clk_rate(hw);
2242 struct k230_clk_rate_self *rate_self = &clk->clk;
2243 u32 div, mul, div_reg;
2244
2245 if (rate > parent_rate)
2246 return -EINVAL;
2247
2248 if (rate_self->read_only)
2249 return 0;
2250
2251 ret = k230_clk_find_approximate_div(rate_self->mul_min, rate_self->mul_max,
2252 rate_self->div_min, rate_self->div_max,
2253 rate, parent_rate, &div, &mul);
2254 if (ret)
2255 return ret;
2256
2257 guard(spinlock)(rate_self->lock);
2258
2259 div_reg = readl(rate_self->reg + clk->div_reg_off);
2260 div_reg |= ((div - 1) & rate_self->div_mask) << (rate_self->div_shift);
2261 div_reg |= BIT(rate_self->write_enable_bit);
2262 writel(div_reg, rate_self->reg + clk->div_reg_off);
2263
2264 return 0;
2265 }
2266
k230_clk_set_rate_mul_div(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)2267 static int k230_clk_set_rate_mul_div(struct clk_hw *hw, unsigned long rate,
2268 unsigned long parent_rate)
2269 {
2270 int ret;
2271 struct k230_clk_rate *clk = hw_to_k230_clk_rate(hw);
2272 struct k230_clk_rate_self *rate_self = &clk->clk;
2273 u32 div, mul, div_reg, mul_reg;
2274
2275 if (rate > parent_rate)
2276 return -EINVAL;
2277
2278 if (rate_self->read_only)
2279 return 0;
2280
2281 ret = k230_clk_find_approximate_mul_div(rate_self->mul_min, rate_self->mul_max,
2282 rate_self->div_min, rate_self->div_max,
2283 rate, parent_rate, &div, &mul);
2284 if (ret)
2285 return ret;
2286
2287 guard(spinlock)(rate_self->lock);
2288
2289 div_reg = readl(rate_self->reg + clk->div_reg_off);
2290 div_reg |= ((div - 1) & rate_self->div_mask) << (rate_self->div_shift);
2291 div_reg |= BIT(rate_self->write_enable_bit);
2292 writel(div_reg, rate_self->reg + clk->div_reg_off);
2293
2294 mul_reg = readl(rate_self->reg + clk->mul_reg_off);
2295 mul_reg |= ((mul - 1) & rate_self->mul_mask) << (rate_self->mul_shift);
2296 mul_reg |= BIT(rate_self->write_enable_bit);
2297 writel(mul_reg, rate_self->reg + clk->mul_reg_off);
2298
2299 return 0;
2300 }
2301
k230_register_clk(int id,struct clk_hw * hw,struct device * dev,struct clk_hw_onecell_data * hw_data)2302 static int k230_register_clk(int id, struct clk_hw *hw, struct device *dev,
2303 struct clk_hw_onecell_data *hw_data)
2304 {
2305 int ret;
2306
2307 ret = devm_clk_hw_register(dev, hw);
2308 if (ret)
2309 return ret;
2310
2311 hw_data->hws[id] = hw;
2312
2313 return 0;
2314 }
2315
k230_register_clks(struct platform_device * pdev,struct clk_hw_onecell_data * hw_data,spinlock_t * lock,void __iomem * reg)2316 static int k230_register_clks(struct platform_device *pdev,
2317 struct clk_hw_onecell_data *hw_data,
2318 spinlock_t *lock, void __iomem *reg)
2319 {
2320 int i, ret;
2321 struct device *dev = &pdev->dev;
2322 struct clk_fixed_factor *fixed_factor = &shrm_sram_div2;
2323 struct k230_clk_mux *mux;
2324 struct k230_clk_gate *gate;
2325 struct k230_clk_rate *rate;
2326
2327 for (i = 0; i < K230_CLK_MUX_NUM; i++) {
2328 mux = k230_clk_muxs[i];
2329 mux->clk.lock = lock;
2330 mux->clk.reg = reg + mux->reg_off;
2331
2332 ret = k230_register_clk(mux->id, &mux->clk.hw, dev, hw_data);
2333 if (ret)
2334 return ret;
2335 }
2336
2337 for (i = 0; i < K230_CLK_GATE_NUM; i++) {
2338 gate = k230_clk_gates[i];
2339 gate->clk.lock = lock;
2340 gate->clk.reg = reg + gate->reg_off;
2341
2342 ret = k230_register_clk(gate->id, &gate->clk.hw, dev, hw_data);
2343 if (ret)
2344 return ret;
2345 }
2346
2347 for (i = 0; i < K230_CLK_RATE_NUM; i++) {
2348 rate = k230_clk_rates[i];
2349 rate->clk.lock = lock;
2350 rate->clk.reg = reg;
2351
2352 ret = k230_register_clk(rate->id, &rate->clk.hw, dev, hw_data);
2353 if (ret)
2354 return ret;
2355 }
2356
2357 ret = k230_register_clk(K230_SHRM_SRAM_DIV2, &fixed_factor->hw, dev, hw_data);
2358 if (ret)
2359 return ret;
2360
2361 return devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get, hw_data);
2362 }
2363
k230_clk_init_plls(struct platform_device * pdev)2364 static int k230_clk_init_plls(struct platform_device *pdev)
2365 {
2366 int ret;
2367 void __iomem *reg;
2368 /* used for all the plls */
2369 spinlock_t *lock;
2370
2371 lock = devm_kzalloc(&pdev->dev, sizeof(*lock), GFP_KERNEL);
2372 if (!lock)
2373 return -ENOMEM;
2374
2375 spin_lock_init(lock);
2376
2377 reg = devm_platform_ioremap_resource(pdev, 0);
2378 if (IS_ERR(reg))
2379 return PTR_ERR(reg);
2380
2381 ret = k230_register_plls(pdev, lock, reg);
2382 if (ret)
2383 return ret;
2384
2385 ret = k230_register_pll_divs(pdev);
2386 if (ret)
2387 return ret;
2388
2389 return 0;
2390 }
2391
k230_clk_init_clks(struct platform_device * pdev,struct clk_hw_onecell_data * hw_data)2392 static int k230_clk_init_clks(struct platform_device *pdev,
2393 struct clk_hw_onecell_data *hw_data)
2394 {
2395 int ret;
2396 void __iomem *reg;
2397 /* used for all the clocks */
2398 spinlock_t *lock;
2399
2400 lock = devm_kzalloc(&pdev->dev, sizeof(*lock), GFP_KERNEL);
2401 if (!lock)
2402 return -ENOMEM;
2403
2404 spin_lock_init(lock);
2405
2406 hw_data->num = K230_CLK_NUM;
2407
2408 reg = devm_platform_ioremap_resource(pdev, 1);
2409 if (IS_ERR(reg))
2410 return PTR_ERR(reg);
2411
2412 ret = k230_register_clks(pdev, hw_data, lock, reg);
2413 if (ret)
2414 return ret;
2415
2416 return 0;
2417 }
2418
k230_clk_probe(struct platform_device * pdev)2419 static int k230_clk_probe(struct platform_device *pdev)
2420 {
2421 int ret;
2422 struct clk_hw_onecell_data *hw_data;
2423
2424 hw_data = devm_kzalloc(&pdev->dev, struct_size(hw_data, hws, K230_CLK_NUM),
2425 GFP_KERNEL);
2426 if (!hw_data)
2427 return -ENOMEM;
2428
2429 ret = k230_clk_init_plls(pdev);
2430 if (ret)
2431 return dev_err_probe(&pdev->dev, ret, "init plls failed\n");
2432
2433 ret = k230_clk_init_clks(pdev, hw_data);
2434 if (ret)
2435 return dev_err_probe(&pdev->dev, ret, "init clks failed\n");
2436
2437 return 0;
2438 }
2439
2440 static const struct of_device_id k230_clk_ids[] = {
2441 { .compatible = "canaan,k230-clk" },
2442 { /* Sentinel */ }
2443 };
2444
2445 static struct platform_driver k230_clk_driver = {
2446 .driver = {
2447 .name = "k230_clock_controller",
2448 .of_match_table = k230_clk_ids,
2449 },
2450 .probe = k230_clk_probe,
2451 };
2452 builtin_platform_driver(k230_clk_driver);
2453