1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2026 UltraRISC Technology (Shanghai) Co., Ltd.
4 */
5
6 #include <linux/module.h>
7
8 #include <dt-bindings/clock/ultrarisc,dp1000-clk.h>
9
10 #include "clk-ultrarisc.h"
11
12 #define DP1000_PLL_CFG1_OFFSET 0x400
13 #define DP1000_PLL_CFG2_OFFSET 0x404
14
15 #define DP1000_CCR_UART_OFFSET 0x220
16 #define DP1000_CCR_I2C_OFFSET 0x224
17 #define DP1000_CCR_GMAC_OFFSET 0x228
18 #define DP1000_CCR_SPI_OFFSET 0x22c
19 #define DP1000_PERI_CLKENA_OFFSET 0x270
20
21 #define DP1000_CCR_LOAD BIT(16)
22
23 #define DP1000_PERI_MAX_RATE 62500000UL
24 #define DP1000_CLK_NUM 21
25
26 static const struct ultrarisc_pll_layout dp1000_pll_layout = {
27 .cfg1_offset = DP1000_PLL_CFG1_OFFSET,
28 .cfg2_offset = DP1000_PLL_CFG2_OFFSET,
29 .frac_mask = GENMASK(23, 0),
30 .m_mask = GENMASK(23, 16),
31 .n_mask = GENMASK(11, 6),
32 .oddiv1_mask = GENMASK(1, 0),
33 .oddiv2_mask = GENMASK(4, 3),
34 };
35
36 static const struct ultrarisc_pll_desc dp1000_plls[] = {
37 {
38 .id = DP1000_CLK_SYSPLL,
39 .name = "syspll_clk",
40 },
41 };
42
43 #define DP1000_FIXED_FACTOR(_id, _name, _parent, _mult, _div) \
44 { \
45 .id = (_id), \
46 .name = (_name), \
47 .parent_id = (_parent), \
48 .mult = (_mult), \
49 .div = (_div), \
50 }
51
52 #define DP1000_DIV(_id, _name, _offset, _parent, _max_rate) \
53 { \
54 .id = (_id), \
55 .name = (_name), \
56 .offset = (_offset), \
57 .parent_id = (_parent), \
58 .max_rate = (_max_rate), \
59 .load_mask = DP1000_CCR_LOAD, \
60 .div_shift = 8, \
61 .div_width = 4, \
62 .gate_bit = 0, \
63 .divider_flags = CLK_DIVIDER_ONE_BASED, \
64 .gate_flags = 0, \
65 }
66
67 #define DP1000_GATE(_id, _name, _parent, _bit) \
68 { \
69 .id = (_id), \
70 .name = (_name), \
71 .offset = DP1000_PERI_CLKENA_OFFSET, \
72 .parent_id = (_parent), \
73 .gate_bit = (_bit), \
74 .gate_flags = 0, \
75 }
76
77 static const struct ultrarisc_fixed_factor_desc dp1000_fixed_factor_clks[] = {
78 DP1000_FIXED_FACTOR(DP1000_CLK_SYSPLL_DIV2, "syspll_div2_clk",
79 DP1000_CLK_SYSPLL, 1, 2),
80 DP1000_FIXED_FACTOR(DP1000_CLK_SUBSYS, "subsys_clk",
81 DP1000_CLK_SYSPLL_DIV2, 1, 2),
82 DP1000_FIXED_FACTOR(DP1000_CLK_PCIE_DBI, "pcie_dbi_clk",
83 DP1000_CLK_SYSPLL, 1, 10),
84 DP1000_FIXED_FACTOR(DP1000_CLK_PCIEX4_CORE, "pciex4_core_clk",
85 DP1000_CLK_SYSPLL, 1, 2),
86 DP1000_FIXED_FACTOR(DP1000_CLK_PCIEX16_CORE, "pciex16_core_clk",
87 DP1000_CLK_SYSPLL, 1, 1),
88 DP1000_FIXED_FACTOR(DP1000_CLK_PCIE_AUX, "pcie_aux_clk",
89 DP1000_CLK_SYSPLL, 1, 40),
90 };
91
92 static const struct ultrarisc_divider_desc dp1000_divider_clks[] = {
93 DP1000_DIV(DP1000_CLK_GMAC, "gmac_clk", DP1000_CCR_GMAC_OFFSET,
94 DP1000_CLK_SYSPLL_DIV2, 0),
95 DP1000_DIV(DP1000_CLK_UART_ROOT, "uart_root_clk",
96 DP1000_CCR_UART_OFFSET, DP1000_CLK_SUBSYS,
97 DP1000_PERI_MAX_RATE),
98 DP1000_DIV(DP1000_CLK_I2C_ROOT, "i2c_root_clk",
99 DP1000_CCR_I2C_OFFSET, DP1000_CLK_SUBSYS,
100 DP1000_PERI_MAX_RATE),
101 DP1000_DIV(DP1000_CLK_SPI_ROOT, "spi_root_clk",
102 DP1000_CCR_SPI_OFFSET, DP1000_CLK_SUBSYS,
103 DP1000_PERI_MAX_RATE),
104 };
105
106 static const struct ultrarisc_gate_desc dp1000_gate_clks[] = {
107 DP1000_GATE(DP1000_CLK_UART0, "uart0_clk", DP1000_CLK_UART_ROOT, 0),
108 DP1000_GATE(DP1000_CLK_UART1, "uart1_clk", DP1000_CLK_UART_ROOT, 1),
109 DP1000_GATE(DP1000_CLK_UART2, "uart2_clk", DP1000_CLK_UART_ROOT, 2),
110 DP1000_GATE(DP1000_CLK_UART3, "uart3_clk", DP1000_CLK_UART_ROOT, 3),
111 DP1000_GATE(DP1000_CLK_I2C0, "i2c0_clk", DP1000_CLK_I2C_ROOT, 4),
112 DP1000_GATE(DP1000_CLK_I2C1, "i2c1_clk", DP1000_CLK_I2C_ROOT, 5),
113 DP1000_GATE(DP1000_CLK_I2C2, "i2c2_clk", DP1000_CLK_I2C_ROOT, 6),
114 DP1000_GATE(DP1000_CLK_I2C3, "i2c3_clk", DP1000_CLK_I2C_ROOT, 7),
115 DP1000_GATE(DP1000_CLK_SPI0, "spi0_clk", DP1000_CLK_SPI_ROOT, 8),
116 DP1000_GATE(DP1000_CLK_SPI1, "spi1_clk", DP1000_CLK_SPI_ROOT, 9),
117 };
118
119 static const struct ultrarisc_clk_soc_data dp1000_clk_soc_data = {
120 .num_clks = DP1000_CLK_NUM,
121 .pll_layout = &dp1000_pll_layout,
122 .plls = dp1000_plls,
123 .num_plls = ARRAY_SIZE(dp1000_plls),
124 .fixed_factors = dp1000_fixed_factor_clks,
125 .num_fixed_factors = ARRAY_SIZE(dp1000_fixed_factor_clks),
126 .dividers = dp1000_divider_clks,
127 .num_dividers = ARRAY_SIZE(dp1000_divider_clks),
128 .gates = dp1000_gate_clks,
129 .num_gates = ARRAY_SIZE(dp1000_gate_clks),
130 };
131
dp1000_clk_probe(struct platform_device * pdev)132 static int dp1000_clk_probe(struct platform_device *pdev)
133 {
134 return ultrarisc_clk_probe(pdev, &dp1000_clk_soc_data);
135 }
136
137 static const struct of_device_id dp1000_clk_of_match[] = {
138 { .compatible = "ultrarisc,dp1000-clk" },
139 { }
140 };
141 MODULE_DEVICE_TABLE(of, dp1000_clk_of_match);
142
143 static struct platform_driver dp1000_clk_driver = {
144 .probe = dp1000_clk_probe,
145 .driver = {
146 .name = "ultrarisc-dp1000-clk",
147 .of_match_table = dp1000_clk_of_match,
148 },
149 };
150 module_platform_driver(dp1000_clk_driver);
151
152 MODULE_IMPORT_NS("CLK_ULTRARISC");
153 MODULE_DESCRIPTION("UltraRISC DP1000 clock controller");
154 MODULE_LICENSE("GPL");
155