Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
"Mostly the usual clk driver updates and new SoC additions plus
non-critic

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
"Mostly the usual clk driver updates and new SoC additions plus
non-critical data fixes for things that weren't used yet.

One thing that's new here in the core is SSC spread spectrum support
(SSC) in the clk provider API. The idea is that DT authors will
configure SSC for certain clks and they'll be configured at clk
provider registration time or when a consumer device is probed,
similar to how we handle assigned clk rates or parents.

On the clk driver side we have Qualcomm adding almost half the diff
because they add support for 4 different SoCs and then a long tail of
other SoCs like Mediatek, Renesas, Rockchip, SpaceMiT, etc. add more
SoC support this time around. Luckily it's mostly clk data for these
new SoCs because the actual clk_ops are already there. Beyond the new
drivers we get all the little fixups for more compilation coverage or
usage of more modern APIs. That all looks normal.

Finally, I kinda buried the lede, I'm bringing on Brian and Jerome to
help out with maintaining the clk subsystem. The current working model
is already semi-distributed in that silicon vendors typically take
care of their drivers and send me pull requests but I'm becoming a
bottleneck for new drivers and core framework review because this has
become a 100% volunteer effort on my part.

Mike is stepping down after all these years (thanks Mike!) and that
jump started the conversation around finding co-maintainers. Brian and
Jerome have graciously offered to help me with the work load, meaning
in the future they'll be sending pull requests and committing directly
to the clk.git tree. They've both been around on the list for a while,
I've met them both in person, and they've been making changes to the
core clk framework along with helping review patches so I'm pretty
confident this will work well.

Core:
- devm_clk_bulk_get_enable() consumer API
- devm_clk_hw_register_composite_pdata() provider API
- Spread Spectrum Clock (SSC) support via DT bindings and provider APIs
- Divider clk rounding improved (and tested)

New Drivers:
- Cix Sky1 audio subsystem (AUDSS)
- UltraRISC DP1000
- MediaTek MT8173 MFG_TOP
- Si549
- Aspeed AST2700 PECI
- Airoha EN7523 PCIe
- Rockchip RV1106
- Mobileye EyeQ7H
- Qualcomm Maili GCC, TCSR, RPMh, and video clks
- Qualcomm Shikra GCC, RPM, GPU, display, and audio clks
- Qualcomm Nord display and graphics clks
- Qualcomm Glymur camera and EVA clks
- Qualcomm Hawi video clks
- Amlogic A9 AO and peripheral clks
- Renesas R-Car X5H (R8A78000) CPG"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (269 commits)
clk: microchip: mpfs: fix regmap_update_bits() mask/val order
clk: visconti: Make sure clk_init_data is fully initialized
clk: ti: Make sure clk_init_data is fully initialized
MAINTAINERS: Add Brian Masney and Jerome Brunet as co-maintainers for clk subsystem
Drop Michael Turquette's clk maintainer entry
clk: ti: composite: resolve parent clocks by DT index, not by name
clk: ti: mux: resolve parent clocks by DT index, not by name
clk: devres: fix cleanup in devm_clk_get_optional_enabled_with_rate()
dt-bindings: clock: ti,keystone-gate: Convert to DT schema
dt-bindings: clock: ti: Convert APLL clock to DT schema
clk: zynq: pll: Fix kernel-doc after determine_rate() conversion
dt-bindings: clock: ti,clockdomain: Convert to DT schema
dt-bindings: clock: Correct white-space style
clk: samsung: Don't include <linux/mod_devicetable.h>
clk: at91: Read "reg" with helper
clk: renesas: Add R-Car X5H CPG driver
clk: rockchip: rk3576: fix source muxes for SPI0..SPI4
clk: rockchip: Add clock controller for the RV1106
dt-bindings: clock: rockchip: Add RV1106 CRU support
dt-bindings: clock: Document Renesas R-Car X5H Clock Pulse Generator
...

show more ...

Merge branches 'clk-renesas', 'clk-thead', 'clk-mobileye', 'clk-amlogic' and 'clk-spacemit' into clk-next

* clk-renesas:
clk: renesas: Add R-Car X5H CPG driver
dt-bindings: clock: Document Renes

Merge branches 'clk-renesas', 'clk-thead', 'clk-mobileye', 'clk-amlogic' and 'clk-spacemit' into clk-next

* clk-renesas:
clk: renesas: Add R-Car X5H CPG driver
dt-bindings: clock: Document Renesas R-Car X5H Clock Pulse Generator
clk: r9a08g045: Add clocks and resets for CAN-FD
dt-bindings: clock: renesas,versaclock7: Update maintainer
clk: renesas: r9a09g047: Add LVDS clocks and resets
clk: renesas: r9a09g077: Add LCDC and PLL3 clock support for RZ/T2H display pipeline
clk: renesas: rzv2h-cpg: Extract PLL calculation helpers into shared library
clk: renesas: rzv2h-cpg: Use per-SoC PLL reference frequency for calculations
clk: renesas: r9a08g046: Add USB2.0 clock and reset entries
clk: renesas: r9a09g077: Add RTC clocks
clk: renesas: cpg-mssr: Implement dedicated MSTP delay logic for RZ/T2H LCDC and RTC
clk: renesas: r9a08g046: Add clock and reset entries for GE3D
clk: renesas: r9a08g046: Add clock and reset entries for SDHI
clk: renesas: r9a09g047: Add audio clock and reset support
dt-bindings: clock: renesas: Add audio clock inputs for RZ/V2H family
dt-bindings: clock: renesas,r9a09g077/87: Add PCLKRTC clock ID
dt-bindings: clock: renesas,r9a09g077/87: Add LCDC_CLKD clock ID

* clk-thead:
clk: thead: allow COMPILE_TEST builds

* clk-mobileye:
clk: eyeq: Add EyeQ7H compatibles
clk: eyeq: Drop PLL, dividers, and fixed factors structs
clk: eyeq: Convert clocks declaration to eqc_clock
clk: eyeq: Introduce a generic clock type
clk: eyeq: Prefix the PLL registers with the PLL type
clk: fixed-factor: Export __clk_hw_register_fixed_factor()
clk: fixed-factor: Rework initialization with parent clocks
reset: eyeq: Add EyeQ7H compatibles
dt-bindings: soc: mobileye: Add EyeQ7H OLB

* clk-amlogic:
clk: amlogic: Add A9 peripherals clock controller driver
dt-bindings: clock: Add Amlogic A9 peripherals clock controller
clk: amlogic: Add A9 AO clock controller driver
dt-bindings: clock: Add Amlogic A9 AO clock controller
clk: meson: align gxbb_32k_clk_sel number of parents with actual count

* clk-spacemit:
clk: spacemit: k3: fix missing /2 factor in i2s sysclk dividers
clk: spacemit: k3: fix i2s clock topology
dt-bindings: soc: spacemit: k3: add i2s_sysclk, i2s_bclk_factor and i2s1_sysclk_src IDs
clk: spacemit: k3: Add UFS refclk clock
dt-bindings: soc: spacemit: k3: Add clock ID for UFS refclk
clk: spacemit: k3: fix parent clock of UFS aclk

show more ...

Merge tag 'clk-meson-v7.3-1' of ssh://github.com/BayLibre/clk-meson into clk-amlogic

Pull Amlogic clk driver updates from Jerome Brunet:

- Fix the incorrect parent number of the 32k clock on Amlog

Merge tag 'clk-meson-v7.3-1' of ssh://github.com/BayLibre/clk-meson into clk-amlogic

Pull Amlogic clk driver updates from Jerome Brunet:

- Fix the incorrect parent number of the 32k clock on Amlogic GXBB
- Add the AO and peripheral clock controllers for the new Amlogic A9 chip

* tag 'clk-meson-v7.3-1' of ssh://github.com/BayLibre/clk-meson:
clk: amlogic: Add A9 peripherals clock controller driver
dt-bindings: clock: Add Amlogic A9 peripherals clock controller
clk: amlogic: Add A9 AO clock controller driver
dt-bindings: clock: Add Amlogic A9 AO clock controller
clk: meson: align gxbb_32k_clk_sel number of parents with actual count

show more ...

clk: amlogic: Add A9 peripherals clock controller driver

Add the peripherals clock controller driver for the Amlogic A9 SoC family.

Signed-off-by: Jian Hu <jian.hu@amlogic.com>
Link: https://patch.

clk: amlogic: Add A9 peripherals clock controller driver

Add the peripherals clock controller driver for the Amlogic A9 SoC family.

Signed-off-by: Jian Hu <jian.hu@amlogic.com>
Link: https://patch.msgid.link/20260701-a9_peripherals-v6-2-9630f39879e5@amlogic.com
[jbrunet: removed dependency en A9 PLL]
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

show more ...