Home
last modified time | relevance | path

Searched refs:DEF_MOD (Results 1 – 25 of 29) sorted by relevance

12

/linux/drivers/clk/renesas/
H A Dr8a7795-cpg-mssr.c132 DEF_MOD("3dge", 112, R8A7795_CLK_ZG),
133 DEF_MOD("fdp1-1", 118, R8A7795_CLK_S0D1),
134 DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1),
135 DEF_MOD("tmu4", 121, R8A7795_CLK_S0D6),
136 DEF_MOD("tmu3", 122, R8A7795_CLK_S3D2),
137 DEF_MOD("tmu2", 123, R8A7795_CLK_S3D2),
138 DEF_MOD("tmu1", 124, R8A7795_CLK_S3D2),
139 DEF_MOD("tmu0", 125, R8A7795_CLK_CP),
140 DEF_MOD("scif5", 202, R8A7795_CLK_S3D4),
141 DEF_MOD("scif4", 203, R8A7795_CLK_S3D4),
[all …]
H A Dr8a7742-cpg-mssr.c83 DEF_MOD("msiof0", 0, R8A7742_CLK_MP),
84 DEF_MOD("vcp1", 100, R8A7742_CLK_ZS),
85 DEF_MOD("vcp0", 101, R8A7742_CLK_ZS),
86 DEF_MOD("vpc1", 102, R8A7742_CLK_ZS),
87 DEF_MOD("vpc0", 103, R8A7742_CLK_ZS),
88 DEF_MOD("tmu1", 111, R8A7742_CLK_P),
89 DEF_MOD("3dg", 112, R8A7742_CLK_ZG),
90 DEF_MOD("2d-dmac", 115, R8A7742_CLK_ZS),
91 DEF_MOD("fdp1-2", 117, R8A7742_CLK_ZS),
92 DEF_MOD("fdp1-1", 118, R8A7742_CLK_ZS),
[all …]
H A Dr8a7796-cpg-mssr.c134 DEF_MOD("3dge", 112, R8A7796_CLK_ZG),
135 DEF_MOD("fdp1-0", 119, R8A7796_CLK_S0D1),
136 DEF_MOD("tmu4", 121, R8A7796_CLK_S0D6),
137 DEF_MOD("tmu3", 122, R8A7796_CLK_S3D2),
138 DEF_MOD("tmu2", 123, R8A7796_CLK_S3D2),
139 DEF_MOD("tmu1", 124, R8A7796_CLK_S3D2),
140 DEF_MOD("tmu0", 125, R8A7796_CLK_CP),
141 DEF_MOD("scif5", 202, R8A7796_CLK_S3D4),
142 DEF_MOD("scif4", 203, R8A7796_CLK_S3D4),
143 DEF_MOD("scif3", 204, R8A7796_CLK_S3D4),
[all …]
H A Dr8a77965-cpg-mssr.c129 DEF_MOD("3dge", 112, R8A77965_CLK_ZG),
130 DEF_MOD("fdp1-0", 119, R8A77965_CLK_S0D1),
131 DEF_MOD("tmu4", 121, R8A77965_CLK_S0D6),
132 DEF_MOD("tmu3", 122, R8A77965_CLK_S3D2),
133 DEF_MOD("tmu2", 123, R8A77965_CLK_S3D2),
134 DEF_MOD("tmu1", 124, R8A77965_CLK_S3D2),
135 DEF_MOD("tmu0", 125, R8A77965_CLK_CP),
136 DEF_MOD("scif5", 202, R8A77965_CLK_S3D4),
137 DEF_MOD("scif4", 203, R8A77965_CLK_S3D4),
138 DEF_MOD("scif3", 204, R8A77965_CLK_S3D4),
[all …]
H A Dr8a7743-cpg-mssr.c81 DEF_MOD("msiof0", 0, R8A7743_CLK_MP),
82 DEF_MOD("vcp0", 101, R8A7743_CLK_ZS),
83 DEF_MOD("vpc0", 103, R8A7743_CLK_ZS),
84 DEF_MOD("tmu1", 111, R8A7743_CLK_P),
85 DEF_MOD("3dg", 112, R8A7743_CLK_ZG),
86 DEF_MOD("2d-dmac", 115, R8A7743_CLK_ZS),
87 DEF_MOD("fdp1-1", 118, R8A7743_CLK_ZS),
88 DEF_MOD("fdp1-0", 119, R8A7743_CLK_ZS),
89 DEF_MOD("tmu3", 121, R8A7743_CLK_P),
90 DEF_MOD("tmu2", 122, R8A7743_CLK_P),
[all …]
H A Dr8a7791-cpg-mssr.c89 DEF_MOD("msiof0", 0, R8A7791_CLK_MP),
90 DEF_MOD("vcp0", 101, R8A7791_CLK_ZS),
91 DEF_MOD("vpc0", 103, R8A7791_CLK_ZS),
92 DEF_MOD("jpu", 106, R8A7791_CLK_M2),
93 DEF_MOD("ssp1", 109, R8A7791_CLK_ZS),
94 DEF_MOD("tmu1", 111, R8A7791_CLK_P),
95 DEF_MOD("3dg", 112, R8A7791_CLK_ZG),
96 DEF_MOD("2d-dmac", 115, R8A7791_CLK_ZS),
97 DEF_MOD("fdp1-1", 118, R8A7791_CLK_ZS),
98 DEF_MOD("fdp1-0", 119, R8A7791_CLK_ZS),
[all …]
H A Dr8a7790-cpg-mssr.c92 DEF_MOD("msiof0", 0, R8A7790_CLK_MP),
93 DEF_MOD("vcp1", 100, R8A7790_CLK_ZS),
94 DEF_MOD("vcp0", 101, R8A7790_CLK_ZS),
95 DEF_MOD("vpc1", 102, R8A7790_CLK_ZS),
96 DEF_MOD("vpc0", 103, R8A7790_CLK_ZS),
97 DEF_MOD("jpu", 106, R8A7790_CLK_M2),
98 DEF_MOD("ssp1", 109, R8A7790_CLK_ZS),
99 DEF_MOD("tmu1", 111, R8A7790_CLK_P),
100 DEF_MOD("3dg", 112, R8A7790_CLK_ZG),
101 DEF_MOD("2d-dmac", 115, R8A7790_CLK_ZS),
[all …]
H A Dr8a774e1-cpg-mssr.c128 DEF_MOD("3dge", 112, R8A774E1_CLK_ZG),
129 DEF_MOD("fdp1-1", 118, R8A774E1_CLK_S0D1),
130 DEF_MOD("fdp1-0", 119, R8A774E1_CLK_S0D1),
131 DEF_MOD("tmu4", 121, R8A774E1_CLK_S0D6),
132 DEF_MOD("tmu3", 122, R8A774E1_CLK_S3D2),
133 DEF_MOD("tmu2", 123, R8A774E1_CLK_S3D2),
134 DEF_MOD("tmu1", 124, R8A774E1_CLK_S3D2),
135 DEF_MOD("tmu0", 125, R8A774E1_CLK_CP),
136 DEF_MOD("vcplf", 130, R8A774E1_CLK_S2D1),
137 DEF_MOD("vdpb", 131, R8A774E1_CLK_S2D1),
[all …]
H A Dr8a7745-cpg-mssr.c81 DEF_MOD("msiof0", 0, R8A7745_CLK_MP),
82 DEF_MOD("vcp0", 101, R8A7745_CLK_ZS),
83 DEF_MOD("vpc0", 103, R8A7745_CLK_ZS),
84 DEF_MOD("tmu1", 111, R8A7745_CLK_P),
85 DEF_MOD("3dg", 112, R8A7745_CLK_ZG),
86 DEF_MOD("2d-dmac", 115, R8A7745_CLK_ZS),
87 DEF_MOD("fdp1-0", 119, R8A7745_CLK_ZS),
88 DEF_MOD("tmu3", 121, R8A7745_CLK_P),
89 DEF_MOD("tmu2", 122, R8A7745_CLK_P),
90 DEF_MOD("cmt0", 124, R8A7745_CLK_R),
[all …]
H A Dr8a774a1-cpg-mssr.c127 DEF_MOD("3dge", 112, R8A774A1_CLK_ZG),
128 DEF_MOD("tmu4", 121, R8A774A1_CLK_S0D6),
129 DEF_MOD("tmu3", 122, R8A774A1_CLK_S3D2),
130 DEF_MOD("tmu2", 123, R8A774A1_CLK_S3D2),
131 DEF_MOD("tmu1", 124, R8A774A1_CLK_S3D2),
132 DEF_MOD("tmu0", 125, R8A774A1_CLK_CP),
133 DEF_MOD("fdp1-0", 119, R8A774A1_CLK_S0D1),
134 DEF_MOD("scif5", 202, R8A774A1_CLK_S3D4),
135 DEF_MOD("scif4", 203, R8A774A1_CLK_S3D4),
136 DEF_MOD("scif3", 204, R8A774A1_CLK_S3D4),
[all …]
H A Dr8a774b1-cpg-mssr.c124 DEF_MOD("3dge", 112, R8A774B1_CLK_ZG),
125 DEF_MOD("tmu4", 121, R8A774B1_CLK_S0D6),
126 DEF_MOD("tmu3", 122, R8A774B1_CLK_S3D2),
127 DEF_MOD("tmu2", 123, R8A774B1_CLK_S3D2),
128 DEF_MOD("tmu1", 124, R8A774B1_CLK_S3D2),
129 DEF_MOD("tmu0", 125, R8A774B1_CLK_CP),
130 DEF_MOD("fdp1-0", 119, R8A774B1_CLK_S0D1),
131 DEF_MOD("scif5", 202, R8A774B1_CLK_S3D4),
132 DEF_MOD("scif4", 203, R8A774B1_CLK_S3D4),
133 DEF_MOD("scif3", 204, R8A774B1_CLK_S3D4),
[all …]
H A Dr8a7794-cpg-mssr.c87 DEF_MOD("msiof0", 0, R8A7794_CLK_MP),
88 DEF_MOD("vcp0", 101, R8A7794_CLK_ZS),
89 DEF_MOD("vpc0", 103, R8A7794_CLK_ZS),
90 DEF_MOD("jpu", 106, R8A7794_CLK_M2),
91 DEF_MOD("tmu1", 111, R8A7794_CLK_P),
92 DEF_MOD("3dg", 112, R8A7794_CLK_ZG),
93 DEF_MOD("2d-dmac", 115, R8A7794_CLK_ZS),
94 DEF_MOD("fdp1-0", 119, R8A7794_CLK_ZS),
95 DEF_MOD("tmu3", 121, R8A7794_CLK_P),
96 DEF_MOD("tmu2", 122, R8A7794_CLK_P),
[all …]
H A Dr8a77990-cpg-mssr.c136 DEF_MOD("tmu4", 121, R8A77990_CLK_S0D6C),
137 DEF_MOD("tmu3", 122, R8A77990_CLK_S3D2C),
138 DEF_MOD("tmu2", 123, R8A77990_CLK_S3D2C),
139 DEF_MOD("tmu1", 124, R8A77990_CLK_S3D2C),
140 DEF_MOD("tmu0", 125, R8A77990_CLK_CP),
141 DEF_MOD("scif5", 202, R8A77990_CLK_S3D4C),
142 DEF_MOD("scif4", 203, R8A77990_CLK_S3D4C),
143 DEF_MOD("scif3", 204, R8A77990_CLK_S3D4C),
144 DEF_MOD("scif1", 206, R8A77990_CLK_S3D4C),
145 DEF_MOD("scif0", 207, R8A77990_CLK_S3D4C),
[all …]
H A Dr8a77470-cpg-mssr.c77 DEF_MOD("msiof0", 0, R8A77470_CLK_MP),
78 DEF_MOD("vcp0", 101, R8A77470_CLK_ZS),
79 DEF_MOD("vpc0", 103, R8A77470_CLK_ZS),
80 DEF_MOD("tmu1", 111, R8A77470_CLK_P),
81 DEF_MOD("3dg", 112, R8A77470_CLK_ZS),
82 DEF_MOD("2d-dmac", 115, R8A77470_CLK_ZS),
83 DEF_MOD("fdp1-0", 119, R8A77470_CLK_ZS),
84 DEF_MOD("tmu3", 121, R8A77470_CLK_P),
85 DEF_MOD("tmu2", 122, R8A77470_CLK_P),
86 DEF_MOD("cmt0", 124, R8A77470_CLK_R),
[all …]
H A Dr8a774c0-cpg-mssr.c135 DEF_MOD("tmu4", 121, R8A774C0_CLK_S0D6C),
136 DEF_MOD("tmu3", 122, R8A774C0_CLK_S3D2C),
137 DEF_MOD("tmu2", 123, R8A774C0_CLK_S3D2C),
138 DEF_MOD("tmu1", 124, R8A774C0_CLK_S3D2C),
139 DEF_MOD("tmu0", 125, R8A774C0_CLK_CP),
140 DEF_MOD("scif5", 202, R8A774C0_CLK_S3D4C),
141 DEF_MOD("scif4", 203, R8A774C0_CLK_S3D4C),
142 DEF_MOD("scif3", 204, R8A774C0_CLK_S3D4C),
143 DEF_MOD("scif1", 206, R8A774C0_CLK_S3D4C),
144 DEF_MOD("scif0", 207, R8A774C0_CLK_S3D4C),
[all …]
H A Dr8a779a0-cpg-mssr.c145 DEF_MOD("3dge", 0, R8A779A0_CLK_ZG),
146 DEF_MOD("isp0", 16, R8A779A0_CLK_S1D1),
147 DEF_MOD("isp1", 17, R8A779A0_CLK_S1D1),
148 DEF_MOD("isp2", 18, R8A779A0_CLK_S1D1),
149 DEF_MOD("isp3", 19, R8A779A0_CLK_S1D1),
150 DEF_MOD("avb0", 211, R8A779A0_CLK_S3D2),
151 DEF_MOD("avb1", 212, R8A779A0_CLK_S3D2),
152 DEF_MOD("avb2", 213, R8A779A0_CLK_S3D2),
153 DEF_MOD("avb3", 214, R8A779A0_CLK_S3D2),
154 DEF_MOD("avb4", 215, R8A779A0_CLK_S3D2),
[all …]
H A Dr8a77980-cpg-mssr.c116 DEF_MOD("tmu4", 121, R8A77980_CLK_S0D6),
117 DEF_MOD("tmu3", 122, R8A77980_CLK_S0D6),
118 DEF_MOD("tmu2", 123, R8A77980_CLK_S0D6),
119 DEF_MOD("tmu1", 124, R8A77980_CLK_S0D6),
120 DEF_MOD("tmu0", 125, R8A77980_CLK_CP),
121 DEF_MOD("scif4", 203, R8A77980_CLK_S3D4),
122 DEF_MOD("scif3", 204, R8A77980_CLK_S3D4),
123 DEF_MOD("scif1", 206, R8A77980_CLK_S3D4),
124 DEF_MOD("scif0", 207, R8A77980_CLK_S3D4),
125 DEF_MOD("msiof3", 208, R8A77980_CLK_MSO),
[all …]
H A Dr8a7792-cpg-mssr.c80 DEF_MOD("msiof0", 0, R8A7792_CLK_MP),
81 DEF_MOD("jpu", 106, R8A7792_CLK_M2),
82 DEF_MOD("tmu1", 111, R8A7792_CLK_P),
83 DEF_MOD("3dg", 112, R8A7792_CLK_ZG),
84 DEF_MOD("2d-dmac", 115, R8A7792_CLK_ZS),
85 DEF_MOD("tmu3", 121, R8A7792_CLK_P),
86 DEF_MOD("tmu2", 122, R8A7792_CLK_P),
87 DEF_MOD("cmt0", 124, R8A7792_CLK_R),
88 DEF_MOD("tmu0", 125, R8A7792_CLK_CP),
89 DEF_MOD("vsp1du1", 127, R8A7792_CLK_ZS),
[all …]
H A Dr8a77995-cpg-mssr.c122 DEF_MOD("tmu4", 121, R8A77995_CLK_S1D4C),
123 DEF_MOD("tmu3", 122, R8A77995_CLK_S3D2C),
124 DEF_MOD("tmu2", 123, R8A77995_CLK_S3D2C),
125 DEF_MOD("tmu1", 124, R8A77995_CLK_S3D2C),
126 DEF_MOD("tmu0", 125, R8A77995_CLK_CP),
127 DEF_MOD("scif5", 202, R8A77995_CLK_S3D4C),
128 DEF_MOD("scif4", 203, R8A77995_CLK_S3D4C),
129 DEF_MOD("scif3", 204, R8A77995_CLK_S3D4C),
130 DEF_MOD("scif1", 206, R8A77995_CLK_S3D4C),
131 DEF_MOD("scif0", 207, R8A77995_CLK_S3D4C),
[all …]
H A Dr9a09g047-cpg.c197 DEF_MOD("dmac_0_aclk", CLK_PLLCM33_GEAR, 0, 0, 0, 0,
199 DEF_MOD("dmac_1_aclk", CLK_PLLDTY_ACPU_DIV2, 0, 1, 0, 1,
201 DEF_MOD("dmac_2_aclk", CLK_PLLDTY_ACPU_DIV2, 0, 2, 0, 2,
203 DEF_MOD("dmac_3_aclk", CLK_PLLDTY_RCPU_DIV4, 0, 3, 0, 3,
205 DEF_MOD("dmac_4_aclk", CLK_PLLDTY_RCPU_DIV4, 0, 4, 0, 4,
211 DEF_MOD("gpt_0_pclk_sfr", CLK_PLLCLN_DIV8, 3, 1, 1, 17,
213 DEF_MOD("gpt_1_pclk_sfr", CLK_PLLCLN_DIV8, 3, 2, 1, 18,
215 DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13,
217 DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14,
219 DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15,
[all …]
H A Dr9a09g057-cpg.c245 DEF_MOD("dmac_0_aclk", CLK_PLLCM33_GEAR, 0, 0, 0, 0,
247 DEF_MOD("dmac_1_aclk", CLK_PLLDTY_ACPU_DIV2, 0, 1, 0, 1,
249 DEF_MOD("dmac_2_aclk", CLK_PLLDTY_ACPU_DIV2, 0, 2, 0, 2,
251 DEF_MOD("dmac_3_aclk", CLK_PLLDTY_RCPU_DIV4, 0, 3, 0, 3,
253 DEF_MOD("dmac_4_aclk", CLK_PLLDTY_RCPU_DIV4, 0, 4, 0, 4,
259 DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3,
261 DEF_MOD("gtm_1_pclk", CLK_PLLCM33_DIV16, 4, 4, 2, 4,
263 DEF_MOD("gtm_2_pclk", CLK_PLLCLN_DIV16, 4, 5, 2, 5,
265 DEF_MOD("gtm_3_pclk", CLK_PLLCLN_DIV16, 4, 6, 2, 6,
267 DEF_MOD("gtm_4_pclk", CLK_PLLCLN_DIV16, 4, 7, 2, 7,
[all …]
H A Dr9a09g056-cpg.c236 DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3,
238 DEF_MOD("gtm_1_pclk", CLK_PLLCM33_DIV16, 4, 4, 2, 4,
240 DEF_MOD("gtm_2_pclk", CLK_PLLCLN_DIV16, 4, 5, 2, 5,
242 DEF_MOD("gtm_3_pclk", CLK_PLLCLN_DIV16, 4, 6, 2, 6,
244 DEF_MOD("gtm_4_pclk", CLK_PLLCLN_DIV16, 4, 7, 2, 7,
246 DEF_MOD("gtm_5_pclk", CLK_PLLCLN_DIV16, 4, 8, 2, 8,
248 DEF_MOD("gtm_6_pclk", CLK_PLLCLN_DIV16, 4, 9, 2, 9,
250 DEF_MOD("gtm_7_pclk", CLK_PLLCLN_DIV16, 4, 10, 2, 10,
252 DEF_MOD("wdt_0_clkp", CLK_PLLCM33_DIV16, 4, 11, 2, 11,
254 DEF_MOD("wdt_0_clk_loco", CLK_QEXTAL, 4, 12, 2, 12,
[all …]
H A Dr8a779f0-cpg-mssr.c131 DEF_MOD("hscif0", 514, R8A779F0_CLK_SASYNCPERD1),
132 DEF_MOD("hscif1", 515, R8A779F0_CLK_SASYNCPERD1),
133 DEF_MOD("hscif2", 516, R8A779F0_CLK_SASYNCPERD1),
134 DEF_MOD("hscif3", 517, R8A779F0_CLK_SASYNCPERD1),
135 DEF_MOD("i2c0", 518, R8A779F0_CLK_S0D6_PER),
136 DEF_MOD("i2c1", 519, R8A779F0_CLK_S0D6_PER),
137 DEF_MOD("i2c2", 520, R8A779F0_CLK_S0D6_PER),
138 DEF_MOD("i2c3", 521, R8A779F0_CLK_S0D6_PER),
139 DEF_MOD("i2c4", 522, R8A779F0_CLK_S0D6_PER),
140 DEF_MOD("i2c5", 523, R8A779F0_CLK_S0D6_PER),
[all …]
H A Dr9a07g044-cpg.c244 DEF_MOD("gic", R9A07G044_GIC600_GICCLK, R9A07G044_CLK_P1,
246 DEF_MOD("ia55_pclk", R9A07G044_IA55_PCLK, R9A07G044_CLK_P2,
248 DEF_MOD("ia55_clk", R9A07G044_IA55_CLK, R9A07G044_CLK_P1,
250 DEF_MOD("dmac_aclk", R9A07G044_DMAC_ACLK, R9A07G044_CLK_P1,
252 DEF_MOD("dmac_pclk", R9A07G044_DMAC_PCLK, CLK_P1_DIV2,
254 DEF_MOD("ostm0_pclk", R9A07G044_OSTM0_PCLK, R9A07G044_CLK_P0,
256 DEF_MOD("ostm1_pclk", R9A07G044_OSTM1_PCLK, R9A07G044_CLK_P0,
258 DEF_MOD("ostm2_pclk", R9A07G044_OSTM2_PCLK, R9A07G044_CLK_P0,
260 DEF_MOD("mtu_x_mck", R9A07G044_MTU_X_MCK_MTU3, R9A07G044_CLK_P0,
262 DEF_MOD("gpt_pclk", R9A07G044_GPT_PCLK, R9A07G044_CLK_P0,
[all …]
H A Dr9a07g043-cpg.c166 DEF_MOD("gic", R9A07G043_GIC600_GICCLK, R9A07G043_CLK_P1,
168 DEF_MOD("ia55_pclk", R9A07G043_IA55_PCLK, R9A07G043_CLK_P2,
170 DEF_MOD("ia55_clk", R9A07G043_IA55_CLK, R9A07G043_CLK_P1,
174 DEF_MOD("iax45_pclk", R9A07G043_IAX45_PCLK, R9A07G043_CLK_P2,
176 DEF_MOD("iax45_clk", R9A07G043_IAX45_CLK, R9A07G043_CLK_P1,
179 DEF_MOD("dmac_aclk", R9A07G043_DMAC_ACLK, R9A07G043_CLK_P1,
181 DEF_MOD("dmac_pclk", R9A07G043_DMAC_PCLK, CLK_P1_DIV2,
183 DEF_MOD("ostm0_pclk", R9A07G043_OSTM0_PCLK, R9A07G043_CLK_P0,
185 DEF_MOD("ostm1_pclk", R9A07G043_OSTM1_PCLK, R9A07G043_CLK_P0,
187 DEF_MOD("ostm2_pclk", R9A07G043_OSTM2_PCLK, R9A07G043_CLK_P0,
[all …]

12