Searched refs:CPM (Results 1 – 15 of 15) sorted by relevance
1 PPC4xx Clock Power Management (CPM) node9 - er-offset : All 4xx SoCs with a CPM controller have10 one of two different order for the CPM11 registers. Some have the CPM registers18 in CPM will be set to turn off unused22 in CPM will be set to turn off unused23 devices. This is usually just CPM[CPU].26 in CPM will be set on standby and30 in CPM will be set on suspend (mem) and
14 coprocessors on Freescale embedded CPUs (akin to CPM in older chips).37 tristate "CPM/QE TSA support"40 ((CPM || QUICC_ENGINE) && COMPILE_TEST)42 Freescale CPM/QE Time Slot Assigner (TSA)49 tristate "CPM/QE QMC support"54 Freescale CPM/QE QUICC Multichannel Controller
7 * Root CPM node22 * Properties common to multiple CPM/QE devices25 to specify the device on which a CPM command operates.38 The multi-user/dual-ported RAM is expressed as a bus under the CPM node.47 CPM-side offsets with pointer subtraction. It is recommended that
37 …| CPM (core) | 0 | 0 | Snoop-Logic | CPM # …39 …| CPM (core) | 0 | 2 | Armv8 Core 1 | CPM # …
24 QE and two options for CPM.
18 CPM UART driver, the port-number is required for the QE UART driver.
4 select CPM94 menu "MPC8xx CPM Options"
3 The I2C controller is expressed as a bus under the CPM node.
65 /* CON15,16 - CPM lane 4 */245 /* CPM Lane 5 - U29 */
145 * SPI on CPM and NAND have common pins on this board. We can
84 CPM, enumerator635 .version = CPM,
764 * Since our pcie doesn't support ClockPM(CPM), we want766 * de-assert it along and make ClockPM(CPM) work.
295 tristate "Freescale QE/CPM USB Device Controller"296 depends on FSL_SOC && (QUICC_ENGINE || CPM)
1135 PPC4xx Clock Power Management (CPM) support (suspend/resume).
10174 FREESCALE I2C CPM DRIVER20321 PCI DRIVER FOR XILINX VERSAL CPM