xref: /linux/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi (revision cdd5b5a9761fd66d17586e4f4ba6588c70e640ea)
1b1f0bbe2SRussell King// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2b1f0bbe2SRussell King/*
3b1f0bbe2SRussell King * Copyright (C) 2016 Marvell Technology Group Ltd.
4b1f0bbe2SRussell King *
5b1f0bbe2SRussell King * Device Tree file for MACCHIATOBin Armada 8040 community board platform
6b1f0bbe2SRussell King */
7b1f0bbe2SRussell King
8b1f0bbe2SRussell King#include "armada-8040.dtsi"
9b1f0bbe2SRussell King
10b1f0bbe2SRussell King#include <dt-bindings/gpio/gpio.h>
11b1f0bbe2SRussell King
12b1f0bbe2SRussell King/ {
13b1f0bbe2SRussell King	model = "Marvell 8040 MACCHIATOBin";
14b1f0bbe2SRussell King	compatible = "marvell,armada8040-mcbin", "marvell,armada8040",
15b1f0bbe2SRussell King			"marvell,armada-ap806-quad", "marvell,armada-ap806";
16b1f0bbe2SRussell King
17b1f0bbe2SRussell King	chosen {
18b1f0bbe2SRussell King		stdout-path = "serial0:115200n8";
19b1f0bbe2SRussell King	};
20b1f0bbe2SRussell King
21b1f0bbe2SRussell King	memory@0 {
22b1f0bbe2SRussell King		device_type = "memory";
23b1f0bbe2SRussell King		reg = <0x0 0x0 0x0 0x80000000>;
24b1f0bbe2SRussell King	};
25b1f0bbe2SRussell King
26b1f0bbe2SRussell King	aliases {
27b1f0bbe2SRussell King		ethernet0 = &cp0_eth0;
28b1f0bbe2SRussell King		ethernet1 = &cp1_eth0;
29b1f0bbe2SRussell King		ethernet2 = &cp1_eth1;
30b1f0bbe2SRussell King		ethernet3 = &cp1_eth2;
31b1f0bbe2SRussell King	};
32b1f0bbe2SRussell King
33b1f0bbe2SRussell King	/* Regulator labels correspond with schematics */
34b1f0bbe2SRussell King	v_3_3: regulator-3-3v {
35b1f0bbe2SRussell King		compatible = "regulator-fixed";
36b1f0bbe2SRussell King		regulator-name = "v_3_3";
37b1f0bbe2SRussell King		regulator-min-microvolt = <3300000>;
38b1f0bbe2SRussell King		regulator-max-microvolt = <3300000>;
39b1f0bbe2SRussell King		regulator-always-on;
40b1f0bbe2SRussell King		status = "okay";
41b1f0bbe2SRussell King	};
42b1f0bbe2SRussell King
43b1f0bbe2SRussell King	v_vddo_h: regulator-1-8v {
44b1f0bbe2SRussell King		compatible = "regulator-fixed";
45b1f0bbe2SRussell King		regulator-name = "v_vddo_h";
46b1f0bbe2SRussell King		regulator-min-microvolt = <1800000>;
47b1f0bbe2SRussell King		regulator-max-microvolt = <1800000>;
48b1f0bbe2SRussell King		regulator-always-on;
49b1f0bbe2SRussell King		status = "okay";
50b1f0bbe2SRussell King	};
51b1f0bbe2SRussell King
52b1f0bbe2SRussell King	v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 {
53b1f0bbe2SRussell King		compatible = "regulator-fixed";
54b1f0bbe2SRussell King		enable-active-high;
55b1f0bbe2SRussell King		gpio = <&cp0_gpio2 15 GPIO_ACTIVE_HIGH>;
56b1f0bbe2SRussell King		pinctrl-names = "default";
57b1f0bbe2SRussell King		pinctrl-0 = <&cp0_xhci_vbus_pins>;
58b1f0bbe2SRussell King		regulator-name = "v_5v0_usb3_hst_vbus";
59b1f0bbe2SRussell King		regulator-min-microvolt = <5000000>;
60b1f0bbe2SRussell King		regulator-max-microvolt = <5000000>;
61b1f0bbe2SRussell King		status = "okay";
62b1f0bbe2SRussell King	};
63b1f0bbe2SRussell King
64b1f0bbe2SRussell King	sfp_eth0: sfp-eth0 {
65b1f0bbe2SRussell King		/* CON15,16 - CPM lane 4 */
66b1f0bbe2SRussell King		compatible = "sff,sfp";
67b1f0bbe2SRussell King		i2c-bus = <&sfpp0_i2c>;
684ce223e5SIoana Ciornei		los-gpios = <&cp1_gpio1 28 GPIO_ACTIVE_HIGH>;
694ce223e5SIoana Ciornei		mod-def0-gpios = <&cp1_gpio1 27 GPIO_ACTIVE_LOW>;
704ce223e5SIoana Ciornei		tx-disable-gpios = <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>;
714ce223e5SIoana Ciornei		tx-fault-gpios = <&cp1_gpio1 26 GPIO_ACTIVE_HIGH>;
72b1f0bbe2SRussell King		pinctrl-names = "default";
73b1f0bbe2SRussell King		pinctrl-0 = <&cp1_sfpp0_pins>;
7405abc6a5SRussell King		maximum-power-milliwatt = <2000>;
75b1f0bbe2SRussell King	};
76b1f0bbe2SRussell King
77b1f0bbe2SRussell King	sfp_eth1: sfp-eth1 {
78b1f0bbe2SRussell King		/* CON17,18 - CPS lane 4 */
79b1f0bbe2SRussell King		compatible = "sff,sfp";
80b1f0bbe2SRussell King		i2c-bus = <&sfpp1_i2c>;
814ce223e5SIoana Ciornei		los-gpios = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>;
824ce223e5SIoana Ciornei		mod-def0-gpios = <&cp1_gpio1 11 GPIO_ACTIVE_LOW>;
834ce223e5SIoana Ciornei		tx-disable-gpios = <&cp1_gpio1 10 GPIO_ACTIVE_HIGH>;
844ce223e5SIoana Ciornei		tx-fault-gpios = <&cp0_gpio2 30 GPIO_ACTIVE_HIGH>;
85b1f0bbe2SRussell King		pinctrl-names = "default";
86b1f0bbe2SRussell King		pinctrl-0 = <&cp1_sfpp1_pins &cp0_sfpp1_pins>;
8705abc6a5SRussell King		maximum-power-milliwatt = <2000>;
88b1f0bbe2SRussell King	};
89b1f0bbe2SRussell King
90b1f0bbe2SRussell King	sfp_eth3: sfp-eth3 {
91b1f0bbe2SRussell King		/* CON13,14 - CPS lane 5 */
92b1f0bbe2SRussell King		compatible = "sff,sfp";
93b1f0bbe2SRussell King		i2c-bus = <&sfp_1g_i2c>;
944ce223e5SIoana Ciornei		los-gpios = <&cp0_gpio2 22 GPIO_ACTIVE_HIGH>;
954ce223e5SIoana Ciornei		mod-def0-gpios = <&cp0_gpio2 21 GPIO_ACTIVE_LOW>;
964ce223e5SIoana Ciornei		tx-disable-gpios = <&cp1_gpio1 24 GPIO_ACTIVE_HIGH>;
974ce223e5SIoana Ciornei		tx-fault-gpios = <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>;
98b1f0bbe2SRussell King		pinctrl-names = "default";
99b1f0bbe2SRussell King		pinctrl-0 = <&cp0_sfp_1g_pins &cp1_sfp_1g_pins>;
10005abc6a5SRussell King		maximum-power-milliwatt = <2000>;
101b1f0bbe2SRussell King	};
102b1f0bbe2SRussell King};
103b1f0bbe2SRussell King
104b1f0bbe2SRussell King&uart0 {
105b1f0bbe2SRussell King	status = "okay";
106b1f0bbe2SRussell King	pinctrl-0 = <&uart0_pins>;
107b1f0bbe2SRussell King	pinctrl-names = "default";
108b1f0bbe2SRussell King};
109b1f0bbe2SRussell King
110b1f0bbe2SRussell King&ap_sdhci0 {
111b1f0bbe2SRussell King	bus-width = <8>;
112b1f0bbe2SRussell King	/*
113b1f0bbe2SRussell King	 * Not stable in HS modes - phy needs "more calibration", so add
114b1f0bbe2SRussell King	 * the "slow-mode" and disable SDR104, SDR50 and DDR50 modes.
115b1f0bbe2SRussell King	 */
116b1f0bbe2SRussell King	marvell,xenon-phy-slow-mode;
117b1f0bbe2SRussell King	no-1-8-v;
118b1f0bbe2SRussell King	no-sd;
119b1f0bbe2SRussell King	no-sdio;
120b1f0bbe2SRussell King	non-removable;
121b1f0bbe2SRussell King	status = "okay";
122b1f0bbe2SRussell King	vqmmc-supply = <&v_vddo_h>;
123b1f0bbe2SRussell King};
124b1f0bbe2SRussell King
125b1f0bbe2SRussell King&cp0_i2c0 {
126b1f0bbe2SRussell King	clock-frequency = <100000>;
127b1f0bbe2SRussell King	pinctrl-names = "default";
128b1f0bbe2SRussell King	pinctrl-0 = <&cp0_i2c0_pins>;
129b1f0bbe2SRussell King	status = "okay";
130b1f0bbe2SRussell King};
131b1f0bbe2SRussell King
132b1f0bbe2SRussell King&cp0_i2c1 {
133b1f0bbe2SRussell King	clock-frequency = <100000>;
134b1f0bbe2SRussell King	pinctrl-names = "default";
135b1f0bbe2SRussell King	pinctrl-0 = <&cp0_i2c1_pins>;
136b1f0bbe2SRussell King	status = "okay";
137b1f0bbe2SRussell King
138*fe96d8b2SGeert Uytterhoeven	i2c-mux@70 {
139b1f0bbe2SRussell King		compatible = "nxp,pca9548";
140b1f0bbe2SRussell King		#address-cells = <1>;
141b1f0bbe2SRussell King		#size-cells = <0>;
142b1f0bbe2SRussell King		reg = <0x70>;
143b1f0bbe2SRussell King
144b1f0bbe2SRussell King		sfpp0_i2c: i2c@0 {
145b1f0bbe2SRussell King			#address-cells = <1>;
146b1f0bbe2SRussell King			#size-cells = <0>;
147b1f0bbe2SRussell King			reg = <0>;
148b1f0bbe2SRussell King		};
149b1f0bbe2SRussell King		sfpp1_i2c: i2c@1 {
150b1f0bbe2SRussell King			#address-cells = <1>;
151b1f0bbe2SRussell King			#size-cells = <0>;
152b1f0bbe2SRussell King			reg = <1>;
153b1f0bbe2SRussell King		};
154b1f0bbe2SRussell King		sfp_1g_i2c: i2c@2 {
155b1f0bbe2SRussell King			#address-cells = <1>;
156b1f0bbe2SRussell King			#size-cells = <0>;
157b1f0bbe2SRussell King			reg = <2>;
158b1f0bbe2SRussell King		};
159b1f0bbe2SRussell King	};
160b1f0bbe2SRussell King};
161b1f0bbe2SRussell King
162b1f0bbe2SRussell King/* J25 UART header */
163b1f0bbe2SRussell King&cp0_uart1 {
164b1f0bbe2SRussell King	pinctrl-names = "default";
165b1f0bbe2SRussell King	pinctrl-0 = <&cp0_uart1_pins>;
166b1f0bbe2SRussell King	status = "okay";
167b1f0bbe2SRussell King};
168b1f0bbe2SRussell King
169b1f0bbe2SRussell King&cp0_mdio {
170b1f0bbe2SRussell King	pinctrl-names = "default";
171b1f0bbe2SRussell King	pinctrl-0 = <&cp0_ge_mdio_pins>;
172b1f0bbe2SRussell King	status = "okay";
173b1f0bbe2SRussell King
174b1f0bbe2SRussell King	ge_phy: ethernet-phy@0 {
175b1f0bbe2SRussell King		reg = <0>;
176b1f0bbe2SRussell King	};
177b1f0bbe2SRussell King};
178b1f0bbe2SRussell King
179b1f0bbe2SRussell King&cp0_pcie0 {
180b1f0bbe2SRussell King	pinctrl-names = "default";
181b1f0bbe2SRussell King	pinctrl-0 = <&cp0_pcie_pins>;
182b1f0bbe2SRussell King	num-lanes = <4>;
183b1f0bbe2SRussell King	num-viewport = <8>;
18459c4dccbSBaruch Siach	reset-gpios = <&cp0_gpio2 20 GPIO_ACTIVE_LOW>;
1851399672eSMiquel Raynal	ranges = <0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>;
186ce55522cSMiquel Raynal	phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>,
187ce55522cSMiquel Raynal	       <&cp0_comphy2 0>, <&cp0_comphy3 0>;
188ce55522cSMiquel Raynal	phy-names = "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy",
189ce55522cSMiquel Raynal		    "cp0-pcie0-x4-lane2-phy", "cp0-pcie0-x4-lane3-phy";
190b1f0bbe2SRussell King	status = "okay";
191b1f0bbe2SRussell King};
192b1f0bbe2SRussell King
193b1f0bbe2SRussell King&cp0_pinctrl {
194b1f0bbe2SRussell King	cp0_ge_mdio_pins: ge-mdio-pins {
195b1f0bbe2SRussell King		marvell,pins = "mpp32", "mpp34";
196b1f0bbe2SRussell King		marvell,function = "ge";
197b1f0bbe2SRussell King	};
198b1f0bbe2SRussell King	cp0_i2c1_pins: i2c1-pins {
199b1f0bbe2SRussell King		marvell,pins = "mpp35", "mpp36";
200b1f0bbe2SRussell King		marvell,function = "i2c1";
201b1f0bbe2SRussell King	};
202b1f0bbe2SRussell King	cp0_i2c0_pins: i2c0-pins {
203b1f0bbe2SRussell King		marvell,pins = "mpp37", "mpp38";
204b1f0bbe2SRussell King		marvell,function = "i2c0";
205b1f0bbe2SRussell King	};
206b1f0bbe2SRussell King	cp0_uart1_pins: uart1-pins {
207b1f0bbe2SRussell King		marvell,pins = "mpp40", "mpp41";
208b1f0bbe2SRussell King		marvell,function = "uart1";
209b1f0bbe2SRussell King	};
210b1f0bbe2SRussell King	cp0_xhci_vbus_pins: xhci0-vbus-pins {
211b1f0bbe2SRussell King		marvell,pins = "mpp47";
212b1f0bbe2SRussell King		marvell,function = "gpio";
213b1f0bbe2SRussell King	};
214b1f0bbe2SRussell King	cp0_sfp_1g_pins: sfp-1g-pins {
215b1f0bbe2SRussell King		marvell,pins = "mpp51", "mpp53", "mpp54";
216b1f0bbe2SRussell King		marvell,function = "gpio";
217b1f0bbe2SRussell King	};
218b1f0bbe2SRussell King	cp0_pcie_pins: pcie-pins {
219b1f0bbe2SRussell King		marvell,pins = "mpp52";
220b1f0bbe2SRussell King		marvell,function = "gpio";
221b1f0bbe2SRussell King	};
222b1f0bbe2SRussell King	cp0_sdhci_pins: sdhci-pins {
223b1f0bbe2SRussell King		marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59",
224b1f0bbe2SRussell King			       "mpp60", "mpp61";
225b1f0bbe2SRussell King		marvell,function = "sdio";
226b1f0bbe2SRussell King	};
227b1f0bbe2SRussell King	cp0_sfpp1_pins: sfpp1-pins {
228b1f0bbe2SRussell King		marvell,pins = "mpp62";
229b1f0bbe2SRussell King		marvell,function = "gpio";
230b1f0bbe2SRussell King	};
231b1f0bbe2SRussell King};
232b1f0bbe2SRussell King
233b1f0bbe2SRussell King&cp0_ethernet {
234b1f0bbe2SRussell King	status = "okay";
235b1f0bbe2SRussell King};
236b1f0bbe2SRussell King
237b1f0bbe2SRussell King&cp0_eth0 {
238b1f0bbe2SRussell King	/* Generic PHY, providing serdes lanes */
239b1f0bbe2SRussell King	phys = <&cp0_comphy4 0>;
240b1f0bbe2SRussell King};
241b1f0bbe2SRussell King
242b1f0bbe2SRussell King&cp0_sata0 {
243b1f0bbe2SRussell King	status = "okay";
244d04abe99SMiquel Raynal
245d04abe99SMiquel Raynal	/* CPM Lane 5 - U29 */
246d04abe99SMiquel Raynal	sata-port@1 {
247d04abe99SMiquel Raynal		phys = <&cp0_comphy5 1>;
248d04abe99SMiquel Raynal		phy-names = "cp0-sata0-1-phy";
249d04abe99SMiquel Raynal	};
250b1f0bbe2SRussell King};
251b1f0bbe2SRussell King
252b1f0bbe2SRussell King&cp0_sdhci0 {
253b1f0bbe2SRussell King	/* U6 */
254b1f0bbe2SRussell King	broken-cd;
255b1f0bbe2SRussell King	bus-width = <4>;
256b1f0bbe2SRussell King	pinctrl-names = "default";
257b1f0bbe2SRussell King	pinctrl-0 = <&cp0_sdhci_pins>;
258b1f0bbe2SRussell King	status = "okay";
259b1f0bbe2SRussell King	vqmmc-supply = <&v_3_3>;
260b1f0bbe2SRussell King};
261b1f0bbe2SRussell King
26299fa8ac5SKonstantin Porotchkin&cp0_utmi {
26399fa8ac5SKonstantin Porotchkin	status = "okay";
26499fa8ac5SKonstantin Porotchkin};
26599fa8ac5SKonstantin Porotchkin
266b1f0bbe2SRussell King&cp0_usb3_0 {
267b1f0bbe2SRussell King	/* J38? - USB2.0 only */
26899fa8ac5SKonstantin Porotchkin	phys = <&cp0_utmi0>;
26999fa8ac5SKonstantin Porotchkin	phy-names = "utmi";
27099fa8ac5SKonstantin Porotchkin	dr_mode = "host";
271b1f0bbe2SRussell King	status = "okay";
272b1f0bbe2SRussell King};
273b1f0bbe2SRussell King
274b1f0bbe2SRussell King&cp0_usb3_1 {
275b1f0bbe2SRussell King	/* J38? - USB2.0 only */
27699fa8ac5SKonstantin Porotchkin	phys = <&cp0_utmi1>;
27799fa8ac5SKonstantin Porotchkin	phy-names = "utmi";
27899fa8ac5SKonstantin Porotchkin	dr_mode = "host";
279b1f0bbe2SRussell King	status = "okay";
280b1f0bbe2SRussell King};
281b1f0bbe2SRussell King
282b1f0bbe2SRussell King&cp1_ethernet {
283b1f0bbe2SRussell King	status = "okay";
284b1f0bbe2SRussell King};
285b1f0bbe2SRussell King
286b1f0bbe2SRussell King&cp1_eth0 {
287b1f0bbe2SRussell King	/* Generic PHY, providing serdes lanes */
288b1f0bbe2SRussell King	phys = <&cp1_comphy4 0>;
289b1f0bbe2SRussell King};
290b1f0bbe2SRussell King
291b1f0bbe2SRussell King&cp1_eth1 {
292b1f0bbe2SRussell King	/* CPS Lane 0 - J5 (Gigabit RJ45) */
293b1f0bbe2SRussell King	status = "okay";
294b1f0bbe2SRussell King	/* Network PHY */
295b1f0bbe2SRussell King	phy = <&ge_phy>;
296b1f0bbe2SRussell King	phy-mode = "sgmii";
297b1f0bbe2SRussell King	/* Generic PHY, providing serdes lanes */
298b1f0bbe2SRussell King	phys = <&cp1_comphy0 1>;
299b1f0bbe2SRussell King};
300b1f0bbe2SRussell King
301b1f0bbe2SRussell King&cp1_eth2 {
302b1f0bbe2SRussell King	/* CPS Lane 5 */
303b1f0bbe2SRussell King	status = "okay";
304b1f0bbe2SRussell King	/* Network PHY */
305b1f0bbe2SRussell King	phy-mode = "2500base-x";
306b1f0bbe2SRussell King	managed = "in-band-status";
307b1f0bbe2SRussell King	/* Generic PHY, providing serdes lanes */
308b1f0bbe2SRussell King	phys = <&cp1_comphy5 2>;
309b1f0bbe2SRussell King	sfp = <&sfp_eth3>;
310b1f0bbe2SRussell King};
311b1f0bbe2SRussell King
312b1f0bbe2SRussell King&cp1_pinctrl {
313b1f0bbe2SRussell King	cp1_sfpp1_pins: sfpp1-pins {
314b1f0bbe2SRussell King		marvell,pins = "mpp8", "mpp10", "mpp11";
315b1f0bbe2SRussell King		marvell,function = "gpio";
316b1f0bbe2SRussell King	};
317b1f0bbe2SRussell King	cp1_spi1_pins: spi1-pins {
318b1f0bbe2SRussell King		marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16";
319b1f0bbe2SRussell King		marvell,function = "spi1";
320b1f0bbe2SRussell King	};
321b1f0bbe2SRussell King	cp1_uart0_pins: uart0-pins {
322b1f0bbe2SRussell King		marvell,pins = "mpp6", "mpp7";
323b1f0bbe2SRussell King		marvell,function = "uart0";
324b1f0bbe2SRussell King	};
325b1f0bbe2SRussell King	cp1_sfp_1g_pins: sfp-1g-pins {
326b1f0bbe2SRussell King		marvell,pins = "mpp24";
327b1f0bbe2SRussell King		marvell,function = "gpio";
328b1f0bbe2SRussell King	};
329b1f0bbe2SRussell King	cp1_sfpp0_pins: sfpp0-pins {
330b1f0bbe2SRussell King		marvell,pins = "mpp26", "mpp27", "mpp28", "mpp29";
331b1f0bbe2SRussell King		marvell,function = "gpio";
332b1f0bbe2SRussell King	};
333b1f0bbe2SRussell King};
334b1f0bbe2SRussell King
335b1f0bbe2SRussell King/* J27 UART header */
336b1f0bbe2SRussell King&cp1_uart0 {
337b1f0bbe2SRussell King	pinctrl-names = "default";
338b1f0bbe2SRussell King	pinctrl-0 = <&cp1_uart0_pins>;
339b1f0bbe2SRussell King	status = "okay";
340b1f0bbe2SRussell King};
341b1f0bbe2SRussell King
342b1f0bbe2SRussell King&cp1_sata0 {
343b1f0bbe2SRussell King	status = "okay";
344d04abe99SMiquel Raynal
345d04abe99SMiquel Raynal	/* CPS Lane 1 - U32 */
346d04abe99SMiquel Raynal	sata-port@0 {
347d04abe99SMiquel Raynal		phys = <&cp1_comphy1 0>;
348d04abe99SMiquel Raynal		phy-names = "cp1-sata0-0-phy";
349d04abe99SMiquel Raynal	};
350d04abe99SMiquel Raynal
351d04abe99SMiquel Raynal	/* CPS Lane 3 - U31 */
352d04abe99SMiquel Raynal	sata-port@1 {
353d04abe99SMiquel Raynal		phys = <&cp1_comphy3 1>;
354d04abe99SMiquel Raynal		phy-names = "cp1-sata0-1-phy";
355d04abe99SMiquel Raynal	};
356b1f0bbe2SRussell King};
357b1f0bbe2SRussell King
358b1f0bbe2SRussell King&cp1_spi1 {
359b1f0bbe2SRussell King	pinctrl-names = "default";
360b1f0bbe2SRussell King	pinctrl-0 = <&cp1_spi1_pins>;
361b1f0bbe2SRussell King	status = "okay";
362b1f0bbe2SRussell King
3632f00bb4aSKrzysztof Kozlowski	flash@0 {
364b1f0bbe2SRussell King		compatible = "st,w25q32";
365b1f0bbe2SRussell King		spi-max-frequency = <50000000>;
366b1f0bbe2SRussell King		reg = <0>;
367b1f0bbe2SRussell King	};
368b1f0bbe2SRussell King};
369b1f0bbe2SRussell King
37096018a6fSMiquel Raynal&cp1_comphy2 {
37196018a6fSMiquel Raynal	cp1_usbh0_con: connector {
37296018a6fSMiquel Raynal		compatible = "usb-a-connector";
37396018a6fSMiquel Raynal		phy-supply = <&v_5v0_usb3_hst_vbus>;
37496018a6fSMiquel Raynal	};
37596018a6fSMiquel Raynal};
37696018a6fSMiquel Raynal
37799fa8ac5SKonstantin Porotchkin&cp1_utmi {
37899fa8ac5SKonstantin Porotchkin	status = "okay";
37999fa8ac5SKonstantin Porotchkin};
38099fa8ac5SKonstantin Porotchkin
381b1f0bbe2SRussell King&cp1_usb3_0 {
382b1f0bbe2SRussell King	/* CPS Lane 2 - CON7 */
38399fa8ac5SKonstantin Porotchkin	phys = <&cp1_comphy2 0>, <&cp1_utmi0>;
38499fa8ac5SKonstantin Porotchkin	phy-names = "cp1-usb3h0-comphy", "utmi";
38599fa8ac5SKonstantin Porotchkin	dr_mode = "host";
386b1f0bbe2SRussell King	status = "okay";
387b1f0bbe2SRussell King};
388