1*d524dac9SGrant LikelyPPC4xx Clock Power Management (CPM) node 2*d524dac9SGrant Likely 3*d524dac9SGrant LikelyRequired properties: 4*d524dac9SGrant Likely - compatible : compatible list, currently only "ibm,cpm" 5*d524dac9SGrant Likely - dcr-access-method : "native" 6*d524dac9SGrant Likely - dcr-reg : < DCR register range > 7*d524dac9SGrant Likely 8*d524dac9SGrant LikelyOptional properties: 9*d524dac9SGrant Likely - er-offset : All 4xx SoCs with a CPM controller have 10*d524dac9SGrant Likely one of two different order for the CPM 11*d524dac9SGrant Likely registers. Some have the CPM registers 12*d524dac9SGrant Likely in the following order (ER,FR,SR). The 13*d524dac9SGrant Likely others have them in the following order 14*d524dac9SGrant Likely (SR,ER,FR). For the second case set 15*d524dac9SGrant Likely er-offset = <1>. 16*d524dac9SGrant Likely - unused-units : specifier consist of one cell. For each 17*d524dac9SGrant Likely bit in the cell, the corresponding bit 18*d524dac9SGrant Likely in CPM will be set to turn off unused 19*d524dac9SGrant Likely devices. 20*d524dac9SGrant Likely - idle-doze : specifier consist of one cell. For each 21*d524dac9SGrant Likely bit in the cell, the corresponding bit 22*d524dac9SGrant Likely in CPM will be set to turn off unused 23*d524dac9SGrant Likely devices. This is usually just CPM[CPU]. 24*d524dac9SGrant Likely - standby : specifier consist of one cell. For each 25*d524dac9SGrant Likely bit in the cell, the corresponding bit 26*d524dac9SGrant Likely in CPM will be set on standby and 27*d524dac9SGrant Likely restored on resume. 28*d524dac9SGrant Likely - suspend : specifier consist of one cell. For each 29*d524dac9SGrant Likely bit in the cell, the corresponding bit 30*d524dac9SGrant Likely in CPM will be set on suspend (mem) and 31*d524dac9SGrant Likely restored on resume. Note, for standby 32*d524dac9SGrant Likely and suspend the corresponding bits can 33*d524dac9SGrant Likely be different or the same. Usually for 34*d524dac9SGrant Likely standby only class 2 and 3 units are set. 35*d524dac9SGrant Likely However, the interface does not care. 36*d524dac9SGrant Likely If they are the same, the additional 37*d524dac9SGrant Likely power saving will be seeing if support 38*d524dac9SGrant Likely is available to put the DDR in self 39*d524dac9SGrant Likely refresh mode and any additional power 40*d524dac9SGrant Likely saving techniques for the specific SoC. 41*d524dac9SGrant Likely 42*d524dac9SGrant LikelyExample: 43*d524dac9SGrant Likely CPM0: cpm { 44*d524dac9SGrant Likely compatible = "ibm,cpm"; 45*d524dac9SGrant Likely dcr-access-method = "native"; 46*d524dac9SGrant Likely dcr-reg = <0x160 0x003>; 47*d524dac9SGrant Likely er-offset = <0>; 48*d524dac9SGrant Likely unused-units = <0x00000100>; 49*d524dac9SGrant Likely idle-doze = <0x02000000>; 50*d524dac9SGrant Likely standby = <0xfeff0000>; 51*d524dac9SGrant Likely suspend = <0xfeff791d>; 52*d524dac9SGrant Likely}; 53