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Searched refs:u_int32_t (Results 1 – 25 of 1013) sorted by relevance

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/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dosprey_reg_map.h87 volatile u_int32_t MAC_DMA_CR; /* 0x8 - 0xc */
89 volatile u_int32_t MAC_DMA_CFG; /* 0x14 - 0x18 */
90 volatile u_int32_t MAC_DMA_RXBUFPTR_THRESH; /* 0x18 - 0x1c */
91 volatile u_int32_t MAC_DMA_TXDPPTR_THRESH; /* 0x1c - 0x20 */
92 volatile u_int32_t MAC_DMA_MIRT; /* 0x20 - 0x24 */
93 volatile u_int32_t MAC_DMA_GLOBAL_IER; /* 0x24 - 0x28 */
94 volatile u_int32_t MAC_DMA_TIMT; /* 0x28 - 0x2c */
95 volatile u_int32_t MAC_DMA_RIMT; /* 0x2c - 0x30 */
96 volatile u_int32_t MAC_DMA_TXCFG; /* 0x30 - 0x34 */
97 volatile u_int32_t MAC_DMA_RXCFG; /* 0x34 - 0x38 */
[all …]
H A Dscorpion_reg_map.h78 volatile u_int32_t MAC_DMA_CR; /* 0x8 - 0xc */
80 volatile u_int32_t MAC_DMA_CFG; /* 0x14 - 0x18 */
81 volatile u_int32_t MAC_DMA_RXBUFPTR_THRESH; /* 0x18 - 0x1c */
82 volatile u_int32_t MAC_DMA_TXDPPTR_THRESH; /* 0x1c - 0x20 */
83 volatile u_int32_t MAC_DMA_MIRT; /* 0x20 - 0x24 */
84 volatile u_int32_t MAC_DMA_GLOBAL_IER; /* 0x24 - 0x28 */
85 volatile u_int32_t MAC_DMA_TIMT; /* 0x28 - 0x2c */
86 volatile u_int32_t MAC_DMA_RIMT; /* 0x2c - 0x30 */
87 volatile u_int32_t MAC_DMA_TXCFG; /* 0x30 - 0x34 */
88 volatile u_int32_t MAC_DMA_RXCFG; /* 0x34 - 0x38 */
[all …]
H A Dscorpion_reg_map_macro.h83 #define MAC_DMA_CR__RXE_LP__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2)
86 ~0x00000004U) | ((u_int32_t)(1) << 2)
89 ~0x00000004U) | ((u_int32_t)(0) << 2)
95 #define MAC_DMA_CR__RXE_HP__READ(src) (((u_int32_t)(src) & 0x00000008U) >> 3)
98 ~0x00000008U) | ((u_int32_t)(1) << 3)
101 ~0x00000008U) | ((u_int32_t)(0) << 3)
107 #define MAC_DMA_CR__RXD__READ(src) (((u_int32_t)(src) & 0x00000020U) >> 5)
108 #define MAC_DMA_CR__RXD__WRITE(src) (((u_int32_t)(src) << 5) & 0x00000020U)
111 ~0x00000020U) | (((u_int32_t)(src) <<\
114 (!((((u_int32_t)(src)\
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H A Dposeidon_reg_map_macro.h91 (u_int32_t)(src)\
94 ((u_int32_t)(src)\
98 ~0x00000001U) | ((u_int32_t)(src) &\
101 (!(((u_int32_t)(src)\
105 ~0x00000001U) | (u_int32_t)(1)
108 ~0x00000001U) | (u_int32_t)(0)
115 (((u_int32_t)(src)\
118 (((u_int32_t)(src)\
122 ~0x00000002U) | (((u_int32_t)(src) <<\
125 (!((((u_int32_t)(src)\
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H A Dosprey_reg_map_macro.h91 #define MAC_DMA_CR__RXE_LP__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2)
94 ~0x00000004U) | ((u_int32_t)(1) << 2)
97 ~0x00000004U) | ((u_int32_t)(0) << 2)
103 #define MAC_DMA_CR__RXE_HP__READ(src) (((u_int32_t)(src) & 0x00000008U) >> 3)
106 ~0x00000008U) | ((u_int32_t)(1) << 3)
109 ~0x00000008U) | ((u_int32_t)(0) << 3)
115 #define MAC_DMA_CR__RXD__READ(src) (((u_int32_t)(src) & 0x00000020U) >> 5)
116 #define MAC_DMA_CR__RXD__WRITE(src) (((u_int32_t)(src) << 5) & 0x00000020U)
119 ~0x00000020U) | (((u_int32_t)(src) <<\
122 (!((((u_int32_t)(src)\
[all …]
H A Dwasp_reg_map.h21 volatile u_int32_t HOST_INTF_RESET_CONTROL; /* 0x4000 - 0x4004 */
22 volatile u_int32_t HOST_INTF_PM_CTRL; /* 0x4004 - 0x4008 */
23 volatile u_int32_t HOST_INTF_TIMEOUT; /* 0x4008 - 0x400c */
24 volatile u_int32_t HOST_INTF_SREV; /* 0x400c - 0x4010 */
25 volatile u_int32_t HOST_INTF_INTR_SYNC_CAUSE; /* 0x4010 - 0x4014 */
26 volatile u_int32_t HOST_INTF_INTR_SYNC_ENABLE; /* 0x4014 - 0x4018 */
27 volatile u_int32_t HOST_INTF_INTR_ASYNC_MASK; /* 0x4018 - 0x401c */
28 volatile u_int32_t HOST_INTF_INTR_SYNC_MASK; /* 0x401c - 0x4020 */
29 volatile u_int32_t HOST_INTF_INTR_ASYNC_CAUSE; /* 0x4020 - 0x4024 */
30 volatile u_int32_t HOST_INTF_INTR_ASYNC_ENABLE; /* 0x4024 - 0x4028 */
[all …]
H A Dar9300.h104 u_int32_t numStepsInLadder;
105 u_int32_t defaultStepNum;
110 u_int32_t currStepNum;
111 u_int32_t currGain;
112 u_int32_t targetGain;
113 u_int32_t loTrig;
114 u_int32_t hiTrig;
115 u_int32_t gainFCorrection;
116 u_int32_t active;
165 u_int32_t listen_time;
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H A Dar9300_freebsd_inc.h99 u_int32_t rp_numpulses ; /* Num of pulses in radar burst */
100 u_int32_t rp_pulsedur; /* Duration of each pulse in usecs */
101 u_int32_t rp_pulsefreq; /* Frequency of pulses in burst */
102 u_int32_t rp_max_pulsefreq; /* Frequency of pulses in burst */
103 u_int32_t rp_patterntype; /* fixed or variable pattern type*/
104 u_int32_t rp_pulsevar; /* Time variation of pulse duration for
106 u_int32_t rp_threshold; /* Threshold for MF output to indicate
108 u_int32_t rp_mindur; /* Min pulse duration to be considered for
110 u_int32_t rp_maxdur; /* Max pusle duration to be considered for
112 u_int32_t rp_rssithresh; /* Minimum rssi to be considered a radar pulse */
[all …]
H A Dar9300desc.h30 u_int32_t ds_info;
31 u_int32_t status1;
32 u_int32_t status2;
33 u_int32_t status3;
34 u_int32_t status4;
35 u_int32_t status5;
36 u_int32_t status6;
37 u_int32_t status7;
38 u_int32_t status8;
42 u_int32_t ds_info;
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/freebsd/sys/sys/
H A Dtiio.h78 volatile u_int32_t dot3StatsAlignmentErrors; /* 0 */
79 volatile u_int32_t dot3StatsFCSErrors; /* 1 */
80 volatile u_int32_t dot3StatsSingleCollisionFrames; /* 2 */
81 volatile u_int32_t dot3StatsMultipleCollisionFrames; /* 3 */
82 volatile u_int32_t dot3StatsSQETestErrors; /* 4 */
83 volatile u_int32_t dot3StatsDeferredTransmissions; /* 5 */
84 volatile u_int32_t dot3StatsLateCollisions; /* 6 */
85 volatile u_int32_t dot3StatsExcessiveCollisions; /* 7 */
86 volatile u_int32_t dot3StatsInternalMacTransmitErrors; /* 8 */
87 volatile u_int32_t dot3StatsCarrierSenseErrors; /* 9 */
[all …]
/freebsd/sys/dev/ath/
H A Dif_athioctl.h39 u_int32_t aggr_pkts[64];
40 u_int32_t aggr_single_pkt;
41 u_int32_t aggr_nonbaw_pkt;
42 u_int32_t aggr_aggr_pkt;
43 u_int32_t aggr_baw_closed_single_pkt;
44 u_int32_t aggr_low_hwq_single_pkt;
45 u_int32_t aggr_sched_nopkt;
46 u_int32_t aggr_rts_aggr_limited;
51 u_int32_t sync_intr[ATH_IOCTL_INTR_NUM_SYNC_INTR];
58 u_int32_t ast_watchdog; /* device reset by watchdog */
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/freebsd/sys/dev/wtap/
H A Dif_wtapioctl.h53 u_int32_t ast_watchdog; /* device reset by watchdog */
54 u_int32_t ast_hardware; /* fatal hardware error interrupts */
55 u_int32_t ast_bmiss; /* beacon miss interrupts */
56 u_int32_t ast_bmiss_phantom;/* beacon miss interrupts */
57 u_int32_t ast_bstuck; /* beacon stuck interrupts */
58 u_int32_t ast_rxorn; /* rx overrun interrupts */
59 u_int32_t ast_rxeol; /* rx eol interrupts */
60 u_int32_t ast_txurn; /* tx underrun interrupts */
61 u_int32_t ast_mib; /* mib interrupts */
62 u_int32_t ast_intrcoal; /* interrupts coalesced */
[all …]
/freebsd/sys/dev/arcmsr/
H A Darcmsr.h189 #define dma_addr_hi32(addr) (u_int32_t) ((addr>>16)>>16)
190 #define dma_addr_lo32(addr) (u_int32_t) (addr & 0xffffffff)
207 u_int32_t HeaderLength;
209 u_int32_t Timeout;
210 u_int32_t ControlCode;
211 u_int32_t ReturnCode;
212 u_int32_t Length;
510 u_int32_t resrved0[4]; /*0000 000F*/
511 u_int32_t inbound_msgaddr0; /*0010 0013*/
512 u_int32_t inbound_msgaddr1; /*0014 0017*/
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/freebsd/sys/dev/pst/
H A Dpst-iop.h38 u_int32_t buf[I2O_IOP_OUTBOUND_FRAME_SIZE];
46 u_int32_t phys_obase;
61 volatile u_int32_t apic_select;
62 volatile u_int32_t reserved0;
63 volatile u_int32_t apic_winreg;
64 volatile u_int32_t reserved1;
65 volatile u_int32_t iqueue_reg0;
66 volatile u_int32_t iqueue_reg1;
67 volatile u_int32_t oqueue_reg0;
68 volatile u_int32_t oqueue_reg1;
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/freebsd/sys/dev/mrsas/
H A Dmrsas.h160 #define le32_to_cpus(x) do { *((u_int32_t *)(x)) = le32toh((*(u_int32_t *)x)); } while (0)
182 u_int32_t regLockLength;
240 u_int32_t regLockLength;
326 u_int32_t Length;
334 u_int32_t FlagsLength;
336 u_int32_t Address32;
344 u_int32_t PrimaryReferenceTag; /* 0x14 */
347 u_int32_t TransferLength; /* 0x1C */
356 u_int32_t Address32;
363 u_int32_t Address;
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/freebsd/sys/dev/aacraid/
H A Daacraid_reg.h56 u_int32_t Size; /* FIB size excluding xport header */
57 u_int32_t Handle; /* driver handle to reference the FIB */
66 u_int32_t Flink;
67 u_int32_t Blink;
75 u_int32_t XferState;
81 u_int32_t SenderFibAddress;
83 u_int32_t ReceiverFibAddress;
84 u_int32_t SenderFibAddressHigh;
85 u_int32_t TimeStamp;
87 u_int32_t Handle;
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/freebsd/sys/dev/hptiop/
H A Dhptiop.h61 u_int32_t resrved0[4];
62 u_int32_t inbound_msgaddr0;
63 u_int32_t inbound_msgaddr1;
64 u_int32_t outbound_msgaddr0;
65 u_int32_t outbound_msgaddr1;
66 u_int32_t inbound_doorbell;
67 u_int32_t inbound_intstatus;
68 u_int32_t inbound_intmask;
69 u_int32_t outbound_doorbell;
70 u_int32_t outbound_intstatus;
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/freebsd/sys/dev/aac/
H A Daacreg.h85 u_int32_t aq_fib_size; /* FIB size in bytes */
86 u_int32_t aq_fib_addr; /* receiver-space address of the FIB */
98 u_int32_t qt_qindex[AAC_QUEUE_COUNT][2];
131 u_int32_t Flink;
132 u_int32_t Blink;
140 u_int32_t XferState;
146 u_int32_t SenderFibAddress;
147 u_int32_t ReceiverFibAddress;
148 u_int32_t SenderData;
151 u_int32_t ReceiverTimeStart;
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/freebsd/contrib/openbsm/bsm/
H A Dlibbsm.h165 u_int32_t port;
166 u_int32_t addr;
171 u_int32_t addr;
175 u_int32_t port;
176 u_int32_t type;
177 u_int32_t addr[4];
182 u_int32_t type;
183 u_int32_t addr[4];
194 u_int32_t val;
228 u_int32_t mode;
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/freebsd/sys/dev/safe/
H A Dsafevar.h58 u_int32_t dma_paddr; /* physical address */
126 u_int32_t ses_klen; /* key length in bits */
127 u_int32_t ses_key[8]; /* DES/3DES/AES key */
128 u_int32_t ses_mlen; /* hmac length in bytes */
129 u_int32_t ses_hminner[5]; /* hmac inner state */
130 u_int32_t ses_hmouter[5]; /* hmac outer state */
176 u_int32_t st_ipackets;
177 u_int32_t st_opackets;
178 u_int32_t st_invalid; /* invalid argument */
179 u_int32_t st_badsession; /* invalid session id */
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/freebsd/sys/x86/include/
H A Dapicreg.h128 u_int32_t id; PAD3;
129 u_int32_t version; PAD3;
134 u_int32_t tpr; PAD3;
135 u_int32_t apr; PAD3;
136 u_int32_t ppr; PAD3;
137 u_int32_t eoi; PAD3;
139 u_int32_t ldr; PAD3;
140 u_int32_t dfr; PAD3;
141 u_int32_t svr; PAD3;
142 u_int32_t isr0; PAD3;
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/freebsd/sys/netinet/
H A Dtcp.h39 typedef u_int32_t tcp_seq;
398 u_int32_t tcpi_rto; /* Retransmission timeout (usec). */
399 u_int32_t __tcpi_ato;
400 u_int32_t tcpi_snd_mss; /* Max segment size for send. */
401 u_int32_t tcpi_rcv_mss; /* Max segment size for receive. */
403 u_int32_t __tcpi_unacked;
404 u_int32_t __tcpi_sacked;
405 u_int32_t __tcpi_lost;
406 u_int32_t __tcpi_retrans;
407 u_int32_t __tcpi_fackets;
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/freebsd/sys/dev/ciss/
H A Dcissreg.h40 u_int32_t target:24; /* SCSI target */
41 u_int32_t bus:6; /* SCSI bus */
42 u_int32_t mode:2; /* CISS_HDR_ADDRESS_MODE_* */
43 u_int32_t extra_address; /* SCSI-3 level-2 and level-3 address bytes */
47 u_int32_t lun:30; /* logical device ID */
48 u_int32_t mode:2; /* CISS_HDR_ADDRESS_MODE_LOGICAL */
49 u_int32_t :32; /* reserved */
53 u_int32_t :30;
54 u_int32_t mode:2;
55 u_int32_t :32;
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/freebsd/sys/i386/i386/
H A Din_cksum_machdep.c138 : "g" (((const u_int32_t *)w)[0]) in in_cksum_skip()
149 : "g" (((const u_int32_t *)w)[0]), in in_cksum_skip()
150 "g" (((const u_int32_t *)w)[1]) in in_cksum_skip()
193 : "g" (((const u_int32_t *)w)[4]), in in_cksum_skip()
194 "g" (((const u_int32_t *)w)[0]), in in_cksum_skip()
195 "g" (((const u_int32_t *)w)[1]), in in_cksum_skip()
196 "g" (((const u_int32_t *)w)[2]), in in_cksum_skip()
197 "g" (((const u_int32_t *)w)[3]), in in_cksum_skip()
198 "g" (((const u_int32_t *)w)[8]), in in_cksum_skip()
199 "g" (((const u_int32_t *)w)[5]), in in_cksum_skip()
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/freebsd/sys/netinet6/
H A Dip6_id.c108 const u_int32_t ru_max; /* Uniq cycle, avoid blackjack prediction */
109 const u_int32_t ru_gen; /* Starting generator */
110 const u_int32_t ru_n; /* ru_n: prime, ru_n - 1: product of pfacts[] */
111 const u_int32_t ru_agen; /* determine ru_a as ru_agen^(2*rand) */
112 const u_int32_t ru_m; /* ru_m = 2^x*3^y */
113 const u_int32_t pfacts[4]; /* factors of ru_n */
115 u_int32_t ru_counter;
116 u_int32_t ru_msb;
118 u_int32_t ru_x;
119 u_int32_t ru_seed, ru_seed2;
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