Lines Matching refs:u_int32_t
39 u_int32_t aggr_pkts[64];
40 u_int32_t aggr_single_pkt;
41 u_int32_t aggr_nonbaw_pkt;
42 u_int32_t aggr_aggr_pkt;
43 u_int32_t aggr_baw_closed_single_pkt;
44 u_int32_t aggr_low_hwq_single_pkt;
45 u_int32_t aggr_sched_nopkt;
46 u_int32_t aggr_rts_aggr_limited;
51 u_int32_t sync_intr[ATH_IOCTL_INTR_NUM_SYNC_INTR];
58 u_int32_t ast_watchdog; /* device reset by watchdog */
59 u_int32_t ast_hardware; /* fatal hardware error interrupts */
60 u_int32_t ast_bmiss; /* beacon miss interrupts */
61 u_int32_t ast_bmiss_phantom;/* beacon miss interrupts */
62 u_int32_t ast_bstuck; /* beacon stuck interrupts */
63 u_int32_t ast_rxorn; /* rx overrun interrupts */
64 u_int32_t ast_rxeol; /* rx eol interrupts */
65 u_int32_t ast_txurn; /* tx underrun interrupts */
66 u_int32_t ast_mib; /* mib interrupts */
67 u_int32_t ast_intrcoal; /* interrupts coalesced */
68 u_int32_t ast_tx_packets; /* packet sent on the interface */
69 u_int32_t ast_tx_mgmt; /* management frames transmitted */
70 u_int32_t ast_tx_discard; /* frames discarded prior to assoc */
71 u_int32_t ast_tx_qstop; /* output stopped 'cuz no buffer */
72 u_int32_t ast_tx_encap; /* tx encapsulation failed */
73 u_int32_t ast_tx_nonode; /* tx failed 'cuz no node */
74 u_int32_t ast_tx_nombuf; /* tx failed 'cuz no mbuf */
75 u_int32_t ast_tx_nomcl; /* tx failed 'cuz no cluster */
76 u_int32_t ast_tx_linear; /* tx linearized to cluster */
77 u_int32_t ast_tx_nodata; /* tx discarded empty frame */
78 u_int32_t ast_tx_busdma; /* tx failed for dma resrcs */
79 u_int32_t ast_tx_xretries;/* tx failed 'cuz too many retries */
80 u_int32_t ast_tx_fifoerr; /* tx failed 'cuz FIFO underrun */
81 u_int32_t ast_tx_filtered;/* tx failed 'cuz xmit filtered */
82 u_int32_t ast_tx_shortretry;/* tx on-chip retries (short) */
83 u_int32_t ast_tx_longretry;/* tx on-chip retries (long) */
84 u_int32_t ast_tx_badrate; /* tx failed 'cuz bogus xmit rate */
85 u_int32_t ast_tx_noack; /* tx frames with no ack marked */
86 u_int32_t ast_tx_rts; /* tx frames with rts enabled */
87 u_int32_t ast_tx_cts; /* tx frames with cts enabled */
88 u_int32_t ast_tx_shortpre;/* tx frames with short preamble */
89 u_int32_t ast_tx_altrate; /* tx frames with alternate rate */
90 u_int32_t ast_tx_protect; /* tx frames with protection */
91 u_int32_t ast_tx_ctsburst;/* tx frames with cts and bursting */
92 u_int32_t ast_tx_ctsext; /* tx frames with cts extension */
93 u_int32_t ast_rx_nombuf; /* rx setup failed 'cuz no mbuf */
94 u_int32_t ast_rx_busdma; /* rx setup failed for dma resrcs */
95 u_int32_t ast_rx_orn; /* rx failed 'cuz of desc overrun */
96 u_int32_t ast_rx_crcerr; /* rx failed 'cuz of bad CRC */
97 u_int32_t ast_rx_fifoerr; /* rx failed 'cuz of FIFO overrun */
98 u_int32_t ast_rx_badcrypt;/* rx failed 'cuz decryption */
99 u_int32_t ast_rx_badmic; /* rx failed 'cuz MIC failure */
100 u_int32_t ast_rx_phyerr; /* rx failed 'cuz of PHY err */
101 u_int32_t ast_rx_phy[ATH_IOCTL_STATS_NUM_RX_PHYERR];
103 u_int32_t ast_rx_tooshort;/* rx discarded 'cuz frame too short */
104 u_int32_t ast_rx_toobig; /* rx discarded 'cuz frame too large */
105 u_int32_t ast_rx_packets; /* packet recv on the interface */
106 u_int32_t ast_rx_mgt; /* management frames received */
107 u_int32_t ast_rx_ctl; /* rx discarded 'cuz ctl frame */
111 u_int32_t ast_be_xmit; /* beacons transmitted */
112 u_int32_t ast_be_nombuf; /* beacon setup failed 'cuz no mbuf */
113 u_int32_t ast_per_cal; /* periodic calibration calls */
114 u_int32_t ast_per_calfail;/* periodic calibration failed */
115 u_int32_t ast_per_rfgain; /* periodic calibration rfgain reset */
116 u_int32_t ast_rate_calls; /* rate control checks */
117 u_int32_t ast_rate_raise; /* rate control raised xmit rate */
118 u_int32_t ast_rate_drop; /* rate control dropped xmit rate */
119 u_int32_t ast_ant_defswitch;/* rx/default antenna switches */
120 u_int32_t ast_ant_txswitch;/* tx antenna switches */
121 u_int32_t ast_ant_rx[ATH_IOCTL_STATS_NUM_RX_ANTENNA];
123 u_int32_t ast_ant_tx[ATH_IOCTL_STATS_NUM_TX_ANTENNA];
125 u_int32_t ast_cabq_xmit; /* cabq frames transmitted */
126 u_int32_t ast_cabq_busy; /* cabq found busy */
127 u_int32_t ast_tx_raw; /* tx frames through raw api */
128 u_int32_t ast_ff_txok; /* fast frames tx'd successfully */
129 u_int32_t ast_ff_txerr; /* fast frames tx'd w/ error */
130 u_int32_t ast_ff_rx; /* fast frames rx'd */
131 u_int32_t ast_ff_flush; /* fast frames flushed from staging q */
132 u_int32_t ast_tx_qfull; /* tx dropped 'cuz of queue limit */
134 u_int32_t ast_tx_nobuf; /* tx dropped 'cuz no ath buffer */
135 u_int32_t ast_tdma_update;/* TDMA slot timing updates */
136 u_int32_t ast_tdma_timers;/* TDMA slot update set beacon timers */
137 u_int32_t ast_tdma_tsf; /* TDMA slot update set TSF */
140 u_int32_t ast_tdma_ack; /* TDMA tx failed 'cuz ACK required */
141 u_int32_t ast_tx_raw_fail;/* raw tx failed 'cuz h/w down */
142 u_int32_t ast_tx_nofrag; /* tx dropped 'cuz no ath frag buffer */
143 u_int32_t ast_be_missed; /* missed beacons */
144 u_int32_t ast_ani_cal; /* ANI calibrations performed */
145 u_int32_t ast_rx_agg; /* number of aggregate frames RX'ed */
146 u_int32_t ast_rx_halfgi; /* RX half-GI */
147 u_int32_t ast_rx_2040; /* RX 40mhz frame */
148 u_int32_t ast_rx_pre_crc_err; /* RX pre-delimiter CRC error */
149 u_int32_t ast_rx_post_crc_err; /* RX post-delimiter CRC error */
150 u_int32_t ast_rx_decrypt_busy_err; /* RX decrypt engine busy error */
151 u_int32_t ast_rx_hi_rx_chain;
152 u_int32_t ast_tx_htprotect; /* HT tx frames with protection */
153 u_int32_t ast_rx_hitqueueend; /* RX hit descr queue end */
154 u_int32_t ast_tx_timeout; /* Global TX timeout */
155 u_int32_t ast_tx_cst; /* Carrier sense timeout */
156 u_int32_t ast_tx_xtxop; /* tx exceeded TXOP */
157 u_int32_t ast_tx_timerexpired; /* tx exceeded TX_TIMER */
158 u_int32_t ast_tx_desccfgerr; /* tx desc cfg error */
159 u_int32_t ast_tx_swretries; /* software TX retries */
160 u_int32_t ast_tx_swretrymax; /* software TX retry max limit reach */
161 u_int32_t ast_tx_data_underrun;
162 u_int32_t ast_tx_delim_underrun;
163 u_int32_t ast_tx_aggr_failall; /* aggregate TX failed in its entirety */
164 u_int32_t ast_tx_getnobuf;
165 u_int32_t ast_tx_getbusybuf;
166 u_int32_t ast_tx_intr;
167 u_int32_t ast_rx_intr;
168 u_int32_t ast_tx_aggr_ok; /* aggregate TX ok */
169 u_int32_t ast_tx_aggr_fail; /* aggregate TX failed */
170 u_int32_t ast_tx_mcastq_overflow; /* multicast queue overflow */
171 u_int32_t ast_rx_keymiss;
172 u_int32_t ast_tx_swfiltered;
173 u_int32_t ast_tx_node_psq_overflow;
174 u_int32_t ast_rx_stbc; /* RX STBC frame */
175 u_int32_t ast_tx_nodeq_overflow; /* node sw queue overflow */
176 u_int32_t ast_tx_ldpc; /* TX LDPC frame */
177 u_int32_t ast_tx_stbc; /* TX STBC frame */
178 u_int32_t ast_tsfoor; /* TSFOOR interrupts */
179 u_int32_t ast_pad[10];
357 u_int32_t wr_chan_flags;
397 u_int32_t wt_chan_flags;