Lines Matching refs:u_int32_t
61 u_int32_t resrved0[4];
62 u_int32_t inbound_msgaddr0;
63 u_int32_t inbound_msgaddr1;
64 u_int32_t outbound_msgaddr0;
65 u_int32_t outbound_msgaddr1;
66 u_int32_t inbound_doorbell;
67 u_int32_t inbound_intstatus;
68 u_int32_t inbound_intmask;
69 u_int32_t outbound_doorbell;
70 u_int32_t outbound_intstatus;
71 u_int32_t outbound_intmask;
72 u_int32_t reserved1[2];
73 u_int32_t inbound_queue;
74 u_int32_t outbound_queue;
99 u_int32_t inbound_head;
100 u_int32_t inbound_tail;
101 u_int32_t outbound_head;
102 u_int32_t outbound_tail;
103 u_int32_t inbound_msg;
104 u_int32_t outbound_msg;
105 u_int32_t reserve[10];
111 u_int32_t reserved[0x20400 / 4];
112 u_int32_t inbound_doorbell;
113 u_int32_t inbound_intmask;
114 u_int32_t outbound_doorbell;
115 u_int32_t outbound_intmask;
123 u_int32_t reserved[0x4000 / 4];
126 u_int32_t inbound_base; /* 0x4000 : 0 */
127 u_int32_t inbound_base_high; /* 4 */
128 u_int32_t reserved2[(0x18 - 8)/ 4];
129 u_int32_t inbound_write_ptr; /* 0x18 */
130 u_int32_t inbound_read_ptr; /* 0x1c */
131 u_int32_t reserved3[(0x2c - 0x20) / 4];
132 u_int32_t inbound_conf_ctl; /* 0x2c */
133 u_int32_t reserved4[(0x50 - 0x30) / 4];
134 u_int32_t outbound_base; /* 0x50 */
135 u_int32_t outbound_base_high; /* 0x54 */
136 u_int32_t outbound_shadow_base; /* 0x58 */
137 u_int32_t outbound_shadow_base_high; /* 0x5c */
138 u_int32_t reserved5[(0x68 - 0x60) / 4];
139 u_int32_t outbound_write; /* 0x68 */
140 u_int32_t reserved6[(0x70 - 0x6c) / 4];
141 u_int32_t outbound_read; /* 0x70 */
142 u_int32_t reserved7[(0x88 - 0x74) / 4];
143 u_int32_t isr_cause; /* 0x88 */
144 u_int32_t isr_enable; /* 0x8c */
146 u_int32_t reserved8[(0x10200 - 0x4090) / 4];
149 u_int32_t main_int_cuase; /* 0x10200: 0 */
150 u_int32_t main_irq_enable; /* 4 */
151 u_int32_t main_fiq_enable; /* 8 */
152 u_int32_t pcie_f0_int_enable; /* 0xc */
153 u_int32_t pcie_f1_int_enable; /* 0x10 */
154 u_int32_t pcie_f2_int_enable; /* 0x14 */
155 u_int32_t pcie_f3_int_enable; /* 0x18 */
157 u_int32_t reserved9[(0x10400 - 0x1021c) / 4];
160 u_int32_t f0_to_cpu_msg_a; /* 0x10400: 0 */
161 u_int32_t reserved10[(0x20 - 4) / 4];
162 u_int32_t cpu_to_f0_msg_a; /* 0x20 */
163 u_int32_t reserved11[(0x80 - 0x24) / 4];
164 u_int32_t f0_doorbell; /* 0x80 */
165 u_int32_t f0_doorbell_enable; /* 0x84 */
170 u_int32_t intrfc_len;
171 u_int32_t reserved;
175 u_int32_t val;
251 u_int32_t size;
252 u_int32_t type;
253 u_int32_t flags;
254 u_int32_t result;
260 u_int32_t interface_version;
261 u_int32_t firmware_version;
262 u_int32_t max_requests;
263 u_int32_t request_size;
264 u_int32_t max_sg_count;
265 u_int32_t data_transfer_length;
266 u_int32_t alignment_mask;
267 u_int32_t max_devices;
268 u_int32_t sdram_size;
273 u_int32_t iop_id;
276 u_int32_t reserve[6];
280 u_int32_t size;
281 u_int32_t eot; /* non-zero: end of table */
309 u_int32_t dataxfer_length;
315 u_int32_t ioctl_code;
316 u_int32_t inbuf_size;
317 u_int32_t outbuf_size;
318 u_int32_t bytes_returned;
324 u_int32_t Magic; /* used to check if it's a valid ioctl packet */
325 u_int32_t dwIoControlCode; /* operation control code */
327 u_int32_t nInBufferSize; /* size of input data buffer */
329 u_int32_t nOutBufferSize; /* size of output data buffer */
358 u_int32_t inlist_wptr;
361 u_int32_t *outlist_cptr; /* copy pointer shadow */
363 u_int32_t outlist_rptr;
369 u_int32_t firmware_version;
370 u_int32_t interface_version;
371 u_int32_t max_devices;
372 u_int32_t max_requests;
373 u_int32_t max_request_size;
374 u_int32_t max_sg_count;
376 u_int32_t msg_done;
379 u_int32_t pciunit;
413 u_int32_t config_done; /* can be negative value */
414 u_int32_t initialized:1;
422 u_int32_t flag;
436 int (*iop_wait_ready)(struct hpt_iop_hba *hba, u_int32_t millisec);
448 void (*post_msg)(struct hpt_iop_hba *hba, u_int32_t msg);
461 u_int32_t srb_flag;