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/freebsd/contrib/llvm-project/clang/lib/Headers/
H A Damxintrin.h153 #define _tile_dpbssd(dst, src0, src1) \ argument
154 __builtin_ia32_tdpbssd((dst), (src0), (src1))
172 #define _tile_dpbsud(dst, src0, src1) \ argument
173 __builtin_ia32_tdpbsud((dst), (src0), (src1))
191 #define _tile_dpbusd(dst, src0, src1) \ argument
192 __builtin_ia32_tdpbusd((dst), (src0), (src1))
210 #define _tile_dpbuud(dst, src0, src1) \ argument
211 __builtin_ia32_tdpbuud((dst), (src0), (src1))
228 #define _tile_dpbf16ps(dst, src0, src1) \ argument
229 __builtin_ia32_tdpbf16ps((dst), (src0), (src1))
[all …]
H A Damxcomplexintrin.h139 static void __tile_cmmimfp16ps(__tile1024i *dst, __tile1024i src0, in __tile_cmmimfp16ps() argument
141 dst->tile = _tile_cmmimfp16ps_internal(src0.row, src1.col, src0.col, in __tile_cmmimfp16ps()
142 dst->tile, src0.tile, src1.tile); in __tile_cmmimfp16ps()
162 static void __tile_cmmrlfp16ps(__tile1024i *dst, __tile1024i src0, in __tile_cmmrlfp16ps() argument
164 dst->tile = _tile_cmmrlfp16ps_internal(src0.row, src1.col, src0.col, in __tile_cmmrlfp16ps()
165 dst->tile, src0.tile, src1.tile); in __tile_cmmrlfp16ps()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstrInfo.td208 // out = (src0 + src1 > 0xFFFFFFFF) ? 1 : 0
211 // out = (src1 > src0) ? 1 : 0
247 // Special case divide FMA with scale and flags (src0 = Quotient,
253 // Special case divide fixup and flags(src0 = Quotient, src1 =
272 // src0: vec4(src, 0, 0, mask)
349 // i32 or f32 src0
422 def AMDGPUfp_class : PatFrags<(ops node:$src0, node:$src1),
423 [(int_amdgcn_class node:$src0, node:$src1),
424 (AMDGPUfp_class_impl node:$src0, node:$src1)]>;
426 def AMDGPUfmed3 : PatFrags<(ops node:$src0, node:$src1, node:$src2),
[all …]
H A DAMDGPUInstructions.td172 (ops node:$src0),
173 (op $src0)> {
178 (ops node:$src0, node:$src1),
179 (op $src0, $src1)> {
184 (ops node:$src0, node:$src1, node:$src2),
185 (op $src0, $src1, $src2)> {
190 (ops node:$src0),
191 (op $src0),
208 (ops node:$src0, node:$src1),
209 (op $src0, $src1),
[all …]
H A DSIInstructions.td69 let DisableEncoding = "$src0", Constraints = "$src0 = $vdst" in {
74 (ins VGPR_32:$src0, VGPR_32:$vsrc, InterpAttr:$attr,
77 [(set f32:$vdst, (int_amdgcn_interp_p2 f32:$src0, f32:$vsrc,
80 } // End DisableEncoding = "$src0", Constraints = "$src0 = $vdst"
124 (ins VSrc_b64:$src0, VSrc_b64:$src1, SSrc_b64:$src2), "", []> {
133 (ins VSrc_b64:$src0)> {
150 (ins i64imm:$src0)> {
162 def WQM : PseudoInstSI <(outs unknown:$vdst), (ins unknown:$src0)>;
166 def SOFT_WQM : PseudoInstSI <(outs unknown:$vdst), (ins unknown:$src0)>;
170 // the instruction that defines $src0 (which is run in Whole Wave Mode) doesn't
[all …]
H A DSOPInstructions.td73 bits<8> src0;
75 let Inst{7-0} = !if(ps.has_src0, src0, ?);
83 !if(tied_in, (ins SSrc_b32:$src0, SReg_32:$sdst_in),
84 (ins SSrc_b32:$src0)),
85 "$sdst, $src0", pattern> {
91 opName, (outs SReg_32:$sdst), (ins SReg_32:$src0),
92 "$sdst, $src0", pattern>;
96 opName, (outs), (ins SSrc_b32:$src0),
97 "$src0", pattern> {
103 opName, (outs), (ins SReg_32:$sdst, SSrc_b32:$src0),
[all …]
H A DEvergreenInstructions.td348 // [(set f64:$dst, (fma f64:$src0, f64:$src1, f64:$src2))]
366 [(set i32:$dst, (AMDGPUbfe_u32 i32:$src0, i32:$src1, i32:$src2))],
371 [(set i32:$dst, (AMDGPUbfe_i32 i32:$src0, i32:$src1, i32:$src2))],
412 [(set i32:$dst, (AMDGPUbfi i32:$src0, i32:$src1, i32:$src2))],
464 (fcopysign f32:$src0, f32:$src1),
465 (BFI_INT_eg (MOV_IMM_I32 (i32 0x7fffffff)), $src0, $src1)
469 (fcopysign f32:$src0, f64:$src1),
470 (BFI_INT_eg (MOV_IMM_I32 (i32 0x7fffffff)), $src0,
475 (fcopysign f64:$src0, f64:$src1),
477 (i32 (EXTRACT_SUBREG $src0, sub0)), sub0,
[all …]
H A DR600Instructions.td105 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
110 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
136 [(set R600_Reg32:$dst, (node R600_Reg32:$src0))], itin
147 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
153 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
175 [(set R600_Reg32:$dst, (node R600_Reg32:$src0,
187 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, SEL:$src0_sel,
193 "$src0_neg$src0$src0_rel, "
372 (ins i32imm:$src0, R600_TReg32_Y:$src1, R600_TReg32_X:$src2),
373 "INTERP_PAIR_XY $src0
[all...]
H A DVOP3Instructions.td40 let Asm64 = "$vdst, $sdst, $src0, $src1, $src2$clamp";
65 let Ins64 = (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
73 let Ins64 = (ins InterpSlot:$src0,
77 let Asm64 = "$vdst, $src0, $attr$attrchan$clamp$omod";
94 (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
98 (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
103 (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
183 // result = src0 * src1 + src2
190 // result = src0 * src1 + src2
361 (VOP3Mods f32:$src0, i32:$src0_modifiers),
[all …]
H A DVOPInstructions.td226 bits<9> src0;
239 let Inst{40-32} = !if(P.HasSrc0, src0, 0);
318 // NB: For V_INTERP* opcodes, src0 is encoded as src1 and vice versa
324 let Inst{8} = 0; // No modifiers for src0
334 let Inst{49-41} = src0;
347 let Inst{49-41} = src0;
357 bits<9> src0;
368 let Inst{40-32} = !if(P.HasSrc0, src0, 0);
380 bits<9> src0;
390 let Inst{8} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); // neg_hi src0
[all …]
H A DVOP2Instructions.td15 bits<9> src0;
18 let Inst{8-0} = !if(P.HasSrc0, src0, 0);
27 bits<9> src0;
31 let Inst{8-0} = !if(P.HasSrc0, src0, 0);
135 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod),
136 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))),
138 [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]);
282 (inst ps.Pfl.DstRC:$vdst, ps.Pfl.Src0RC32:$src0,
345 (inst ps.Pfl.DstRC:$vdst, ps.Pfl.Src0RC32:$src0,
353 ps.Pfl.Src0RC32:$src0, ps.Pfl.Src1RC32:$src1, Clamp:$clamp),
[all …]
H A DEXPInstructions.td16 ExpSrc0:$src0, ExpSrc1:$src1, ExpSrc2:$src2, ExpSrc3:$src3,
41 : EXPCommon<0, ps.done, "exp$tgt $src0, $src1, $src2, $src3"
49 : EXPCommon<ps.row, ps.done, name#"$tgt $src0, $src1, $src2, $src3"
142 (vt ExpSrc0:$src0), (vt ExpSrc1:$src1),
145 (Inst timm:$tgt, ExpSrc0:$src0, ExpSrc1:$src1,
151 (vt ExpSrc0:$src0), (vt ExpSrc1:$src1),
154 (Inst timm:$tgt, ExpSrc0:$src0, ExpSrc1:$src1,
160 (vt ExpSrc0:$src0), (vt ExpSrc1:$src1),
162 (Inst timm:$tgt, ExpSrc0:$src0, ExpSrc1:$src1,
H A DVINTERPInstructions.td16 bits<9> src0;
34 let Inst{40-32} = src0;
77 let Ins64 = (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
95 let Ins64 = (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
130 (VINTERPMods f32:$src0, i32:$src0_modifiers),
133 (inst $src0_modifiers, $src0,
149 (pat[0] f32:$src0, i32:$src0_modifiers),
153 (inst $src0_modifiers, $src0,
H A DAMDGPUGISel.td309 (dst_vt (node (src0_vt SReg_32:$src0), (src1_vt SReg_32:$src1))),
310 (inst src0_vt:$src0, src1_vt:$src1)
319 (dst_vt (node (src0_vt (sd_vsrc0 src0_vt:$src0)), (src1_vt VGPR_32:$src1))),
320 (inst src0_vt:$src0, src1_vt:$src1)
329 (dst_vt (node (src1_vt VGPR_32:$src1), (src0_vt (sd_vsrc0 src0_vt:$src0)))),
330 (inst src0_vt:$src0, src1_vt:$src1)
339 (dst_vt (node (src0_vt (sd_vcsrc src0_vt:$src0)), (src1_vt (sd_vcsrc src1_vt:$src1)))),
340 (inst src0_vt:$src0, src1_vt:$src1)
349 (dst_vt (node (src0_vt (sd_vcsrc src0_vt:$src0)), (src1_vt (sd_vcsrc src1_vt:$src1)))),
350 (inst src0_vt:$src1, src1_vt:$src0)
[all …]
H A DVOP3PInstructions.td33 (ins FP16InputMods:$src0_modifiers, VCSrc_f16:$src0,
37 (ins FPVRegInputMods:$src0_modifiers, VGPRSrc_32:$src0,
130 (pat (v2i16 (VOP3PMods v2i16:$src0, i32:$src0_modifiers)),
132 (inst $src0_modifiers, $src0, $src1_modifiers, $src1, DSTCLAMP.ENABLE)
151 (f32 (fma_like (f32 (VOP3PMadMixModsExt f16:$src0, i32:$src0_mods)),
154 (mix_inst $src0_mods, $src0, $src1_mods, $src1, $src2_mods, $src2,
157 (f32 (fma_like (f32 (VOP3PMadMixMods f16:$src0, i32:$src0_mods)),
160 (mix_inst $src0_mods, $src0, $src1_mods, $src1, $src2_mods, $src2,
163 (f32 (fma_like (f32 (VOP3PMadMixMods f16:$src0, i32:$src0_mods)),
166 (mix_inst $src0_mods, $src0, $src1_mods, $src1, $src2_mods, $src2,
[all …]
H A DSIInstrInfo.td667 (ops node:$src1, node:$src0),
668 (srl $src0, $src1)
672 (ops node:$src1, node:$src0),
673 (sra $src0, $src1)
677 (ops node:$src1, node:$src0),
678 (shl $src0, $src1)
682 (ops node:$src0, node:$src1),
683 (add (ctpop $src0), $src1)
687 (ops node:$src0, node:$src1),
688 (not (xor $src0, $src1))
[all …]
H A DVOP1Instructions.td16 bits<9> src0;
18 let Inst{8-0} = !if(P.HasSrc0, src0{8-0}, ?);
111 [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3Mods P.Src0VT:$src0, i32:$src0_modifiers))))],
113 [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3OMods P.Src0VT:$src0,
115 [(set P.DstVT:$vdst, (node (P.Src0VT P.Src0RC32:$src0)))]
181 let Ins64 = (ins Src0RC64:$src0, Clamp:$clamp, omod:$omod);
182 let InsVOP3Base = (ins Src0VOP3DPP:$src0, Clamp:$clamp, omod:$omod);
183 let AsmVOP3Base = "$vdst, $src0$clamp$omod";
192 let Ins64 = (ins Src0RC64:$src0, Clamp:$clamp, omod:$omod);
193 let InsVOP3Base = (ins Src0VOP3DPP:$src0, Clamp:$clamp, omod:$omod);
[all …]
H A DSIPeepholeSDWA.cpp316 if (TII->getNamedOperand(*MI, AMDGPU::OpName::src0) == SrcOp) { in getSrcMods()
386 MachineOperand *Src = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in convertToSDWA()
582 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in matchSDWAOperand()
622 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in matchSDWAOperand()
689 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in matchSDWAOperand()
706 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in matchSDWAOperand()
762 MachineOperand *OrSDWA = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in matchSDWAOperand()
768 OrOther = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in matchSDWAOperand()
943 .add(*TII->getNamedOperand(MI, AMDGPU::OpName::src0)) in pseudoOpConvertToVOP2()
1005 if (MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0)) { in isConvertibleToSDWA()
[all …]
H A DVOPCInstructions.td14 bits<9> src0;
17 let Inst{8-0} = src0;
54 let Asm32 = "$src0, $src1";
59 "$src0, $src1 $dpp_ctrl$row_mask$bank_mask$bound_ctrl");
60 let AsmDPP8 = "$src0, $src1 $dpp8$fi";
108 let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
112 "$src0, $src1");
206 (inst p.DstRC:$sdst, p.Src0RC32:$src0),
209 (inst p.DstRC:$sdst, p.Src0RC32:$src0, p.Src1RC32:$src1),
215 (inst p.Src0RC32:$src0, p.Src1RC32:$src1),
[all …]
H A DCaymanInstructions.td23 [(set i32:$dst, (AMDGPUmad_i24 i32:$src0, i32:$src1, i32:$src2))], VecALU
26 [(set i32:$dst, (AMDGPUmul_i24 i32:$src0, i32:$src1))], VecALU
61 (AMDGPUurecip i32:$src0),
62 (FLT_TO_UINT_eg (MUL_IEEE (RECIP_IEEE_cm (UINT_TO_FLT_eg $src0)),
/freebsd/crypto/openssl/crypto/ec/asm/
H A Decp_nistz256-x86_64.pl3060 my ($a,$b,$src0) = @_;
3061 my $bias = $src0 eq "%rax" ? 0 : -128;
3063 " mov $b, $src0
3073 my ($a,$src0) = @_;
3074 my $bias = $src0 eq "%rax" ? 0 : -128;
3076 " mov 8*0+$a, $src0
3223 my ($src0,$sfx,$bias);
3227 $src0 = "%rax";
3245 $src0 = "%rdx";
3295 mov 0x40+8*0($a_ptr), $src0
[all …]
/freebsd/lib/libc/string/
H A Dbcopy.c59 (void *dst0, const void *src0, size_t length) in memcpy() argument
66 bcopy(const void *src0, void *dst0, size_t length) in memcpy()
70 const char *src = src0; in memcpy()
/freebsd/sys/libkern/
H A Dbcopy.c60 memcpy(void *dst0, const void *src0, size_t length) in memcpy() argument
67 src = src0; in memcpy()
/freebsd/sys/cddl/dev/kinst/
H A Dkinst.c81 volatile const unsigned char *src0; in kinst_memcpy() local
84 src0 = src; in kinst_memcpy()
88 *dst0++ = *src0++; in kinst_memcpy()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXIntrinsics.td610 : NVPTXInst<(outs target_regclass:$dst), (ins src_regclass:$src0),
612 [(set target_regclass:$dst, (IntOP src_regclass:$src0))]>,
621 (ins s0_regclass:$src0, s1_regclass:$src1),
623 [(set t_regclass:$dst, (IntOP s0_regclass:$src0, s1_regclass:$src1))]>,
630 (ins s0_regclass:$src0, s1_regclass:$src1, s2_regclass:$src2),
633 (IntOP s0_regclass:$src0, s1_regclass:$src1, s2_regclass:$src2))]>,
640 def INT_NVVM_PRMT : F_MATH_3<"prmt.b32 \t$dst, $src0, $src1, $src2;", Int32Regs,
653 def INT_NVVM_FMIN_F : F_MATH_2<"min.f32 \t$dst, $src0, $src1;", Float32Regs,
655 def INT_NVVM_FMIN_FTZ_F : F_MATH_2<"min.ftz.f32 \t$dst, $src0, $src1;",
657 def INT_NVVM_FMIN_NAN_F : F_MATH_2<"min.NaN.f32 \t$dst, $src0, $src1;",
[all …]

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