Lines Matching refs:src0
16 bits<9> src0;
18 let Inst{8-0} = !if(P.HasSrc0, src0{8-0}, ?);
111 [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3Mods P.Src0VT:$src0, i32:$src0_modifiers))))],
113 [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3OMods P.Src0VT:$src0,
115 [(set P.DstVT:$vdst, (node (P.Src0VT P.Src0RC32:$src0)))]
181 let Ins64 = (ins Src0RC64:$src0, Clamp:$clamp, omod:$omod);
182 let InsVOP3Base = (ins Src0VOP3DPP:$src0, Clamp:$clamp, omod:$omod);
183 let AsmVOP3Base = "$vdst, $src0$clamp$omod";
192 let Ins64 = (ins Src0RC64:$src0, Clamp:$clamp, omod:$omod);
193 let InsVOP3Base = (ins Src0VOP3DPP:$src0, Clamp:$clamp, omod:$omod);
194 let AsmVOP3Base = "$vdst, $src0$clamp$omod";
246 let Asm32 = " $vdst, $src0";
258 def : GCNPat<(vt (int_amdgcn_readfirstlane (vt VRegOrLdsSrc_32:$src0))),
259 (V_READFIRSTLANE_B32 (vt VRegOrLdsSrc_32:$src0))
367 // Restrict src0 to be VGPR
383 let Ins32 = (ins Src0RC32:$vdst, Src1RC:$src0);
384 let Ins64 = (ins Src0RC64:$vdst, Src1RC:$src0);
388 let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
394 let InsDPP16 = (ins Src0RC32:$old, Src0RC32:$src0,
398 let InsDPP8 = (ins Src0RC32:$old, Src0RC32:$src0, dpp8:$dpp8, Dpp8FI:$fi);
540 let Ins32 = (ins VRegSrc_32:$src0, VGPR_32:$src1);
541 let Asm32 = " $vdst, $src0";
546 let Constraints = "$vdst = $src1, $vdst1 = $src0";
577 let InsSDWA = (ins Bin32SDWAInputMods:$src0_modifiers, Src0SDWA:$src0,
677 (node i32:$src0, timm:$byte_sel),
678 (inst $src0, (as_i32timm $byte_sel))
711 let Constraints = "$vdst = $src1, $vdst1 = $src0";
723 let Asm32 = " $vdst, $src0";
733 // Restrict src0 to be VGPR
746 def : GCNPat<(int_amdgcn_permlane64 (vt VRegSrc_32:$src0)),
747 (vt (V_PERMLANE64_B32 (vt VRegSrc_32:$src0)))
1347 (ins getVALUDstForVT<i32>.ret:$vdst, getVOPSrc0ForVT<i32, 0>.ret:$src0)>,
1349 getVOPSrc0ForVT<i32, 0>.ret:$src0)>;
1355 (ins getVOPSrc0ForVT<i32, 0>.ret:$src0)>,
1357 getVOPSrc0ForVT<i32, 0>.ret:$src0)>;