Lines Matching refs:src0
226 bits<9> src0;
239 let Inst{40-32} = !if(P.HasSrc0, src0, 0);
318 // NB: For V_INTERP* opcodes, src0 is encoded as src1 and vice versa
324 let Inst{8} = 0; // No modifiers for src0
334 let Inst{49-41} = src0;
347 let Inst{49-41} = src0;
357 bits<9> src0;
368 let Inst{40-32} = !if(P.HasSrc0, src0, 0);
380 bits<9> src0;
390 let Inst{8} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); // neg_hi src0
404 let Inst{40-32} = !if(P.HasSrc0, src0, 0);
416 bits<10> src0;
432 let Inst{40-32} = !if(P.HasSrc0, src0{8-0}, 0);
436 let Inst{59} = !if(P.HasSrc0, src0{9}, 0); // acc(0)
444 bits<10> src0;
462 let Inst{40-32} = src0{8-0};
466 let Inst{59} = src0{9}; // acc(0)
514 bits<8> src0;
523 let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0);
550 bits<9> src0; // {src0_sgpr{0}, src0{7-0}}
557 let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0);
561 let Inst{55} = !if(P.HasSrc0, src0{8}, 0);
709 bits<8> src0;
717 let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0);
737 bits<8> src0;
787 let Inst{8} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); // neg_hi src0
941 let Inst{71-64} = !if(P.HasSrc0, src0{7-0}, 0);
960 let Inst{71-64} = !if(P.HasSrc0, src0{7-0}, 0);
971 bits<8> src0;
975 let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0);
980 bits<8> src0;
1023 let Inst{71-64} = !if(P.HasSrc0, src0{7-0}, 0);
1033 let Inst{71-64} = !if(P.HasSrc0, src0{7-0}, 0);
1055 (ops node:$src0),
1057 (ops node:$src0, node:$src1),
1058 (ops node:$src0, node:$src1, node:$src2))),
1060 (Op $src0),
1062 (Op $src0, $src1),
1063 (Op $src0, $src1, $src2))),
1082 (ops node:$src0),
1083 (Op $src0),
1109 GCNPat<(node vt:$src0, vt:$src1),
1110 (inst getVSrcOp<vt>.ret:$src0, getVSrcOp<vt>.ret:$src1,
1119 dag src0 = !if(P.HasOMod,
1120 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod),
1121 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp));
1124 (DivergentFragOrOp<node, P>.ret (P.Src0VT src0),
1129 (DivergentFragOrOp<node, P>.ret (P.Src0VT src0),
1133 (DivergentFragOrOp<node, P>.ret (P.Src0VT src0)))];
1143 dag src0_dag = (P.Src0VT (SrcPat P.Src0VT:$src0, i32:$src0_modifiers));
1170 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers)),
1175 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers)),
1179 (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers))))];
1188 …(DivergentFragOrOp<node, P>.ret (P.Src0VT !if(P.HasClamp, (VOP3OpSelMods P.Src0VT:$src0, i32:$src0…
1189 (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))),
1194 …(DivergentFragOrOp<node, P>.ret !if(P.HasClamp, (P.Src0VT (VOP3OpSelMods P.Src0VT:$src0, i32:$src0…
1195 (P.Src0VT (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))),
1199 … (DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))))];
1207 list<dag> ret = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))];
1211 dag src0 =
1214 (VOP3Mods0 P.Src0VT:$src0, i1:$clamp, i32:$omod),
1215 (VOP3Mods0 P.Src0VT:$src0, i32:$omod)), // impossible?
1217 (VOP3Mods0 P.Src0VT:$src0, i1:$clamp),
1218 (VOP3Mods0 P.Src0VT:$src0))
1220 …list<dag> ret3 = [(set P.DstVT:$vdst, (DivergentFragOrOp<node, P>.ret (P.Src0VT src0), P.Src1VT:$s…
1222 …list<dag> ret2 = [(set P.DstVT:$vdst, (DivergentFragOrOp<node, P>.ret (P.Src0VT src0), P.Src1VT:$s…
1224 list<dag> ret1 = [(set P.DstVT:$vdst, (DivergentFragOrOp<node, P>.ret (P.Src0VT src0)))];
1231 …list<dag> ret3 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, i1:$cl…
1232 list<dag> ret2 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, i1:$clamp))];
1233 list<dag> ret1 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, i1:$clamp))];
1242 [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2,
1245 … [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, i32:$idx,
1327 (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp,
1652 (is_fpclass (vt (VOP3ModsNonCanonicalizing vt:$src0, i32:$src0_mods)), (i32 timm:$mask)),
1653 (inst i32:$src0_mods, vt:$src0, (V_MOV_B32_e32 timm:$mask))