Lines Matching refs:src0
105 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
110 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
136 [(set R600_Reg32:$dst, (node R600_Reg32:$src0))], itin
147 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
153 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
175 [(set R600_Reg32:$dst, (node R600_Reg32:$src0,
187 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, SEL:$src0_sel,
193 "$src0_neg$src0$src0_rel, "
372 (ins i32imm:$src0, R600_TReg32_Y:$src1, R600_TReg32_X:$src2),
373 "INTERP_PAIR_XY $src0 $src1 $src2 : $dst0 dst1",
378 (ins i32imm:$src0, R600_TReg32_Y:$src1, R600_TReg32_X:$src2),
379 "INTERP_PAIR_ZW $src0 $src1 $src2 : $dst0 dst1",
435 (ins i32imm:$src0),
436 "INTERP_LOAD $src0 : $dst">;
683 (ins rc:$src0),
684 "FABS $dst, $src0",
685 [(set f32:$dst, (fabs f32:$src0))]
690 (ins rc:$src0),
691 "FNEG $dst, $src0",
692 [(set f32:$dst, (fneg f32:$src0))]
742 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_OEQ))]
747 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_OGT))]
752 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_OGE))]
757 [(set f32:$dst, (selectcc f32:$src0, f32:$src1, FP_ONE, FP_ZERO, COND_UNE_NE))]
762 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_OEQ))]
767 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_OGT))]
772 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_OGE))]
778 [(set i32:$dst, (selectcc f32:$src0, f32:$src1, -1, 0, COND_UNE_NE))]
860 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETEQ))]
865 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETGT))]
870 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETGE))]
875 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETNE))]
880 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETUGT))]
885 [(set i32:$dst, (selectcc i32:$src0, i32:$src1, -1, 0, SETUGE))]
895 [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_EQ))]
900 [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_SGE))]
905 [(set i32:$dst, (selectcc i32:$src0, 0, i32:$src1, i32:$src2, COND_SGT))]
997 [(set f32:$dst, (any_fmad f32:$src0, f32:$src1, f32:$src2))]
1002 [(set f32:$dst, (fma f32:$src0, f32:$src1, f32:$src2))], VecALU
1010 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_OEQ))]
1015 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_OGT))]
1022 [(set f32:$dst, (selectcc f32:$src0, FP_ZERO, f32:$src1, f32:$src2, COND_OGE))]
1079 (ins R600_Reg128:$src0),
1080 "CUBE $dst $src0",
1081 [(set v4f32:$dst, (int_r600_cube v4f32:$src0))],
1170 inst, "RECIP_IEEE", [(set f32:$dst, (AMDGPUrcp f32:$src0))]
1196 inst, "SIN", [(set f32:$dst, (SIN_HW f32:$src0))]>{
1202 inst, "COS", [(set f32:$dst, (COS_HW f32:$src0))]> {
1217 (fdiv f32:$src0, f32:$src1),
1218 (MUL_IEEE $src0, (recip_ieee $src1))
1375 (ins R600_Reg32:$src0, i32imm:$src1, i32imm:$flags),
1418 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2,
1420 "TXD $dst, $src0, $src1, $src2, $resourceId, $samplerId, $textureTarget", [],
1427 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2,
1429 "TXD_SHADOW $dst, $src0, $src1, $src2, $resourceId, $samplerId, $textureTarget",
1567 (ins brtarget:$target, rci:$src0),
1569 [(Op bb:$target, (i32 rci:$src0))]>;
1571 (ins brtarget:$target, rcf:$src0),
1573 [(Op bb:$target, (f32 rcf:$src0))]>;
1585 def _i32 : ILFormat<(outs), (ins R600_Reg32:$src0, R600_Reg32:$src1),
1586 !strconcat(name, " $src0, $src1"), []>;
1587 def _f32 : ILFormat<(outs), (ins R600_Reg32:$src0, R600_Reg32:$src1),
1588 !strconcat(name, " $src0, $src1"), []>;
1717 (selectcc i32:$src0, 0, f32:$src1, f32:$src2, cc),
1718 (cnd $src0, $src1, $src2)
1727 (selectcc i32:$src0, -1, i32:$src1, i32:$src2, COND_SGT),
1728 (CNDGE_INT $src0, $src1, $src2)
1733 (int_r600_kill f32:$src0),
1734 (MASK_WRITE (KILLGT (f32 ZERO), $src0))