Lines Matching refs:src0
73 bits<8> src0;
75 let Inst{7-0} = !if(ps.has_src0, src0, ?);
83 !if(tied_in, (ins SSrc_b32:$src0, SReg_32:$sdst_in),
84 (ins SSrc_b32:$src0)),
85 "$sdst, $src0", pattern> {
91 opName, (outs SReg_32:$sdst), (ins SReg_32:$src0),
92 "$sdst, $src0", pattern>;
96 opName, (outs), (ins SSrc_b32:$src0),
97 "$src0", pattern> {
103 opName, (outs), (ins SReg_32:$sdst, SSrc_b32:$src0),
104 "$sdst, $src0", pattern>;
108 opName, (outs), (ins SReg_64:$sdst, SSrc_b64:$src0),
109 "$sdst, $src0", pattern
113 opName, (outs), (ins SReg_32:$src0),
114 "$src0", pattern> {
119 opName, (outs SReg_64:$sdst), (ins SSrc_b64:$src0),
120 "$sdst, $src0", pattern
125 opName, (outs SReg_64:$sdst), (ins SReg_64:$src0),
126 "$sdst, $src0", pattern
131 opName, (outs SReg_32:$sdst), (ins SSrc_b64:$src0),
132 "$sdst, $src0", pattern
138 !if(tied_in, (ins SSrc_b32:$src0, SReg_64:$sdst_in),
139 (ins SSrc_b32:$src0)),
140 "$sdst, $src0", pattern> {
152 opName, (outs), (ins SReg_64:$src0), "$src0", pattern> {
158 (ops node:$src0),
159 (Op $src0),
170 (ops node:$src0, node:$src1),
171 (Op $src0, $src1),
182 (ops node:$src0, node:$src1, node:$src2),
183 (Op $src0, $src1, $src2),
194 (ops node:$src0, node:$src1),
195 (Op $src0, $src1),
225 [(set i32:$sdst, (UniformUnaryFrag<not> i32:$src0))]
229 [(set i64:$sdst, (UniformUnaryFrag<not> i64:$src0))]
232 [(set i32:$sdst, (int_amdgcn_s_wqm i32:$src0))]>;
234 [(set i64:$sdst, (int_amdgcn_s_wqm i64:$src0))]>;
240 (int_amdgcn_wqm_vote i1:$src0),
241 (S_WQM_B32 SSrc_b32:$src0)
247 (int_amdgcn_wqm_vote i1:$src0),
248 (S_WQM_B64 SSrc_b64:$src0)
254 [(set i32:$sdst, (UniformUnaryFrag<bitreverse> i32:$src0))]
257 [(set i64:$sdst, (UniformUnaryFrag<bitreverse> i64:$src0))]
265 [(set i32:$sdst, (UniformUnaryFrag<ctpop> i32:$src0))]
268 [(set i32:$sdst, (UniformUnaryFrag<ctpop> i64:$src0))]
276 [(set i32:$sdst, (UniformUnaryFrag<AMDGPUffbl_b32> i64:$src0))]
280 [(set i32:$sdst, (UniformUnaryFrag<AMDGPUffbl_b32> i32:$src0))]
284 [(set i32:$sdst, (UniformUnaryFrag<AMDGPUffbh_u32> i32:$src0))]
288 [(set i32:$sdst, (UniformUnaryFrag<AMDGPUffbh_u32> i64:$src0))]
291 [(set i32:$sdst, (UniformUnaryFrag<AMDGPUffbh_i32> i32:$src0))]
295 [(set i32:$sdst, (UniformSextInreg<i8> i32:$src0))]
298 [(set i32:$sdst, (UniformSextInreg<i16> i32:$src0))]
348 [(set i32:$sdst, (int_amdgcn_s_quadmask i32:$src0))]>;
350 [(set i64:$sdst, (int_amdgcn_s_quadmask i64:$src0))]>;
365 [(set i32:$sdst, (UniformUnaryFrag<abs> i32:$src0))]
386 [(set i64:$sdst, (int_amdgcn_s_bitreplicate i32:$src0))]>;
412 // For s_sendmsg_rtn_* the src0 field encodes the message type directly; it
415 "s_sendmsg_rtn_b32", (outs SReg_32:$sdst), (ins SendMsg:$src0),
416 "$sdst, $src0", [(set i32:$sdst, (int_amdgcn_s_sendmsg_rtn timm:$src0))]
419 "s_sendmsg_rtn_b64", (outs SReg_64:$sdst), (ins SendMsg:$src0),
420 "$sdst, $src0", [(set i64:$sdst, (int_amdgcn_s_sendmsg_rtn timm:$src0))]
427 SOP1_32<opName, [(set vt0:$sdst, (UniformUnaryFrag<Op> vt1:$src0))]>;
479 (ins SplitBarrier:$src0), "$src0", []>{
498 (ins SplitBarrier:$src0), "$src0", [(int_amdgcn_s_barrier_signal timm:$src0)]>{
504 (ins SplitBarrier:$src0), "$src0", [(set SCC, (int_amdgcn_s_barrier_signal_isfirst timm:$src0))]>{
511 (ins SplitBarrier:$src0), "$src0", []>{
517 (ins SplitBarrier:$src0), "$src0", []>{
524 (ins SplitBarrier:$src0), "$sdst, $src0", []>{
585 bits<8> src0;
592 let Inst{7-0} = src0;
601 let Inst{7-0} = src0;
610 opName, (outs SReg_32:$sdst), (ins SSrc_f16:$src0, SSrc_f16:$src1),
611 "$sdst, $src0, $src1", pattern
615 opName, (outs SReg_32:$sdst), (ins SSrc_b32:$src0, SSrc_b32:$src1),
616 "$sdst, $src0, $src1", pattern
620 opName, (outs SReg_32:$sdst), (ins SSrc_f32:$src0, SSrc_f32:$src1),
621 "$sdst, $src0, $src1", pattern
625 opName, (outs SReg_64:$sdst), (ins SSrc_b64:$src0, SSrc_b64:$src1),
626 "$sdst, $src0, $src1", pattern
630 opName, (outs SReg_64:$sdst), (ins SSrc_b64:$src0, SSrc_b32:$src1),
631 "$sdst, $src0, $src1", pattern
635 opName, (outs SReg_64:$sdst), (ins SSrc_b32:$src0, SSrc_b32:$src1),
636 "$sdst, $src0, $src1", pattern
644 [(set i32:$sdst, (UniformBinFrag<add> SSrc_b32:$src0, SSrc_b32:$src1))]
650 [(set i32:$sdst, (UniformBinFrag<sub> SSrc_b32:$src0, SSrc_b32:$src1))]
656 [(set i32:$sdst, (UniformBinFrag<adde> (i32 SSrc_b32:$src0), (i32 SSrc_b32:$src1)))]>;
660 [(set i32:$sdst, (UniformBinFrag<sube> (i32 SSrc_b32:$src0), (i32 SSrc_b32:$src1)))]>;
665 [(set i32:$sdst, (UniformBinFrag<smin> i32:$src0, i32:$src1))]
668 [(set i32:$sdst, (UniformBinFrag<umin> i32:$src0, i32:$src1))]
671 [(set i32:$sdst, (UniformBinFrag<smax> i32:$src0, i32:$src1))]
674 [(set i32:$sdst, (UniformBinFrag<umax> i32:$src0, i32:$src1))]
687 [(set i64:$sdst, (UniformBinFrag<mul> i64:$src0, i64:$src1))]> {
693 (outs SReg_64:$sdst), (ins SSrc_b64:$src0, SSrc_b64:$src1)
698 (outs SReg_64:$sdst), (ins SSrc_b64:$src0, SSrc_b64:$src1)
711 [(set i32:$sdst, (UniformBinFrag<and> i32:$src0, i32:$src1))]
715 [(set i64:$sdst, (UniformBinFrag<and> i64:$src0, i64:$src1))]
719 [(set i32:$sdst, (UniformBinFrag<or> i32:$src0, i32:$src1))]
723 [(set i64:$sdst, (UniformBinFrag<or> i64:$src0, i64:$src1))]
727 [(set i32:$sdst, (UniformBinFrag<xor> i32:$src0, i32:$src1))]
731 [(set i64:$sdst, (UniformBinFrag<xor> i64:$src0, i64:$src1))]
735 [(set i32:$sdst, (UniformUnaryFrag<not> (xor_oneuse i32:$src0, i32:$src1)))]
739 [(set i64:$sdst, (UniformUnaryFrag<not> (xor_oneuse i64:$src0, i64:$src1)))]
743 [(set i32:$sdst, (UniformUnaryFrag<not> (and_oneuse i32:$src0, i32:$src1)))]
747 [(set i64:$sdst, (UniformUnaryFrag<not> (and_oneuse i64:$src0, i64:$src1)))]
751 [(set i32:$sdst, (UniformUnaryFrag<not> (or_oneuse i32:$src0, i32:$src1)))]
755 [(set i64:$sdst, (UniformUnaryFrag<not> (or_oneuse i64:$src0, i64:$src1)))]
761 [(set i32:$sdst, (UniformBinFrag<and> i32:$src0, (not i32:$src1)))]
765 [(set i64:$sdst, (UniformBinFrag<and> i64:$src0, (not i64:$src1)))]
769 [(set i32:$sdst, (UniformBinFrag<or> i32:$src0, (not i32:$src1)))]
773 [(set i64:$sdst, (UniformBinFrag<or> i64:$src0, (not i64:$src1)))]
783 [(set SReg_32:$sdst, (UniformBinFrag<cshl_32> (i32 SSrc_b32:$src0), (i32 SSrc_b32:$src1)))]
786 [(set SReg_64:$sdst, (UniformBinFrag<cshl_64> (i64 SSrc_b64:$src0), (i32 SSrc_b32:$src1)))]
789 [(set SReg_32:$sdst, (UniformBinFrag<csrl_32> (i32 SSrc_b32:$src0), (i32 SSrc_b32:$src1)))]
792 [(set SReg_64:$sdst, (UniformBinFrag<csrl_64> (i64 SSrc_b64:$src0), (i32 SSrc_b32:$src1)))]
795 [(set SReg_32:$sdst, (UniformBinFrag<csra_32> (i32 SSrc_b32:$src0), (i32 SSrc_b32:$src1)))]
798 [(set SReg_64:$sdst, (UniformBinFrag<csra_64> (i64 SSrc_b64:$src0), (i32 SSrc_b32:$src1)))]
804 [(set i32:$sdst, (UniformBinFrag<AMDGPUbfm> i32:$src0, i32:$src1))]>;
808 [(set i32:$sdst, (UniformBinFrag<mul> i32:$src0, i32:$src1))]> {
823 (ins SCSrc_b64:$src0, SCSrc_b64:$src1),
824 "$src0, $src1"
837 (ins SSrc_b64:$src0, SSrc_b32:$src1),
838 "$src0, $src1"
854 [(set i32:$sdst, (shl1_add SSrc_b32:$src0, SSrc_b32:$src1))]
857 [(set i32:$sdst, (shl2_add SSrc_b32:$src0, SSrc_b32:$src1))]
860 [(set i32:$sdst, (shl3_add SSrc_b32:$src0, SSrc_b32:$src1))]
863 [(set i32:$sdst, (shl4_add SSrc_b32:$src0, SSrc_b32:$src1))]
869 [(set i32:$sdst, (UniformBinFrag<mulhu> SSrc_b32:$src0, SSrc_b32:$src1))]>;
871 [(set i32:$sdst, (UniformBinFrag<mulhs> SSrc_b32:$src0, SSrc_b32:$src1))]>;
881 [(set dstVt:$sdst, (UniformBinFrag<Op> SSrc_f32:$src0, SSrc_f32:$src1))]>;
885 [(set f16:$sdst, (UniformBinFrag<Op> SSrc_f16:$src0, SSrc_f16:$src1))]>;
899 (ins SSrc_f32_Deferred:$src0, SSrc_f32_Deferred:$src1, KImmFP32:$imm),
900 "$sdst, $src0, $src1, $imm"
922 (ins SSrc_f32_Deferred:$src0, KImmFP32:$imm, SSrc_f32_Deferred:$src1),
923 "$sdst, $src0, $imm, $src1"
931 (ins SSrc_f32:$src0, SSrc_f32:$src1, SReg_32:$src2),
932 "$sdst, $src0, $src1",
933 [(set f32:$sdst, (UniformTernaryFrag<any_fma> SSrc_f32:$src0, SSrc_f32:$src1, SReg_32:$src2))]
938 (ins SSrc_f16:$src0, SSrc_f16:$src1, SReg_32:$src2),
939 "$sdst, $src0, $src1",
940 [(set f16:$sdst, (UniformTernaryFrag<any_fma> SSrc_f16:$src0, SSrc_f16:$src1, SReg_32:$src2))]
1064 (ins SReg_32:$src0, s16imm:$simm16),
1090 // [(set i1:$dst, (setcc i32:$src0, imm:$src1, SETEQ))]
1108 let isCommutable = 1, DisableEncoding = "$src0",
1109 Constraints = "$sdst = $src0" in {
1267 bits<8> src0;
1270 let Inst{7-0} = src0;
1278 opName, (outs), (ins rc0:$src0, rc1:$src1),
1279 "$src0, $src1", pattern > {
1285 [(set SCC, (UniformTernaryFrag<setcc> vt:$src0, vt:$src1, cond))] > {
1368 (ins SSrc_b32:$src0, GPRIdxMode:$src1),
1369 "$src0, $src1"> {
1654 def S_SLEEP_VAR : SOP1_0_32 <"s_sleep_var", [(int_amdgcn_s_sleep_var SSrc_b32:$src0)]> {
1899 (ops node:$src0, node:$src1),
1900 (select SCC, $src0, $src1),
1906 (i32 (UniformSelect i32:$src0, i32:$src1)),
1907 (S_CSELECT_B32 SSrc_b32:$src0, SSrc_b32:$src1)
1914 (f32 (UniformSelect f32:$src0, f32:$src1)),
1915 (S_CSELECT_B32 SSrc_b32:$src0, SSrc_b32:$src1)
1922 (i32 (addc i32:$src0, i32:$src1)),
1923 (S_ADD_U32 $src0, $src1)
1949 (UniformBinFrag<op> vt:$src0, (notnode vt:$src1)),
1950 (inst getSOPSrcForVT<vt>.ret:$src0, getSOPSrcForVT<vt>.ret:$src1)