Lines Matching refs:src0
40 let Asm64 = "$vdst, $sdst, $src0, $src1, $src2$clamp";
65 let Ins64 = (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
73 let Ins64 = (ins InterpSlot:$src0,
77 let Asm64 = "$vdst, $src0, $attr$attrchan$clamp$omod";
94 (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
98 (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
103 (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
183 // result = src0 * src1 + src2
190 // result = src0 * src1 + src2
361 (VOP3Mods f32:$src0, i32:$src0_modifiers),
386 [(set f32:$vdst, (int_amdgcn_interp_p1_f16 (VOP3Mods f32:$src0, i32:$src0_modifiers),
417 (i32 (zext (op i16:$src0, i16:$src1, i16:$src2))),
418 (inst VSrc_b16:$src0, VSrc_b16:$src1, VSrc_b16:$src2)
432 (op i16:$src0, i16:$src1, i16:$src2),
433 (inst i16:$src0, i16:$src1, i16:$src2, (i1 0))
444 (op2 (op1 i16:$src0, i16:$src1), i16:$src2),
445 (inst SRCMODS.NONE, $src0, SRCMODS.NONE, $src1, SRCMODS.NONE, $src2, DSTCLAMP.NONE)
507 (ops node:$src0, node:$src1), (shl node:$src0, node:$src1),
524 let InsVOP3OpSel = (ins FP32InputMods:$src0_modifiers, Src0RC64:$src0,
528 FP32InputMods:$src0_modifiers, Src0VOP3DPP:$src0,
535 FP32InputMods:$src0_modifiers, Src0VOP3DPP:$src0,
541 FP32InputMods:$src0_modifiers, Src0VOP3DPP:$src0,
551 let InsVOP3OpSel = (ins FP32InputMods:$src0_modifiers, Src0RC64:$src0,
556 FP32InputMods:$src0_modifiers, Src0VOP3DPP:$src0,
562 FP32InputMods:$src0_modifiers, Src0VOP3DPP:$src0,
622 // TODO src0 contains the opsel bit for dst, so if we commute, need to mask and swap this
623 // to the new src0.
659 // src0 is shifted left by 0-4 (use “0” to get ADD_U64).
685 (i32 (node f32:$src0, f32:$src1, i32:$old, index)),
686 (inst !if(index, SRCMODS.DST_OP_SEL, 0), $src0, 0, $src1, $old, 0)
690 (i32 (node f32:$src0, i32:$src1, i32:$old, index)),
691 (inst !if(index{1}, SRCMODS.DST_OP_SEL, 0), $src0, 0, $src1,
696 … (i32 (node (VOP3Mods SrcVT:$src0, i32:$src0_modifiers), (VOP3Mods i32:$src1, i32:$src1_modifiers),
698 (inst $src0_modifiers, $src0, $src1_modifiers, $src1, $old, (as_i32timm $byte_sel))
721 // This matches (op2 (op1 i32:$src0, i32:$src1), i32:$src2) with conditions.
722 (ThreeOpFrag<op1, op2> i32:$src0, i32:$src1, i32:$src2),
723 (inst VSrc_b32:$src0, VSrc_b32:$src1, VSrc_b32:$src2)
736 (DivergentBinFrag<mul> i32:$src0, IsPow2Plus1:$src1),
737 (V_LSHL_ADD_U32_e64 i32:$src0, (i32 (Log2_32 imm:$src1)), i32:$src0)>;
741 (ThreeOpFrag<shl_0_to_4, add> i64:$src0, i32:$src1, i64:$src2),
742 (V_LSHL_ADD_U64_e64 VSrc_b64:$src0, VSrc_b32:$src1, VSrc_b64:$src2)
748 def : GCNPat<(DivergentBinFrag<or> (or_oneuse i64:$src0, i64:$src1), i64:$src2),
750 (V_OR3_B32_e64 (i32 (EXTRACT_SUBREG $src0, sub0)),
753 (V_OR3_B32_e64 (i32 (EXTRACT_SUBREG $src0, sub1)),
760 (node (i16 (VOP3OpSel i16:$src0, i32:$src0_modifiers)),
762 (inst $src0_modifiers, $src0, $src1_modifiers, $src1, DSTCLAMP.ENABLE, 0)
771 (ThreeOpFrag<mul, add> i32:$src0, i32:$src1, i32:$src2),
772 (EXTRACT_SUBREG (inst i32:$src0, i32:$src1,
783 (ThreeOpFrag<mul, add> i32:$src0, i32:$src1, VGPR_32:$src2),
784 (EXTRACT_SUBREG (inst i32:$src0, i32:$src1,
795 (ThreeOpFrag<mul, add> i32:$src0, i32:$src1, (i32 imm:$src2)),
796 (EXTRACT_SUBREG (inst i32:$src0, i32:$src1, (i64 (as_i64imm $src2)), 0 /* clamp */), sub0)
803 (i64 (add (i64 (AMDGPUmul_u24 i32:$src0, i32:$src1)), i64:$src2)),
804 (inst $src0, $src1, $src2, 0 /* clamp */)
818 let InsVOP3OpSel = (ins IntOpSelMods:$src0_modifiers, VRegSrc_32:$src0,
828 let InsVOP3OpSel = (ins IntOpSelMods:$src0_modifiers, VRegSrc_32:$src0,
846 (vt (permlane vt:$vdst_in, vt:$src0, i32:$src1, i32:$src2,
848 (inst (opsel_i1timm $fi), VGPR_32:$src0, (opsel_i1timm $bc),
854 (permlane i32:$vdst_in, i32:$src0, i32:$src1,
856 (inst (opsel_i1timm $fi), VGPR_32:$src0, (opsel_i1timm $bc),
885 (add i16:$src0, (i16 NegSubInlineIntConst16:$src1)),
886 (V_SUB_NC_U16_e64 0, VSrc_b16:$src0, 0, NegSubInlineIntConst16:$src1, 0, 0)
903 (AMDGPUdiv_fmas (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)),
907 (inst $src0_modifiers, $src0, $src1_modifiers, $src1, $src2_modifiers, $src2)
978 (f16 (UniformUnaryFrag<node> (f16 (VOP3Mods0 f16:$src0, i32:$src0_modifiers,
980 (f16 (COPY_TO_REGCLASS (f32 (inst i32:$src0_modifiers, f16:$src0, i1:$clamp,
998 dag ret3 = (P.DstVT (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2));
999 dag ret2 = (P.DstVT (node P.Src0VT:$src0, P.Src1VT:$src1));
1000 dag ret1 = (P.DstVT (node P.Src0VT:$src0));
1007 dag ret3 = (inst P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, (i1 0));
1008 dag ret2 = (inst P.Src0VT:$src0, P.Src1VT:$src1, (i1 0));
1009 dag ret1 = (inst P.Src0VT:$src0, (i1 0));
1226 let InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in) in {
1228 } // End InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in)
1286 …let InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VGPR_32:$vdst_in), IsInvalidSingleU…
1288 …} // End InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32: $src1, VGPR_32:$vdst_in), IsInvalidS…