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/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcInstrVIS.td19 (outs RC:$rd), (ins RC:$rs1, RC:$rs2),
20 !strconcat(OpcStr, " $rs1, $rs2, $rd")>;
25 (outs I64Regs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
26 !strconcat(OpcStr, " $rs1, $rs2, $rd")>;
29 let rd = 0, rs1 = 0, rs2 = 0 in
34 let rs2 = 0 in
40 // For VIS Instructions with only rs2, rd operands.
44 (outs RC:$rd), (ins RC:$rs2),
45 !strconcat(OpcStr, " $rs2, $rd")>;
48 let rs1 = 0, rs2 = 0 in
[all …]
H A DSparcInstrAliases.td14 // mov<cond> <ccreg> rs2, rd
19 // mov<cond> (%icc|%xcc), rs2, rd
21 ", $rs2, $rd"),
22 (movrr IntRegs:$rd, IntRegs:$rs2, condVal)>;
29 // fmovs<cond> (%icc|%xcc), $rs2, $rd
31 ", $rs2, $rd"),
32 (fmovs FPRegs:$rd, FPRegs:$rs2, condVal)>;
34 // fmovd<cond> (%icc|%xcc), $rs2, $rd
36 ", $rs2, $rd"),
37 (fmovd DFPRegs:$rd, DFPRegs:$rs2, condVal)>;
[all …]
H A DSparcInstrUAOSA.td17 let rs2 = 0;
23 : F3_4<op3val, op5val, (outs RC:$rd), (ins RC:$rs1, RC:$rs2, RC:$rs3),
24 !strconcat(OpcStr, " $rs1, $rs2, $rs3, $rd")>;
29 (ins cbtarget:$imm10, CCOp:$cond, IntRegs:$rs1, IntRegs:$rs2),
30 !strconcat(OpcStr, "$cond $rs1, $rs2, $imm10")>;
72 def : Pat<(f32 (any_fma f32:$rs1, f32:$rs2, f32:$add)), (FMADDS $rs1, $rs2, $add)>;
73 def : Pat<(f64 (any_fma f64:$rs1, f64:$rs2, f64:$add)), (FMADDD $rs1, $rs2, $add)>;
74 def : Pat<(f32 (any_fma f32:$rs1, f32:$rs2, (fneg f32:$sub))), (FMSUBS $rs1, $rs2, $sub)>;
75 def : Pat<(f64 (any_fma f64:$rs1, f64:$rs2, (fneg f64:$sub))), (FMSUBD $rs1, $rs2, $sub)>;
76 def : Pat<(f32 (fneg (any_fma f32:$rs1, f32:$rs2, f32:$add))), (FNMADDS $rs1, $rs2, $add)>;
[all …]
H A DSparcInstrInfo.td456 (outs RC:$rd), (ins RC:$rs1, RC:$rs2),
457 !strconcat(OpcStr, " $rs1, $rs2, $rd"),
458 [(set Ty:$rd, (OpNode Ty:$rs1, Ty:$rs2))],
471 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
472 !strconcat(OpcStr, " $rs1, $rs2, $rd"), [],
484 (outs RC:$rd), (ins (MEMrr $rs1, $rs2):$addr),
498 def rr : F3_1_asi<3, Op3Val, (outs RC:$rd), (ins (MEMrr $rs1, $rs2):$addr, ASITag:$asi),
520 (outs), (ins (MEMrr $rs1, $rs2):$addr, RC:$rd),
535 def rr : F3_1_asi<3, Op3Val, (outs), (ins (MEMrr $rs1, $rs2):$addr, RC:$rd, ASITag:$asi),
579 let rd = 0, rs1 = 0, rs2 = 0 in
[all …]
H A DSparcInstrCrypto.td17 : F3_4<op3val, op5val, (outs RC:$rd), (ins RC:$rs1, RC:$rs2, simm5Op:$rs3),
18 !strconcat(OpcStr, " $rs1, $rs2, $rs3, $rd")>;
30 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
31 "aes_kexpand0 $rs1, $rs2, $rd", []>;
34 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
35 "aes_kexpand2 $rs1, $rs2, $rd", []>;
39 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
40 "camellia_fl $rs1, $rs2, $rd", []>;
42 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
43 "camellia_fli $rs1, $rs2, $rd", []>;
[all …]
H A DSparcInstr64Bit.td168 def : Pat<(tlsadd i64:$rs1, i64:$rs2, tglobaltlsaddr:$sym),
169 (TLS_ADDrr $rs1, $rs2, $sym)>;
212 (ins (MEMrr $rs1, $rs2):$addr, TailRelocSymTLSLoad:$sym),
218 (ins (MEMrr $rs1, $rs2):$addr, TailRelocSymGOTLoad:$sym),
291 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
292 "mov$cond %xcc, $rs2, $rd",
294 (SPselectxcc i32:$rs2, i32:$f, imm:$cond))]>;
304 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
305 "fmovs$cond %xcc, $rs2, $rd",
307 (SPselectxcc f32:$rs2, f32:$f, imm:$cond))]>;
[all …]
H A DSparcInstrFormats.td110 bits<5> rs2;
124 let Inst{4-0} = rs2;
171 bits<5> rs2;
178 let Inst{4-0} = rs2;
211 bits<5> rs2;
217 let Inst{4-0} = rs2;
224 bits<5> rs2;
231 let Inst{4-0} = rs2;
238 bits<5> rs2;
244 let Inst{4-0} = rs2;
[all …]
/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/
H A DEmulateInstructionRISCV.cpp168 static bool CompareB(uint64_t rs1, uint64_t rs2, uint32_t funct3) { in CompareB() argument
171 return rs1 == rs2; in CompareB()
173 return rs1 != rs2; in CompareB()
175 return int64_t(rs1) < int64_t(rs2); in CompareB()
177 return int64_t(rs1) >= int64_t(rs2); in CompareB()
179 return rs1 < rs2; in CompareB()
181 return rs1 >= rs2; in CompareB()
246 inst.rs2.Read(emulator), in Store()
247 [&](uint64_t rs2) { return emulator.WriteMem<T>(*addr, rs2); }) in Store() argument
273 zipOpt(emulator.ReadMem<T>(*addr), inst.rs2.Read(emulator)), in AtomicSwap()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo16Instr.td490 def : Pat<(brcond (i32 (cond0 mGPR:$rs1, imm_ty:$rs2)), bb:$offset),
491 (BT16 (inst mGPR:$rs1, imm_ty:$rs2), bb:$offset)>;
492 def : Pat<(brcond (i32 (cond1 mGPR:$rs1, imm_ty:$rs2)), bb:$offset),
493 (BF16 (inst mGPR:$rs1, imm_ty:$rs2), bb:$offset)>;
500 def : Pat<(brcond (i32 (setne sGPR:$rs1, sGPR:$rs2)), bb:$offset),
501 (BT16 (CMPNE16 sGPR:$rs1, sGPR:$rs2), bb:$offset)>;
502 def : Pat<(brcond (i32 (seteq sGPR:$rs1, sGPR:$rs2)), bb:$offset),
503 (BF16 (CMPNE16 sGPR:$rs1, sGPR:$rs2), bb:$offset)>;
507 def : Pat<(brcond (i32 (cond0 sGPR:$rs1, sGPR:$rs2)), bb:$offset),
508 (br (cmp sGPR:$rs1, sGPR:$rs2), bb:$offset)>;
[all …]
H A DCSKYInstrInfo.td1115 def : Pat<(Type (LoadOp (add GPR:$rs1, GPR:$rs2))), (Inst GPR:$rs1, GPR:$rs2, 0)>;
1116 def : Pat<(Type (LoadOp (add GPR:$rs1, (shl GPR:$rs2, (i32 1))))), (Inst GPR:$rs1, GPR:$rs2, 1)>;
1117 def : Pat<(Type (LoadOp (add GPR:$rs1, (shl GPR:$rs2, (i32 2))))), (Inst GPR:$rs1, GPR:$rs2, 2)>;
1118 def : Pat<(Type (LoadOp (add GPR:$rs1, (shl GPR:$rs2, (i32 3))))), (Inst GPR:$rs1, GPR:$rs2, 3)>;
1132 def : Pat<(StoreOp Type:$rs2, GPR:$rs1), (Inst Type:$rs2, GP
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoD.td188 def : InstAlias<"fsd $rs2, (${rs1})", (FSD FPR64:$rs2, GPR:$rs1, 0), 0>;
290 def : Pat<(fcopysign FPR64:$rs1, (fneg FPR64:$rs2)),
291 (FSGNJN_D FPR64:$rs1, FPR64:$rs2)>;
292 def : Pat<(fcopysign FPR64:$rs1, FPR32:$rs2), (FSGNJ_D $rs1, (FCVT_D_S $rs2,
294 def : Pat<(fcopysign FPR32:$rs1, FPR64:$rs2), (FSGNJ_S $rs1, (FCVT_S_D $rs2,
297 // fmadd: rs1 * rs2 + rs3
298 def : Pat<(any_fma FPR64:$rs1, FPR64:$rs2, FPR64:$rs3),
299 (FMADD_D $rs1, $rs2, $rs3, FRM_DYN)>;
301 // fmsub: rs1 * rs2 - rs3
302 def : Pat<(any_fma FPR64:$rs1, FPR64:$rs2, (fneg FPR64:$rs3)),
[all …]
H A DRISCVInstrInfoC.td244 : RVInst16CSS<funct3, 0b10, (outs), (ins cls:$rs2, SPMem:$rs1, opnd:$imm),
245 OpcodeStr, "$rs2, ${imm}(${rs1})">;
256 : RVInst16CS<funct3, 0b00, (outs), (ins cls:$rs2,GPRCMem:$rs1, opnd:$imm),
257 OpcodeStr, "$rs2, ${imm}(${rs1})">;
286 (ins GPRC:$rd, GPRC:$rs2), OpcodeStr, "$rd, $rs2"> {
542 let rs2 = 0;
547 def C_MV : RVInst16CR<0b1000, 0b10, (outs GPRNoX0:$rs1), (ins GPRNoX0:$rs2),
548 "c.mv", "$rs1, $rs2">,
551 let rs1 = 0, rs2 = 0, hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
555 isCall=1, Defs=[X1], rs2 = 0 in
[all …]
H A DRISCVInstrInfoVSDPatterns.td41 def : Pat<(store (type regclass:$rs2), (XLenVT GPR:$rs1)),
42 (store_instr reg_class:$rs2, GPR:$rs1, avl, log2sew)>;
53 def : Pat<(store (m.Mask VR:$rs2), GPR:$rs1),
54 (store_instr VR:$rs2, GPR:$rs1, m.AVL, m.Log2SEW)>;
68 (op_type op_reg_class:$rs2))),
75 op_reg_class:$rs2,
89 (op_type op_reg_class:$rs2))),
96 op_reg_class:$rs2,
116 (vop_type (SplatPatKind (XLenVT xop_kind:$rs2))))),
123 xop_kind:$rs2,
[all …]
H A DRISCVInstrInfoZb.td256 let rs2 = 0;
498 def : Pat<(XLenVT (and GPR:$rs1, (not GPR:$rs2))), (ANDN GPR:$rs1, GPR:$rs2)>;
499 def : Pat<(XLenVT (or GPR:$rs1, (not GPR:$rs2))), (ORN GPR:$rs1, GPR:$rs2)>;
500 def : Pat<(XLenVT (not (riscv_xor_like GPR:$rs1, GPR:$rs2))),
501 (XNOR GPR:$rs1, GPR:$rs2)>;
503 def : Pat<(XLenVT (and GPR:$rs1, invLogicImm:$rs2)), (ANDN GPR:$rs1, invLogicImm:$rs2)>;
504 def : Pat<(XLenVT (or GPR:$rs1, invLogicImm:$rs2)), (ORN GPR:$rs1, invLogicImm:$rs2)>;
505 def : Pat<(XLenVT (xor GPR:$rs1, invLogicImm:$rs2)), (XNOR GPR:$rs1, invLogicImm:$rs2)>;
523 def : Pat<(riscv_rolw GPR:$rs1, uimm5:$rs2),
524 (RORIW GPR:$rs1, (ImmSubFrom32 uimm5:$rs2))>;
[all …]
H A DRISCVInstrInfoZfh.td232 def : InstAlias<"fsh $rs2, (${rs1})", (FSH FPR16:$rs2, GPR:$rs1, 0), 0>;
303 def : Pat<(f16 (fcopysign FPR16:$rs1, (f16 (fneg FPR16:$rs2)))),
304 (FSGNJN_H FPR16:$rs1, FPR16:$rs2)>;
305 def : Pat<(f16 (fcopysign FPR16:$rs1, FPR32:$rs2)),
306 (FSGNJ_H $rs1, (f16 (FCVT_H_S $rs2, FRM_DYN)))>;
308 // fmadd: rs1 * rs2 + rs3
309 def : Pat<(f16 (any_fma FPR16:$rs1, FPR16:$rs2, FPR16:$rs3)),
310 (FMADD_H $rs1, $rs2, $rs3, FRM_DYN)>;
312 // fmsub: rs1 * rs2 - rs3
313 def : Pat<(f16 (any_fma FPR16:$rs1, FPR16:$rs2, (fneg FPR16:$rs3))),
[all …]
H A DRISCVInstrInfoXwch.td75 (ins GPRC:$rs2, GPRCMem:$rs1,
77 "qk.c.sb", "$rs2, ${imm}(${rs1})">,
96 (ins GPRC:$rs2, GPRCMem:$rs1, uimm6_lsb0:$imm),
97 "qk.c.sh", "$rs2, ${imm}(${rs1})">,
150 def : InstAlias<"qk.c.sb $rs2, (${rs1})", (QK_C_SB GPRC:$rs2, GPRCMem:$rs1, 0)>;
152 def : InstAlias<"qk.c.sh $rs2, (${rs1})", (QK_C_SH GPRC:$rs2, GPRCMem:$rs1, 0)>;
154 def : InstAlias<"qk.c.sbsp $rs2, (${rs1})", (QK_C_SBSP GPRC:$rs2, SPMem:$rs1, 0)>;
156 def : InstAlias<"qk.c.shsp $rs2, (${rs1})", (QK_C_SHSP GPRC:$rs2, SPMem:$rs1, 0)>;
167 def : CompressPat<(SB GPRC:$rs2, GPRCMem:$rs1, uimm5:$imm),
168 (QK_C_SB GPRC:$rs2, GPRCMem:$rs1, uimm5:$imm)>;
[all …]
H A DRISCVInstrInfoXMips.td81 bits<5> rs2;
86 let Inst{24-20} = rs2;
99 bits<5> rs2;
104 let Inst{24-20} = rs2;
151 (ins GPR:$rs1, GPR:$rs2, GPR:$rs3),
152 "mips.ccmov", "$rd, $rs2, $rs1, $rs3">,
157 def : Pat<(select (riscv_setne (XLenVT GPR:$rs2)),
159 (MIPS_CCMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
160 def : Pat<(select (riscv_seteq (XLenVT GPR:$rs2)),
162 (MIPS_CCMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
[all …]
H A DRISCVInstrInfoSFB.td47 // Conditional binops, that updates update $dst to (op rs1, rs2) when condition
55 GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
60 GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
65 GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
70 GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
75 GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
80 GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
85 GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
90 GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
96 GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
[all …]
H A DRISCVInstrInfoXqci.td298 bits<5> rs2;
304 let Inst{24-20} = rs2;
355 AnyReg:$rs2,
358 "$opcode, $func3, $func2, $rs2, ${imm26}(${rs1})">;
402 def : InstAlias<".insn_qc.es $opcode, $func3, $func2, $rs2, ${imm26}(${rs1})",
406 AnyReg:$rs2,
409 def : InstAlias<".insn_qc.es $opcode, $func3, $func2, $rs2, (${rs1})",
413 AnyReg:$rs2,
425 (outs GPR:$rd), (ins GPRMem:$rs1, GPRNoX0:$rs2, uimm3:$shamt),
426 opcodestr, "$rd, $rs1, $rs2, $shamt"> {
[all …]
H A DRISCVInstrInfoF.td104 def any_fma_nsz : PatFrag<(ops node:$rs1, node:$rs2, node:$rs3),
105 (any_fma node:$rs1, node:$rs2, node:$rs3), [{
207 (ins rty:$rs2, GPRMem:$rs1, simm12:$imm12),
208 opcodestr, "$rs2, ${imm12}(${rs1})">,
216 (ins rty:$rs1, rty:$rs2, rty:$rs3, frmarg:$frm),
217 opcodestr, "$rd, $rs1, $rs2, $rs3$frm">;
229 (ins rty:$rs1, rty:$rs2), opcodestr, "$rd, $rs1, $rs2"> {
243 (ins rty:$rs1, rty:$rs2, frmarg:$frm), opcodestr,
244 "$rd, $rs1, $rs2$frm"> {
258 let rs2 = rs2val;
[all …]
H A DRISCVInstrInfoXCV.td73 (ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2">;
78 let rs2 = 0b00000;
84 (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
85 opcodestr, "$rd, $rs1, $rs2"> {
95 "$rd, $rs1, $rs2, $imm5"> {
108 (ins GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$imm5), opcodestr> {
114 (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5), opcodestr>;
119 (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5), opcodestr,
120 "$rd, $rs1, $rs2, $imm5"> {
129 (ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2">;
[all …]
H A DRISCVGISel.td46 def : Pat<(XLenVT (setult (PtrVT GPR:$rs1), (PtrVT GPR:$rs2))),
47 (SLTU GPR:$rs1, GPR:$rs2)>;
50 def : Pat<(XLenVT (setlt (PtrVT GPR:$rs1), (PtrVT GPR:$rs2))),
51 (SLT GPR:$rs1, GPR:$rs2)>;
59 def : Pat<(XLenVT (seteq (Ty GPR:$rs1), (Ty GPR:$rs2))),
60 (SLTIU (XOR GPR:$rs1, GPR:$rs2), 1)>;
64 def : Pat<(XLenVT (setne (Ty GPR:$rs1), (Ty GPR:$rs2))),
65 (SLTU (XLenVT X0), (XOR GPR:$rs1, GPR:$rs2))>;
69 def : Pat<(XLenVT (setugt (Ty GPR:$rs1), (Ty GPR:$rs2))),
70 (SLTU GPR:$rs2, GPR:$rs1)>;
[all …]
H A DRISCVInstrInfoVVLPatterns.td280 def any_riscv_vfmadd_vl : PatFrags<(ops node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl),
281 [(riscv_vfmadd_vl node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl),
282 … (riscv_strict_vfmadd_vl node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl)]>;
283 def any_riscv_vfnmadd_vl : PatFrags<(ops node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl),
284 [(riscv_vfnmadd_vl node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl),
285 … (riscv_strict_vfnmadd_vl node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl)]>;
286 def any_riscv_vfmsub_vl : PatFrags<(ops node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl),
287 [(riscv_vfmsub_vl node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl),
288 … (riscv_strict_vfmsub_vl node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl)]>;
289 def any_riscv_vfnmsub_vl : PatFrags<(ops node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl),
[all …]
H A DRISCVInstrInfoXTHead.td106 (ins GPR:$rs1, GPR:$rs2, uimm2:$uimm2),
107 opcodestr, "$rd, $rs1, $rs2, $uimm2"> {
144 (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
145 opcodestr, "$rd, $rs1, $rs2"> {
152 (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
153 opcodestr, "$rd, $rs1, $rs2"> {
160 (outs GPR:$rd, GPR:$rs2),
162 opcodestr, "$rd, $rs2, (${rs1}), $uimm2, $const3or4"> {
167 let Constraints = "@earlyclobber $rd,@earlyclobber $rs2";
173 (ins GPR:$rd, GPR:$rs2, GPR:$rs1, uimm2:$uimm2, consttype:$const3or4),
[all …]
/freebsd/crypto/openssl/crypto/perlasm/
H A Driscv.pm287 my $rs2 = read_reg shift;
288 return ".word ".($template | ($rs2 << 20) | ($rs1 << 15) | ($rd << 7));
297 my $rs2 = read_reg shift;
298 return ".word ".($template | ($rs2 << 20) | ($rs1 << 15) | ($rd << 7));
307 my $rs2 = read_reg shift;
308 return ".word ".($template | ($rs2 << 20) | ($rs1 << 15) | ($rd << 7));
317 my $rs2 = read_reg shift;
318 return ".word ".($template | ($rs2 << 20) | ($rs1 << 15) | ($rd << 7));
346 my $rs2 = read_reg shift;
347 return ".word ".($template | ($rs2 << 20) | ($rs1 << 15) | ($rd << 7));
[all …]

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