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Searched refs:rs2 (Results 1 – 25 of 70) sorted by relevance

123

/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcInstrVIS.td20 (outs RC:$rd), (ins RC:$rs1, RC:$rs2),
21 !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
26 (outs I64Regs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
27 !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
30 let rd = 0, rs1 = 0, rs2 = 0 in
35 let rs2 = 0 in
41 // For VIS Instructions with only rs2, rd operands.
45 (outs RC:$rd), (ins RC:$rs2),
46 !strconcat(OpcStr, " $rs2, $rd"), []>;
49 let Constraints = "$rd = $f", rs1 = 0, rs2 = 0 in
[all …]
H A DSparcInstrAliases.td14 // mov<cond> <ccreg> rs2, rd
19 // mov<cond> (%icc|%xcc), rs2, rd
21 ", $rs2, $rd"),
22 (movrr IntRegs:$rd, IntRegs:$rs2, condVal)>;
29 // fmovs<cond> (%icc|%xcc), $rs2, $rd
31 ", $rs2, $rd"),
32 (fmovs FPRegs:$rd, FPRegs:$rs2, condVal)>;
34 // fmovd<cond> (%icc|%xcc), $rs2, $rd
36 ", $rs2, $rd"),
37 (fmovd DFPRegs:$rd, DFPRegs:$rs2, condVal)>;
[all …]
H A DSparcInstrInfo.td408 (outs RC:$rd), (ins RC:$rs1, RC:$rs2),
409 !strconcat(OpcStr, " $rs1, $rs2, $rd"),
410 [(set Ty:$rd, (OpNode Ty:$rs1, Ty:$rs2))],
423 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
424 !strconcat(OpcStr, " $rs1, $rs2, $rd"), [],
436 (outs RC:$rd), (ins (MEMrr $rs1, $rs2):$addr),
450 def rr : F3_1_asi<3, Op3Val, (outs RC:$rd), (ins (MEMrr $rs1, $rs2):$addr, ASITag:$asi),
472 def LDSTUBrr : F3_1<3, 0b001101, (outs IntRegs:$rd), (ins (MEMrr $rs1, $rs2):$addr),
477 (ins (MEMrr $rs1, $rs2):$addr, ASITag:$asi),
488 (outs), (ins (MEMrr $rs1, $rs2):$addr, RC:$rd),
[all …]
H A DSparcInstr64Bit.td166 def : Pat<(tlsadd i64:$rs1, i64:$rs2, tglobaltlsaddr:$sym),
167 (TLS_ADDrr $rs1, $rs2, $sym)>;
183 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2),
184 "mulx $rs1, $rs2, $rd",
185 [(set i64:$rd, (mul i64:$rs1, i64:$rs2))]>;
194 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2),
195 "sdivx $rs1, $rs2, $rd",
196 [(set i64:$rd, (sdiv i64:$rs1, i64:$rs2))]>;
203 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2),
204 "udivx $rs1, $rs2, $rd",
[all …]
H A DSparcInstrFormats.td128 bits<5> rs2;
135 let Inst{4-0} = rs2;
168 bits<5> rs2;
174 let Inst{4-0} = rs2;
181 bits<5> rs2;
188 let Inst{4-0} = rs2;
195 bits<5> rs2;
201 let Inst{4-0} = rs2;
204 // Shift by register rs2.
209 bits<5> rs2;
[all...]
/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/
H A DEmulateInstructionRISCV.cpp168 static bool CompareB(uint64_t rs1, uint64_t rs2, uint32_t funct3) { in CompareB() argument
171 return rs1 == rs2; in CompareB()
173 return rs1 != rs2; in CompareB()
175 return int64_t(rs1) < int64_t(rs2); in CompareB()
177 return int64_t(rs1) >= int64_t(rs2); in CompareB()
179 return rs1 < rs2; in CompareB()
181 return rs1 >= rs2; in CompareB()
246 inst.rs2.Read(emulator), in Store()
247 [&](uint64_t rs2) { return emulator.WriteMem<T>(*addr, rs2); }) in Store() argument
273 zipOpt(emulator.ReadMem<T>(*addr), inst.rs2.Read(emulator)), in AtomicSwap()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoZb.td497 def : Pat<(XLenVT (and GPR:$rs1, (not GPR:$rs2))), (ANDN GPR:$rs1, GPR:$rs2)>;
498 def : Pat<(XLenVT (or GPR:$rs1, (not GPR:$rs2))), (ORN GPR:$rs1, GPR:$rs2)>;
499 def : Pat<(XLenVT (xor GPR:$rs1, (not GPR:$rs2))), (XNOR GPR:$rs1, GPR:$rs2)>;
517 def : Pat<(riscv_rolw GPR:$rs1, uimm5:$rs2),
518 (RORIW GPR:$rs1, (ImmSubFrom32 uimm5:$rs2))>;
522 def : Pat<(XLenVT (and (not (shiftop<shl> 1, (XLenVT GPR:$rs2))), GPR:$rs1)),
523 (BCLR GPR:$rs1, GPR:$rs2)>;
524 def : Pat<(XLenVT (and (rotl -2, (XLenVT GPR:$rs2)), GPR:$rs1)),
525 (BCLR GPR:$rs1, GPR:$rs2)>;
526 def : Pat<(XLenVT (or (shiftop<shl> 1, (XLenVT GPR:$rs2)), GPR:$rs1)),
[all …]
H A DRISCVInstrInfoD.td186 def : InstAlias<"fsd $rs2, (${rs1})", (FSD FPR64:$rs2, GPR:$rs1, 0), 0>;
285 def : Pat<(fcopysign FPR64:$rs1, (fneg FPR64:$rs2)), (FSGNJN_D $rs1, $rs2)>;
286 def : Pat<(fcopysign FPR64:$rs1, FPR32:$rs2), (FSGNJ_D $rs1, (FCVT_D_S $rs2,
288 def : Pat<(fcopysign FPR32:$rs1, FPR64:$rs2), (FSGNJ_S $rs1, (FCVT_S_D $rs2,
291 // fmadd: rs1 * rs2 + rs3
292 def : Pat<(any_fma FPR64:$rs1, FPR64:$rs2, FPR64:$rs3),
293 (FMADD_D $rs1, $rs2, $rs3, FRM_DYN)>;
295 // fmsub: rs1 * rs2 - rs3
296 def : Pat<(any_fma FPR64:$rs1, FPR64:$rs2, (fneg FPR64:$rs3)),
297 (FMSUB_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, FRM_DYN)>;
[all …]
H A DRISCVInstrInfoVSDPatterns.td40 def : Pat<(store type:$rs2, GPR:$rs1),
41 (store_instr reg_class:$rs2, GPR:$rs1, avl, log2sew)>;
58 def : Pat<(store type:$rs2, GPR:$rs1),
59 (store_instr reg_class:$rs2, GPR:$rs1)>;
70 def : Pat<(store m.Mask:$rs2, GPR:$rs1),
71 (store_instr VR:$rs2, GPR:$rs1, m.AVL, m.Log2SEW)>;
85 (op_type op_reg_class:$rs2))),
92 op_reg_class:$rs2,
106 (op_type op_reg_class:$rs2))),
113 op_reg_class:$rs2,
[all …]
H A DRISCVInstrInfoC.td250 : RVInst16CSS<funct3, 0b10, (outs), (ins cls:$rs2, SPMem:$rs1, opnd:$imm),
251 OpcodeStr, "$rs2, ${imm}(${rs1})">;
262 : RVInst16CS<funct3, 0b00, (outs), (ins cls:$rs2,GPRCMem:$rs1, opnd:$imm),
263 OpcodeStr, "$rs2, ${imm}(${rs1})">;
293 : RVInst16CA<funct6, funct2, 0b01, (outs cls:$rd_wb), (ins cls:$rd, cls:$rs2),
294 OpcodeStr, "$rd, $rs2"> {
540 let rs2 = 0;
545 def C_MV : RVInst16CR<0b1000, 0b10, (outs GPRNoX0:$rs1), (ins GPRNoX0:$rs2),
546 "c.mv", "$rs1, $rs2">,
549 let rs1 = 0, rs2 = 0, hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
[all …]
H A DRISCVInstrInfoSFB.td47 // Conditional binops, that updates update $dst to (op rs1, rs2) when condition
55 GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
60 GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
65 GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
70 GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
75 GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
80 GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
85 GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
90 GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
96 GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
[all …]
H A DRISCVInstrInfoXwch.td93 (ins GPRC:$rs2, GPRCMem:$rs1,
95 "qk.c.sb", "$rs2, ${imm}(${rs1})">,
114 (ins GPRC:$rs2, GPRCMem:$rs1, uimm6_lsb0:$imm),
115 "qk.c.sh", "$rs2, ${imm}(${rs1})">,
168 def : InstAlias<"qk.c.sb $rs2, (${rs1})", (QK_C_SB GPRC:$rs2, GPRCMem:$rs1, 0)>;
170 def : InstAlias<"qk.c.sh $rs2, (${rs1})", (QK_C_SH GPRC:$rs2, GPRCMem:$rs1, 0)>;
172 def : InstAlias<"qk.c.sbsp $rs2, (${rs1})", (QK_C_SBSP GPRC:$rs2, SPMem:$rs1, 0)>;
174 def : InstAlias<"qk.c.shsp $rs2, (${rs1})", (QK_C_SHSP GPRC:$rs2, SPMem:$rs1, 0)>;
185 def : CompressPat<(SB GPRC:$rs2, GPRCMem:$rs1, uimm5_with_predicate:$imm),
186 (QK_C_SB GPRC:$rs2, GPRCMem:$rs1, uimm5_with_predicate:$imm)>;
[all …]
H A DRISCVInstrInfoZfh.td205 def : InstAlias<"fsh $rs2, (${rs1})", (FSH FPR16:$rs2, GPR:$rs1, 0), 0>;
275 def : Pat<(f16 (fcopysign FPR16:$rs1, (f16 (fneg FPR16:$rs2)))), (FSGNJN_H $rs1, $rs2)>;
276 def : Pat<(f16 (fcopysign FPR16:$rs1, FPR32:$rs2)),
277 (FSGNJ_H $rs1, (FCVT_H_S $rs2, FRM_DYN))>;
279 // fmadd: rs1 * rs2 + rs3
280 def : Pat<(f16 (any_fma FPR16:$rs1, FPR16:$rs2, FPR16:$rs3)),
281 (FMADD_H $rs1, $rs2, $rs3, FRM_DYN)>;
283 // fmsub: rs1 * rs2 - rs3
284 def : Pat<(f16 (any_fma FPR16:$rs1, FPR16:$rs2, (fneg FPR16:$rs3))),
285 (FMSUB_H FPR16:$rs1, FPR16:$rs2, FPR16:$rs3, FRM_DYN)>;
[all …]
H A DRISCVInstrInfoF.td71 def any_fma_nsz : PatFrag<(ops node:$rs1, node:$rs2, node:$rs3),
72 (any_fma node:$rs1, node:$rs2, node:$rs3), [{
171 (ins rty:$rs2, GPRMem:$rs1, simm12:$imm12),
172 opcodestr, "$rs2, ${imm12}(${rs1})">,
180 (ins rty:$rs1, rty:$rs2, rty:$rs3, frmarg:$frm),
181 opcodestr, "$rd, $rs1, $rs2, $rs3$frm">;
193 (ins rty:$rs1, rty:$rs2), opcodestr, "$rd, $rs1, $rs2"> {
207 (ins rty:$rs1, rty:$rs2, frmarg:$frm), opcodestr,
208 "$rd, $rs1, $rs2$frm"> {
222 let rs2 = rs2val;
[all …]
H A DRISCVInstrInfoVVLPatterns.td211 def any_riscv_vfmadd_vl : PatFrags<(ops node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl),
212 [(riscv_vfmadd_vl node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl),
213 … (riscv_strict_vfmadd_vl node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl)]>;
214 def any_riscv_vfnmadd_vl : PatFrags<(ops node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl),
215 [(riscv_vfnmadd_vl node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl),
216 … (riscv_strict_vfnmadd_vl node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl)]>;
217 def any_riscv_vfmsub_vl : PatFrags<(ops node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl),
218 [(riscv_vfmsub_vl node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl),
219 … (riscv_strict_vfmsub_vl node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl)]>;
220 def any_riscv_vfnmsub_vl : PatFrags<(ops node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl),
[all …]
H A DRISCVInstrInfoXCV.td32 (ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2">;
37 let rs2 = 0b00000;
58 (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
59 "cv.insertr", "$rd, $rs1, $rs2">;
74 (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
75 opcodestr, "$rd, $rs1, $rs2"> {
82 "$rd, $rs1, $rs2, $imm5"> {
92 (ins GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$imm5), opcodestr>;
96 (ins GPR:$rs1, GPR:$rs2, uimm
[all...]
H A DRISCVInstrInfoXTHead.td83 (ins GPR:$rs1, GPR:$rs2, uimm2:$uimm2),
84 opcodestr, "$rd, $rs1, $rs2, $uimm2"> {
123 (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
124 opcodestr, "$rd, $rs1, $rs2"> {
132 (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
133 opcodestr, "$rd, $rs1, $rs2"> {
141 (outs GPR:$rd, GPR:$rs2),
143 opcodestr, "$rd, $rs2, (${rs1}), $uimm2, $const3or4"> {
148 let Constraints = "@earlyclobber $rd,@earlyclobber $rs2";
155 (ins GPR:$rd, GPR:$rs2, GPR:$rs1, uimm2:$uimm2, uimm7:$const3or4),
[all …]
H A DRISCVInstrFormatsC.td29 bits<5> rs2;
33 let Inst{6-2} = rs2;
59 bits<5> rs2;
63 let Inst{6-2} = rs2;
99 bits<3> rs2;
104 let Inst{4-2} = rs2;
111 bits<3> rs2;
117 let Inst{4-2} = rs2;
197 bits<3> rs2;
202 let Inst{4-2} = rs2;
[all …]
H A DRISCVInstrInfoZc.td127 (ins GPRC:$rs2, GPRCMem:$rs1, uimm2:$imm),
128 OpcodeStr, "$rs2, ${imm}(${rs1})"> {
137 (ins GPRC:$rs2, GPRCMem:$rs1, uimm2_lsb0:$imm),
138 OpcodeStr, "$rs2, ${imm}(${rs1})"> {
212 (ins SR07:$rs1, SR07:$rs2), "cm.mva01s", "$rs1, $rs2">,
216 def CM_MVSA01 : RVInst16CA<0b101011, 0b01, 0b10, (outs SR07:$rs1, SR07:$rs2),
217 (ins), "cm.mvsa01", "$rs1, $rs2">,
274 def : CompressPat<(MUL GPRC:$rs1, GPRC:$rs1, GPRC:$rs2),
275 (C_MUL GPRC:$rs1, GPRC:$rs2)>;
277 def : CompressPat<(MUL GPRC:$rs1, GPRC:$rs2, GPRC:$rs1),
[all …]
H A DRISCVInstrInfoZvk.td221 (ins RetClass:$rd, OpClass:$rs2, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
237 (ins RetClass:$rd, Op1Class:$rs2, Op2Class:$rs1,
596 vti.RegClass:$rs2)),
599 vti.RegClass:$rs2,
604 vti.RegClass:$rs2)),
607 vti.RegClass:$rs2,
644 def : Pat<(vti.Vector (rotl vti.RegClass:$rs2,
648 vti.RegClass:$rs2,
661 def : Pat<(shl (wti.Vector (zext_oneuse (vti.Vector vti.RegClass:$rs2))),
665 vti.RegClass:$rs2, vti.RegClass:$rs1,
[all …]
H A DRISCVInstrInfoM.td96 (assertzexti32 GPR:$rs2)), 0xffffffff),
97 (DIVU GPR:$rs1, GPR:$rs2)>;
99 (assertzexti32 GPR:$rs2)), 0xffffffff),
100 (REMU GPR:$rs1, GPR:$rs2)>;
105 def : Pat<(srem (sexti32 (i64 GPR:$rs1)), (sexti32 (i64 GPR:$rs2))),
106 (REMW GPR:$rs1, GPR:$rs2)>;
114 def : Pat<(i64 (mul (and GPR:$rs1, 0xffffffff), (and GPR:$rs2, 0xffffffff))),
115 (MULHU (i64 (SLLI GPR:$rs1, 32)), (i64 (SLLI GPR:$rs2, 32)))>;
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo16Instr.td490 def : Pat<(brcond (i32 (cond0 mGPR:$rs1, imm_ty:$rs2)), bb:$offset),
491 (BT16 (inst mGPR:$rs1, imm_ty:$rs2), bb:$offset)>;
492 def : Pat<(brcond (i32 (cond1 mGPR:$rs1, imm_ty:$rs2)), bb:$offset),
493 (BF16 (inst mGPR:$rs1, imm_ty:$rs2), bb:$offset)>;
500 def : Pat<(brcond (i32 (setne sGPR:$rs1, sGPR:$rs2)), bb:$offset),
501 (BT16 (CMPNE16 sGPR:$rs1, sGPR:$rs2), bb:$offset)>;
502 def : Pat<(brcond (i32 (seteq sGPR:$rs1, sGPR:$rs2)), bb:$offset),
503 (BF16 (CMPNE16 sGPR:$rs1, sGPR:$rs2), bb:$offset)>;
507 def : Pat<(brcond (i32 (cond0 sGPR:$rs1, sGPR:$rs2)), bb:$offset),
508 (br (cmp sGPR:$rs1, sGPR:$rs2), bb:$offset)>;
[all …]
H A DCSKYInstrInfo.td1115 def : Pat<(Type (LoadOp (add GPR:$rs1, GPR:$rs2))), (Inst GPR:$rs1, GPR:$rs2, 0)>;
1116 def : Pat<(Type (LoadOp (add GPR:$rs1, (shl GPR:$rs2, (i32 1))))), (Inst GPR:$rs1, GPR:$rs2, 1)>;
1117 def : Pat<(Type (LoadOp (add GPR:$rs1, (shl GPR:$rs2, (i32 2))))), (Inst GPR:$rs1, GPR:$rs2, 2)>;
1118 def : Pat<(Type (LoadOp (add GPR:$rs1, (shl GPR:$rs2, (i32 3))))), (Inst GPR:$rs1, GPR:$rs2, 3)>;
1132 def : Pat<(StoreOp Type:$rs2, GPR:$rs1), (Inst Type:$rs2, GP
[all...]
H A DCSKYInstrInfoF2.td299 def : Pat<(brcond (i32 (setcc FPR32Op:$rs1, FPR32Op:$rs2, CC)), bb:$imm16),
300 (Br0 (!cast<Instruction>(Instr#_S) FPR32Op:$rs1, FPR32Op:$rs2), bb:$imm16)>;
302 def : Pat<(brcond (xor (i32 (setcc FPR32Op:$rs1, FPR32Op:$rs2, CC)), 1), bb:$imm16),
303 (Br1 (!cast<Instruction>(Instr#_S) FPR32Op:$rs1, FPR32Op:$rs2), bb:$imm16)>;
305 def : Pat<(brcond (i32 (setcc FPR64Op:$rs1, FPR64Op:$rs2, CC)), bb:$imm16),
306 (Br0 (!cast<Instruction>(Instr#_D) FPR64Op:$rs1, FPR64Op:$rs2), bb:$imm16)>;
308 def : Pat<(brcond (xor (i32 (setcc FPR64Op:$rs1, FPR64Op:$rs2, CC)), 1), bb:$imm16),
309 (Br1 (!cast<Instruction>(Instr#_D) FPR64Op:$rs1, FPR64Op:$rs2), bb:$imm16)>;
312 def : Pat<(i32 (setcc FPR32Op:$rs1, FPR32Op:$rs2, CC)),
313 (MV (!cast<Instruction>(Instr#_S) FPR32Op:$rs1, FPR32Op:$rs2))>;
[all...]
/freebsd/crypto/openssl/crypto/aes/asm/
H A Daesfx-sparcv9.pl1119 .Lout_align: ! fshiftorx parameters for right shift toward %rs2
1140 my ($mnemonic,$rs1,$rs2,$rd)=@_;
1148 $ref = "$mnemonic\t$rs1,$rs2,$rd";
1151 foreach ($rs1,$rs2,$rd) {
1162 0x81b00000|$rd<<25|$rs1<<14|$opf<<5|$rs2,
1170 my ($mnemonic,$rs1,$rs2,$rd)=@_;
1177 $ref = "$mnemonic\t$rs1,$rs2,$rd";
1180 foreach ($rs1,$rs2,$rd) {
1186 0x81b00000|$rd<<25|$rs1<<14|$opf<<5|$rs2,
1194 my ($mnemonic,$rs1,$rs2,$rd)=@_;
[all …]

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