Lines Matching refs:rs2
408 (outs RC:$rd), (ins RC:$rs1, RC:$rs2),
409 !strconcat(OpcStr, " $rs1, $rs2, $rd"),
410 [(set Ty:$rd, (OpNode Ty:$rs1, Ty:$rs2))],
423 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
424 !strconcat(OpcStr, " $rs1, $rs2, $rd"), [],
436 (outs RC:$rd), (ins (MEMrr $rs1, $rs2):$addr),
450 def rr : F3_1_asi<3, Op3Val, (outs RC:$rd), (ins (MEMrr $rs1, $rs2):$addr, ASITag:$asi),
472 def LDSTUBrr : F3_1<3, 0b001101, (outs IntRegs:$rd), (ins (MEMrr $rs1, $rs2):$addr),
477 (ins (MEMrr $rs1, $rs2):$addr, ASITag:$asi),
488 (outs), (ins (MEMrr $rs1, $rs2):$addr, RC:$rd),
503 def rr : F3_1_asi<3, Op3Val, (outs), (ins (MEMrr $rs1, $rs2):$addr, RC:$rd, ASITag:$asi),
547 let rd = 0, rs1 = 0, rs2 = 0 in
651 def LDCSRrr : F3_1<3, 0b110001, (outs), (ins (MEMrr $rs1, $rs2):$addr),
660 def LDFSRrr : F3_1<3, 0b100001, (outs), (ins (MEMrr $rs1, $rs2):$addr),
666 def LDXFSRrr : F3_1<3, 0b100001, (outs), (ins (MEMrr $rs1, $rs2):$addr),
676 (ins (MEMrr $rs1, $rs2):$addr, TailRelocSymGOTLoad:$sym),
707 def STCSRrr : F3_1<3, 0b110101, (outs), (ins (MEMrr $rs1, $rs2):$addr),
713 def STDCQrr : F3_1<3, 0b110110, (outs), (ins (MEMrr $rs1, $rs2):$addr),
722 def STFSRrr : F3_1<3, 0b100101, (outs), (ins (MEMrr $rs1, $rs2):$addr),
728 def STDFQrr : F3_1<3, 0b100110, (outs), (ins (MEMrr $rs1, $rs2):$addr),
735 def STXFSRrr : F3_1<3, 0b100101, (outs), (ins (MEMrr $rs1, $rs2):$addr),
745 (outs IntRegs:$rd), (ins (MEMrr $rs1, $rs2):$addr, IntRegs:$val),
753 (outs IntRegs:$rd), (ins (MEMrr $rs1, $rs2):$addr, ASITag:$asi, IntRegs:$val),
780 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
781 "andn $rs1, $rs2, $rd",
782 [(set i32:$rd, (and i32:$rs1, (not i32:$rs2)))]>;
790 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
791 "orn $rs1, $rs2, $rd",
792 [(set i32:$rd, (or i32:$rs1, (not i32:$rs2)))]>;
799 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
800 "xnor $rs1, $rs2, $rd",
801 [(set i32:$rd, (not (xor i32:$rs1, i32:$rs2)))]>;
806 def : Pat<(and IntRegs:$rs1, SETHIimm_not:$rs2),
807 (ANDNrr i32:$rs1, (SETHIi SETHIimm_not:$rs2))>;
809 def : Pat<(or IntRegs:$rs1, SETHIimm_not:$rs2),
810 (ORNrr i32:$rs1, (SETHIi SETHIimm_not:$rs2))>;
935 (outs), (ins (MEMrr $rs1, $rs2):$addr),
1043 (outs), (ins (MEMrr $rs1, $rs2):$addr, variable_ops),
1060 (outs IntRegs:$rd), (ins (MEMrr $rs1, $rs2):$addr),
1094 (outs), (ins (MEMrr $rs1, $rs2):$addr),
1111 (outs), (ins IntRegs:$rs1, IntRegs:$rs2, CCOp:$cond),
1112 "t$cond $rs1 + $rs2",
1122 (outs), (ins IntRegs:$rs1, IntRegs:$rs2, CCOp:$cond),
1123 !strconcat(!strconcat("t$cond ", regStr), ", $rs1 + $rs2"),
1142 let rs2 = 0 in
1149 let rs2 = 0, rs1 = 0, Uses=[PSR] in
1154 let rs2 = 0, rs1 = 0, Uses=[WIM] in
1159 let rs2 = 0, rs1 = 0, Uses=[TBR] in
1167 (outs ASRRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
1168 "wr $rs1, $rs2, $rd", []>;
1177 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
1178 "wr $rs1, $rs2, %psr", []>;
1186 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
1187 "wr $rs1, $rs2, %wim", []>;
1195 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
1196 "wr $rs1, $rs2, %tbr", []>;
1204 let hasSideEffects = 1, rd = 0, rs1 = 0b01111, rs2 = 0 in
1215 def FLUSHrr : F3_1<2, 0b111011, (outs), (ins (MEMrr $rs1, $rs2):$addr),
1223 let rs1 = 0, rs2 = 0 in
1231 (outs FPRegs:$rd), (ins FPRegs:$rs2),
1232 "fitos $rs2, $rd",
1233 [(set FPRegs:$rd, (SPitof FPRegs:$rs2))],
1236 (outs DFPRegs:$rd), (ins FPRegs:$rs2),
1237 "fitod $rs2, $rd",
1238 [(set DFPRegs:$rd, (SPitof FPRegs:$rs2))],
1241 (outs QFPRegs:$rd), (ins FPRegs:$rs2),
1242 "fitoq $rs2, $rd",
1243 [(set QFPRegs:$rd, (SPitof FPRegs:$rs2))]>,
1248 (outs FPRegs:$rd), (ins FPRegs:$rs2),
1249 "fstoi $rs2, $rd",
1250 [(set FPRegs:$rd, (SPftoi FPRegs:$rs2))],
1253 (outs FPRegs:$rd), (ins DFPRegs:$rs2),
1254 "fdtoi $rs2, $rd",
1255 [(set FPRegs:$rd, (SPftoi DFPRegs:$rs2))],
1258 (outs FPRegs:$rd), (ins QFPRegs:$rs2),
1259 "fqtoi $rs2, $rd",
1260 [(set FPRegs:$rd, (SPftoi QFPRegs:$rs2))]>,
1265 (outs DFPRegs:$rd), (ins FPRegs:$rs2),
1266 "fstod $rs2, $rd",
1267 [(set f64:$rd, (fpextend f32:$rs2))],
1270 (outs QFPRegs:$rd), (ins FPRegs:$rs2),
1271 "fstoq $rs2, $rd",
1272 [(set f128:$rd, (fpextend f32:$rs2))]>,
1275 (outs FPRegs:$rd), (ins DFPRegs:$rs2),
1276 "fdtos $rs2, $rd",
1277 [(set f32:$rd, (fpround f64:$rs2))],
1280 (outs QFPRegs:$rd), (ins DFPRegs:$rs2),
1281 "fdtoq $rs2, $rd",
1282 [(set f128:$rd, (fpextend f64:$rs2))]>,
1285 (outs FPRegs:$rd), (ins QFPRegs:$rs2),
1286 "fqtos $rs2, $rd",
1287 [(set f32:$rd, (fpround f128:$rs2))]>,
1290 (outs DFPRegs:$rd), (ins QFPRegs:$rs2),
1291 "fqtod $rs2, $rd",
1292 [(set f64:$rd, (fpround f128:$rs2))]>,
1297 (outs FPRegs:$rd), (ins FPRegs:$rs2),
1298 "fmovs $rs2, $rd", []>;
1300 (outs FPRegs:$rd), (ins FPRegs:$rs2),
1301 "fnegs $rs2, $rd",
1302 [(set f32:$rd, (fneg f32:$rs2))],
1305 (outs FPRegs:$rd), (ins FPRegs:$rs2),
1306 "fabss $rs2, $rd",
1307 [(set f32:$rd, (fabs f32:$rs2))],
1316 (outs FPRegs:$rd), (ins FPRegs:$rs2),
1317 "fsqrts $rs2, $rd",
1318 [(set f32:$rd, (fsqrt f32:$rs2))],
1321 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
1322 "fsqrtd $rs2, $rd",
1323 [(set f64:$rd, (fsqrt f64:$rs2))],
1326 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
1327 "fsqrtq $rs2, $rd",
1328 [(set f128:$rd, (fsqrt f128:$rs2))]>,
1335 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1336 "fadds $rs1, $rs2, $rd",
1337 [(set f32:$rd, (fadd f32:$rs1, f32:$rs2))],
1340 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1341 "faddd $rs1, $rs2, $rd",
1342 [(set f64:$rd, (fadd f64:$rs1, f64:$rs2))],
1345 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1346 "faddq $rs1, $rs2, $rd",
1347 [(set f128:$rd, (fadd f128:$rs1, f128:$rs2))]>,
1351 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1352 "fsubs $rs1, $rs2, $rd",
1353 [(set f32:$rd, (fsub f32:$rs1, f32:$rs2))],
1356 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1357 "fsubd $rs1, $rs2, $rd",
1358 [(set f64:$rd, (fsub f64:$rs1, f64:$rs2))],
1361 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1362 "fsubq $rs1, $rs2, $rd",
1363 [(set f128:$rd, (fsub f128:$rs1, f128:$rs2))]>,
1369 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1370 "fmuls $rs1, $rs2, $rd",
1371 [(set f32:$rd, (fmul f32:$rs1, f32:$rs2))],
1375 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1376 "fmuld $rs1, $rs2, $rd",
1377 [(set f64:$rd, (fmul f64:$rs1, f64:$rs2))],
1380 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1381 "fmulq $rs1, $rs2, $rd",
1382 [(set f128:$rd, (fmul f128:$rs1, f128:$rs2))]>,
1386 (outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1387 "fsmuld $rs1, $rs2, $rd",
1389 (fpextend f32:$rs2)))],
1393 (outs QFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1394 "fdmulq $rs1, $rs2, $rd",
1396 (fpextend f64:$rs2)))]>,
1402 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1403 "fdivs $rs1, $rs2, $rd",
1404 [(set f32:$rd, (fdiv f32:$rs1, f32:$rs2))],
1407 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1408 "fdivd $rs1, $rs2, $rd",
1409 [(set f64:$rd, (fdiv f64:$rs1, f64:$rs2))],
1412 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1413 "fdivq $rs1, $rs2, $rd",
1414 [(set f128:$rd, (fdiv f128:$rs1, f128:$rs2))]>,
1426 (outs), (ins FPRegs:$rs1, FPRegs:$rs2),
1427 "fcmps $rs1, $rs2",
1428 [(SPcmpfcc f32:$rs1, f32:$rs2)],
1431 (outs), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1432 "fcmpd $rs1, $rs2",
1433 [(SPcmpfcc f64:$rs1, f64:$rs2)],
1436 (outs), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1437 "fcmpq $rs1, $rs2",
1438 [(SPcmpfcc f128:$rs1, f128:$rs2)]>,
1451 (outs), (ins FPRegs:$rs1, FPRegs:$rs2),
1452 "fcmps %fcc0, $rs1, $rs2",
1453 [(SPcmpfccv9 f32:$rs1, f32:$rs2)],
1456 (outs), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1457 "fcmpd %fcc0, $rs1, $rs2",
1458 [(SPcmpfccv9 f64:$rs1, f64:$rs2)],
1461 (outs), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1462 "fcmpq %fcc0, $rs1, $rs2",
1463 [(SPcmpfccv9 f128:$rs1, f128:$rs2)]>,
1473 (ins IntRegs:$rs1, IntRegs:$rs2, TailRelocSymTLSAdd:$sym),
1474 "add $rs1, $rs2, $rd, $sym",
1476 (tlsadd i32:$rs1, i32:$rs2, tglobaltlsaddr:$sym))]>;
1481 (ins (MEMrr $rs1, $rs2):$addr, TailRelocSymTLSLoad:$sym),
1535 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
1536 "mov$cond %icc, $rs2, $rd",
1537 [(set i32:$rd, (SPselecticc i32:$rs2, i32:$f, imm:$cond))]>;
1550 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
1551 "mov$cond %fcc0, $rs2, $rd",
1552 [(set i32:$rd, (SPselectfcc i32:$rs2, i32:$f, imm:$cond))]>;
1564 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
1565 "fmovs$cond %icc, $rs2, $rd",
1566 [(set f32:$rd, (SPselecticc f32:$rs2, f32:$f, imm:$cond))]>;
1569 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
1570 "fmovd$cond %icc, $rs2, $rd",
1571 [(set f64:$rd, (SPselecticc f64:$rs2, f64:$f, imm:$cond))]>;
1575 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
1576 "fmovq$cond %icc, $rs2, $rd",
1577 [(set f128:$rd, (SPselecticc f128:$rs2, f128:$f, imm:$cond))]>;
1583 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
1584 "fmovs$cond %fcc0, $rs2, $rd",
1585 [(set f32:$rd, (SPselectfcc f32:$rs2, f32:$f, imm:$cond))]>;
1588 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
1589 "fmovd$cond %fcc0, $rs2, $rd",
1590 [(set f64:$rd, (SPselectfcc f64:$rs2, f64:$f, imm:$cond))]>;
1594 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
1595 "fmovq$cond %fcc0, $rs2, $rd",
1596 [(set f128:$rd, (SPselectfcc f128:$rs2, f128:$f, imm:$cond))]>;
1604 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
1605 "fmovd $rs2, $rd", []>;
1608 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
1609 "fmovq $rs2, $rd", []>;
1611 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
1612 "fnegd $rs2, $rd",
1613 [(set f64:$rd, (fneg f64:$rs2))]>;
1616 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
1617 "fnegq $rs2, $rd",
1618 [(set f128:$rd, (fneg f128:$rs2))]>;
1620 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
1621 "fabsd $rs2, $rd",
1622 [(set f64:$rd, (fabs f64:$rs2))]>;
1625 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
1626 "fabsq $rs2, $rd",
1627 [(set f128:$rd, (fabs f128:$rs2))]>;
1632 (outs FCCRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1633 "fcmps $rd, $rs1, $rs2", []>;
1635 (outs FCCRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1636 "fcmpd $rd, $rs1, $rs2", []>;
1638 (outs FCCRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1639 "fcmpq $rd, $rs1, $rs2", []>,
1644 (outs FCCRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1645 "fcmpes $rd, $rs1, $rs2", []>;
1647 (outs FCCRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1648 "fcmped $rd, $rs1, $rs2", []>;
1650 (outs FCCRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1651 "fcmpeq $rd, $rs1, $rs2", []>,
1660 (ins FCCRegs:$cc, IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
1661 "mov$cond $cc, $rs2, $rd", []>;
1668 (ins FCCRegs:$opf_cc, FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
1669 "fmovs$cond $opf_cc, $rs2, $rd", []>;
1672 (ins FCCRegs:$opf_cc, DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
1673 "fmovd$cond $opf_cc, $rs2, $rd", []>;
1677 (ins FCCRegs:$opf_cc, QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
1678 "fmovq$cond $opf_cc, $rs2, $rd", []>;
1687 (outs IntRegs:$rd), (ins IntRegs:$rs2),
1688 "popc $rs2, $rd", []>, Requires<[HasV9]>;
1704 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
1706 "casa [$rs1] $asi, $rs2, $rd", []>;
1712 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
1714 "casa [$rs1] %asi, $rs2, $rd", []>;
1720 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2, ASRRegs:$asr18),
1721 "smac $rs1, $rs2, $rd",
1730 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2, ASRRegs:$asr18),
1731 "umac $rs1, $rs2, $rd",
1744 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
1745 "pwr $rs1, $rs2, %psr", []>;
1763 let Predicates = [HasV9], rs1 = 0, rs2 = 0 in {
1780 (outs), (ins (MEMrr $rs1, $rs2):$addr, PrefetchTag:$rd),
1786 (ins (MEMrr $rs1, $rs2):$addr, ASITag:$asi, PrefetchTag:$rd),
1798 let rs2 = 0 in
1807 let Uses = [FQ], rs1 = 15, rs2 = 0 in
1816 (outs PRRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
1817 "wrpr $rs1, $rs2, $rd", []>;
1916 def : Pat<(atomic_cmp_swap_i32 iPTR:$rs1, i32:$rs2, i32:$swap),
1917 (CASArr $rs1, $rs2, $swap, 0x80)>;
1921 def : Pat<(atomic_cmp_swap_i32 iPTR:$rs1, i32:$rs2, i32:$swap),
1922 (CASArr $rs1, $rs2, $swap, 0x0A)>;