Lines Matching refs:rs2
186 def : InstAlias<"fsd $rs2, (${rs1})", (FSD FPR64:$rs2, GPR:$rs1, 0), 0>;
285 def : Pat<(fcopysign FPR64:$rs1, (fneg FPR64:$rs2)), (FSGNJN_D $rs1, $rs2)>;
286 def : Pat<(fcopysign FPR64:$rs1, FPR32:$rs2), (FSGNJ_D $rs1, (FCVT_D_S $rs2,
288 def : Pat<(fcopysign FPR32:$rs1, FPR64:$rs2), (FSGNJ_S $rs1, (FCVT_S_D $rs2,
291 // fmadd: rs1 * rs2 + rs3
292 def : Pat<(any_fma FPR64:$rs1, FPR64:$rs2, FPR64:$rs3),
293 (FMADD_D $rs1, $rs2, $rs3, FRM_DYN)>;
295 // fmsub: rs1 * rs2 - rs3
296 def : Pat<(any_fma FPR64:$rs1, FPR64:$rs2, (fneg FPR64:$rs3)),
297 (FMSUB_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, FRM_DYN)>;
299 // fnmsub: -rs1 * rs2 + rs3
300 def : Pat<(any_fma (fneg FPR64:$rs1), FPR64:$rs2, FPR64:$rs3),
301 (FNMSUB_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, FRM_DYN)>;
303 // fnmadd: -rs1 * rs2 - rs3
304 def : Pat<(any_fma (fneg FPR64:$rs1), FPR64:$rs2, (fneg FPR64:$rs3)),
305 (FNMADD_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, FRM_DYN)>;
307 // fnmadd: -(rs1 * rs2 + rs3) (the nsz flag on the FMA)
308 def : Pat<(fneg (any_fma_nsz FPR64:$rs1, FPR64:$rs2, FPR64:$rs3)),
309 (FNMADD_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, FRM_DYN)>;
321 def : Pat<(fcopysign FPR64INX:$rs1, (fneg FPR64INX:$rs2)),
322 (FSGNJN_D_INX $rs1, $rs2)>;
323 def : Pat<(fcopysign FPR64INX:$rs1, FPR32INX:$rs2),
324 (FSGNJ_D_INX $rs1, (FCVT_D_S_INX $rs2, FRM_RNE))>;
325 def : Pat<(fcopysign FPR32INX:$rs1, FPR64INX:$rs2),
326 (FSGNJ_S_INX $rs1, (FCVT_S_D_INX $rs2, FRM_DYN))>;
328 // fmadd: rs1 * rs2 + rs3
329 def : Pat<(any_fma FPR64INX:$rs1, FPR64INX:$rs2, FPR64INX:$rs3),
330 (FMADD_D_INX $rs1, $rs2, $rs3, FRM_DYN)>;
332 // fmsub: rs1 * rs2 - rs3
333 def : Pat<(any_fma FPR64INX:$rs1, FPR64INX:$rs2, (fneg FPR64INX:$rs3)),
334 (FMSUB_D_INX FPR64INX:$rs1, FPR64INX:$rs2, FPR64INX:$rs3, FRM_DYN)>;
336 // fnmsub: -rs1 * rs2 + rs3
337 def : Pat<(any_fma (fneg FPR64INX:$rs1), FPR64INX:$rs2, FPR64INX:$rs3),
338 (FNMSUB_D_INX FPR64INX:$rs1, FPR64INX:$rs2, FPR64INX:$rs3, FRM_DYN)>;
340 // fnmadd: -rs1 * rs2 - rs3
341 def : Pat<(any_fma (fneg FPR64INX:$rs1), FPR64INX:$rs2, (fneg FPR64INX:$rs3)),
342 (FNMADD_D_INX FPR64INX:$rs1, FPR64INX:$rs2, FPR64INX:$rs3, FRM_DYN)>;
344 // fnmadd: -(rs1 * rs2 + rs3) (the nsz flag on the FMA)
345 def : Pat<(fneg (any_fma_nsz FPR64INX:$rs1, FPR64INX:$rs2, FPR64INX:$rs3)),
346 (FNMADD_D_INX FPR64INX:$rs1, FPR64INX:$rs2, FPR64INX:$rs3, FRM_DYN)>;
358 def : Pat<(fcopysign FPR64IN32X:$rs1, (fneg FPR64IN32X:$rs2)),
359 (FSGNJN_D_IN32X $rs1, $rs2)>;
360 def : Pat<(fcopysign FPR64IN32X:$rs1, FPR32INX:$rs2),
361 (FSGNJ_D_IN32X $rs1, (FCVT_D_S_INX $rs2, FRM_RNE))>;
362 def : Pat<(fcopysign FPR32INX:$rs1, FPR64IN32X:$rs2),
363 (FSGNJ_S_INX $rs1, (FCVT_S_D_IN32X $rs2, FRM_DYN))>;
365 // fmadd: rs1 * rs2 + rs3
366 def : Pat<(any_fma FPR64IN32X:$rs1, FPR64IN32X:$rs2, FPR64IN32X:$rs3),
367 (FMADD_D_IN32X $rs1, $rs2, $rs3, FRM_DYN)>;
369 // fmsub: rs1 * rs2 - rs3
370 def : Pat<(any_fma FPR64IN32X:$rs1, FPR64IN32X:$rs2, (fneg FPR64IN32X:$rs3)),
371 (FMSUB_D_IN32X FPR64IN32X:$rs1, FPR64IN32X:$rs2, FPR64IN32X:$rs3, FRM_DYN)>;
373 // fnmsub: -rs1 * rs2 + rs3
374 def : Pat<(any_fma (fneg FPR64IN32X:$rs1), FPR64IN32X:$rs2, FPR64IN32X:$rs3),
375 (FNMSUB_D_IN32X FPR64IN32X:$rs1, FPR64IN32X:$rs2, FPR64IN32X:$rs3, FRM_DYN)>;
377 // fnmadd: -rs1 * rs2 - rs3
378 def : Pat<(any_fma (fneg FPR64IN32X:$rs1), FPR64IN32X:$rs2, (fneg FPR64IN32X:$rs3)),
379 (FNMADD_D_IN32X FPR64IN32X:$rs1, FPR64IN32X:$rs2, FPR64IN32X:$rs3, FRM_DYN)>;
381 // fnmadd: -(rs1 * rs2 + rs3) (the nsz flag on the FMA)
382 def : Pat<(fneg (any_fma_nsz FPR64IN32X:$rs1, FPR64IN32X:$rs2, FPR64IN32X:$rs3)),
383 (FNMADD_D_IN32X FPR64IN32X:$rs1, FPR64IN32X:$rs2, FPR64IN32X:$rs3, FRM_DYN)>;
412 def : Pat<(XLenVT (strict_fsetccs FPR64:$rs1, FPR64:$rs2, SETEQ)),
413 (AND (XLenVT (FLE_D $rs1, $rs2)),
414 (XLenVT (FLE_D $rs2, $rs1)))>;
415 def : Pat<(XLenVT (strict_fsetccs FPR64:$rs1, FPR64:$rs2, SETOEQ)),
416 (AND (XLenVT (FLE_D $rs1, $rs2)),
417 (XLenVT (FLE_D $rs2, $rs1)))>;
432 def : Pat<(XLenVT (strict_fsetccs (f64 FPR64INX:$rs1), FPR64INX:$rs2, SETEQ)),
433 (AND (XLenVT (FLE_D_INX $rs1, $rs2)),
434 (XLenVT (FLE_D_INX $rs2, $rs1)))>;
435 def : Pat<(XLenVT (strict_fsetccs (f64 FPR64INX:$rs1), FPR64INX:$rs2, SETOEQ)),
436 (AND (XLenVT (FLE_D_INX $rs1, $rs2)),
437 (XLenVT (FLE_D_INX $rs2, $rs1)))>;
452 def : Pat<(XLenVT (strict_fsetccs FPR64IN32X:$rs1, FPR64IN32X:$rs2, SETEQ)),
453 (AND (XLenVT (FLE_D_IN32X $rs1, $rs2)),
454 (XLenVT (FLE_D_IN32X $rs2, $rs1)))>;
455 def : Pat<(XLenVT (strict_fsetccs FPR64IN32X:$rs1, FPR64IN32X:$rs2, SETOEQ)),
456 (AND (XLenVT (FLE_D_IN32X $rs1, $rs2)),
457 (XLenVT (FLE_D_IN32X $rs2, $rs1)))>;
524 def PseudoRV32ZdinxSD : Pseudo<(outs), (ins GPRPair:$rs2, GPRNoX0:$rs1, simm12:$imm12), []>;
525 def : Pat<(store (f64 GPRPair:$rs2), (AddrRegImmINX (XLenVT GPR:$rs1), simm12:$imm12)),
526 (PseudoRV32ZdinxSD GPRPair:$rs2, GPR:$rs1, simm12:$imm12)>;