Lines Matching refs:rs2
128 bits<5> rs2;
135 let Inst{4-0} = rs2;
168 bits<5> rs2;
174 let Inst{4-0} = rs2;
181 bits<5> rs2;
188 let Inst{4-0} = rs2;
195 bits<5> rs2;
201 let Inst{4-0} = rs2;
204 // Shift by register rs2.
209 bits<5> rs2;
216 let Inst{4-0} = rs2;
238 def rr : F3_Sr<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, IntRegs:$rs2),
239 !strconcat(OpcStr, " $rs1, $rs2, $rd"),
240 [(set VT:$rd, (OpNode VT:$rs1, i32:$rs2))],
266 bits<5> rs2;
268 let Inst{4-0} = rs2;
298 bits<5> rs2;
305 let Inst{4-0} = rs2;
313 bits<5> rs2;
319 let Inst{4-0} = rs2;
357 bits<5> rs2;
360 let Inst{4-0} = rs2;