Lines Matching refs:rs2
71 def any_fma_nsz : PatFrag<(ops node:$rs1, node:$rs2, node:$rs3),
72 (any_fma node:$rs1, node:$rs2, node:$rs3), [{
171 (ins rty:$rs2, GPRMem:$rs1, simm12:$imm12),
172 opcodestr, "$rs2, ${imm12}(${rs1})">,
180 (ins rty:$rs1, rty:$rs2, rty:$rs3, frmarg:$frm),
181 opcodestr, "$rd, $rs1, $rs2, $rs3$frm">;
193 (ins rty:$rs1, rty:$rs2), opcodestr, "$rd, $rs1, $rs2"> {
207 (ins rty:$rs1, rty:$rs2, frmarg:$frm), opcodestr,
208 "$rd, $rs1, $rs2$frm"> {
222 let rs2 = rs2val;
238 let rs2 = rs2val;
256 let rs2 = rs2val;
272 (ins rty:$rs1, rty:$rs2), opcodestr, "$rd, $rs1, $rs2"> {
282 : Pseudo<(outs Ty:$rd), (ins Ty:$rs1, Ty:$rs2, ixlenimm:$rm),
283 [(set Ty:$rd, (vt (riscv_fround Ty:$rs1, Ty:$rs2, timm:$rm)))]> {
400 def : InstAlias<"fsw $rs2, (${rs1})", (FSW FPR32:$rs2, GPR:$rs1, 0), 0>;
482 : Pat<(XLenVT (OpNode (vt Ty:$rs1), Ty:$rs2, Cond)), (Inst $rs1, $rs2)>;
492 : Pat<(OpNode (vt RegTy:$rs1), (vt RegTy:$rs2)), (Inst $rs1, $rs2)>;
502 : Pat<(OpNode (vt RegTy:$rs1), (vt RegTy:$rs2)), (Inst $rs1, $rs2, FRM_DYN)>;
546 def : Pat<(fcopysign FPR32:$rs1, (fneg FPR32:$rs2)), (FSGNJN_S $rs1, $rs2)>;
548 // fmadd: rs1 * rs2 + rs3
549 def : Pat<(any_fma FPR32:$rs1, FPR32:$rs2, FPR32:$rs3),
550 (FMADD_S $rs1, $rs2, $rs3, FRM_DYN)>;
552 // fmsub: rs1 * rs2 - rs3
553 def : Pat<(any_fma FPR32:$rs1, FPR32:$rs2, (fneg FPR32:$rs3)),
554 (FMSUB_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, FRM_DYN)>;
556 // fnmsub: -rs1 * rs2 + rs3
557 def : Pat<(any_fma (fneg FPR32:$rs1), FPR32:$rs2, FPR32:$rs3),
558 (FNMSUB_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, FRM_DYN)>;
560 // fnmadd: -rs1 * rs2 - rs3
561 def : Pat<(any_fma (fneg FPR32:$rs1), FPR32:$rs2, (fneg FPR32:$rs3)),
562 (FNMADD_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, FRM_DYN)>;
564 // fnmadd: -(rs1 * rs2 + rs3) (the nsz flag on the FMA)
565 def : Pat<(fneg (any_fma_nsz FPR32:$rs1, FPR32:$rs2, FPR32:$rs3)),
566 (FNMADD_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, FRM_DYN)>;
570 def : Pat<(fcopysign FPR32INX:$rs1, (fneg FPR32INX:$rs2)), (FSGNJN_S_INX $rs1, $rs2)>;
572 // fmadd: rs1 * rs2 + rs3
573 def : Pat<(any_fma FPR32INX:$rs1, FPR32INX:$rs2, FPR32INX:$rs3),
574 (FMADD_S_INX $rs1, $rs2, $rs3, FRM_DYN)>;
576 // fmsub: rs1 * rs2 - rs3
577 def : Pat<(any_fma FPR32INX:$rs1, FPR32INX:$rs2, (fneg FPR32INX:$rs3)),
578 (FMSUB_S_INX FPR32INX:$rs1, FPR32INX:$rs2, FPR32INX:$rs3, FRM_DYN)>;
580 // fnmsub: -rs1 * rs2 + rs3
581 def : Pat<(any_fma (fneg FPR32INX:$rs1), FPR32INX:$rs2, FPR32INX:$rs3),
582 (FNMSUB_S_INX FPR32INX:$rs1, FPR32INX:$rs2, FPR32INX:$rs3, FRM_DYN)>;
584 // fnmadd: -rs1 * rs2 - rs3
585 def : Pat<(any_fma (fneg FPR32INX:$rs1), FPR32INX:$rs2, (fneg FPR32INX:$rs3)),
586 (FNMADD_S_INX FPR32INX:$rs1, FPR32INX:$rs2, FPR32INX:$rs3, FRM_DYN)>;
588 // fnmadd: -(rs1 * rs2 + rs3) (the nsz flag on the FMA)
589 def : Pat<(fneg (any_fma_nsz FPR32INX:$rs1, FPR32INX:$rs2, FPR32INX:$rs3)),
590 (FNMADD_S_INX FPR32INX:$rs1, FPR32INX:$rs2, FPR32INX:$rs3, FRM_DYN)>;
619 def : Pat<(XLenVT (strict_fsetccs FPR32:$rs1, FPR32:$rs2, SETEQ)),
620 (AND (XLenVT (FLE_S $rs1, $rs2)),
621 (XLenVT (FLE_S $rs2, $rs1)))>;
622 def : Pat<(XLenVT (strict_fsetccs FPR32:$rs1, FPR32:$rs2, SETOEQ)),
623 (AND (XLenVT (FLE_S $rs1, $rs2)),
624 (XLenVT (FLE_S $rs2, $rs1)))>;
634 def : Pat<(XLenVT (strict_fsetccs FPR32INX:$rs1, FPR32INX:$rs2, SETEQ)),
635 (AND (XLenVT (FLE_S_INX $rs1, $rs2)),
636 (XLenVT (FLE_S_INX $rs2, $rs1)))>;
637 def : Pat<(XLenVT (strict_fsetccs FPR32INX:$rs1, FPR32INX:$rs2, SETOEQ)),
638 (AND (XLenVT (FLE_S_INX $rs1, $rs2)),
639 (XLenVT (FLE_S_INX $rs2, $rs1)))>;
679 def : Pat<(store (f32 FPR32INX:$rs2), (AddrRegImm (XLenVT GPR:$rs1), simm12:$imm12)),
680 (SW (COPY_TO_REGCLASS FPR32INX:$rs2, GPR), GPR:$rs1, simm12:$imm12)>;