Home
last modified time | relevance | path

Searched refs:getReg (Results 1 – 25 of 694) sorted by relevance

12345678910>>...28

/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86InstComments.cpp241 unsigned OpReg = MI->getOperand(OperandIndex).getReg(); in getRegOperandNumElts()
264 const char *MaskRegName = getRegName(MI->getOperand(MaskOp).getReg()); in printMasking()
302 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); in printFMAComments()
306 Mul2Name = getRegName(MI->getOperand(2).getReg()); in printFMAComments()
307 Mul1Name = getRegName(MI->getOperand(1).getReg()); in printFMAComments()
311 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); in printFMAComments()
312 Mul1Name = getRegName(MI->getOperand(1).getReg()); in printFMAComments()
317 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); in printFMAComments()
321 Mul2Name = getRegName(MI->getOperand(2).getReg()); in printFMAComments()
322 Mul1Name = getRegName(MI->getOperand(1).getReg()); in printFMAComments()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp87 return MIB.buildSub(Ty, Base, Ctlz).getReg(0); in buildLogBase2()
215 Register DstReg = MI.getOperand(0).getReg(); in matchCombineCopy()
216 Register SrcReg = MI.getOperand(1).getReg(); in matchCombineCopy()
220 Register DstReg = MI.getOperand(0).getReg(); in applyCombineCopy()
221 Register SrcReg = MI.getOperand(1).getReg(); in applyCombineCopy()
229 Register DstOp = MI.getOperand(0).getReg(); in matchFreezeOfSingleMaybePoisonOperand()
230 Register OrigOp = MI.getOperand(1).getReg(); in matchFreezeOfSingleMaybePoisonOperand()
256 if (isGuaranteedNotToBeUndefOrPoison(Operand.getReg(), MRI)) in matchFreezeOfSingleMaybePoisonOperand()
279 Register MaybePoisonOperandReg = MaybePoisonOperand->getReg(); in matchFreezeOfSingleMaybePoisonOperand()
290 Freeze.getReg(0)); in matchFreezeOfSingleMaybePoisonOperand()
[all …]
H A DGISelKnownBits.cpp43 return computeKnownAlignment(MI->getOperand(1).getReg(), Depth); in computeKnownAlignment()
64 return getKnownBits(MI.getOperand(0).getReg()); in getKnownBits()
199 computeKnownBitsImpl(MI.getOperand(i + 1).getReg(), Known2, DemandedElts, in computeKnownBitsImpl()
234 Register SrcReg = Src.getReg(); in computeKnownBitsImpl()
270 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known, DemandedElts, in computeKnownBitsImpl()
272 computeKnownBitsImpl(MI.getOperand(2).getReg(), Known2, DemandedElts, in computeKnownBitsImpl()
279 computeKnownBitsImpl(MI.getOperand(2).getReg(), Known, DemandedElts, in computeKnownBitsImpl()
281 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known2, DemandedElts, in computeKnownBitsImpl()
291 LLT Ty = MRI.getType(MI.getOperand(1).getReg()); in computeKnownBitsImpl()
297 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known, DemandedElts, in computeKnownBitsImpl()
[all …]
H A DCombinerHelperVectorOps.cpp37 Register Dst = Extract->getReg(0); in matchExtractVectorElement()
93 MachineInstr *Root = getDefIgnoringCopies(MO.getReg(), MRI); in matchExtractVectorElementWithDifferentIndices()
130 Register Dst = Extract->getReg(0); in matchExtractVectorElementWithDifferentIndices()
150 MachineInstr *Root = getDefIgnoringCopies(MO.getReg(), MRI); in matchExtractVectorElementWithBuildVector()
184 if (!MRI.hasOneNonDBGUse(Build->getReg(0)) || in matchExtractVectorElementWithBuildVector()
200 Register Dst = Extract->getReg(0); in matchExtractVectorElementWithBuildVector()
211 MachineInstr *Root = getDefIgnoringCopies(MO.getReg(), MRI); in matchExtractVectorElementWithBuildVectorTrunc()
245 if (!MRI.hasOneNonDBGUse(Build->getReg(0)) || in matchExtractVectorElementWithBuildVectorTrunc()
261 Register Dst = Extract->getReg(0); in matchExtractVectorElementWithBuildVectorTrunc()
279 cast<GExtractVectorElement>(getDefIgnoringCopies(MO.getReg(), MRI)); in matchExtractVectorElementWithShuffleVector()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerLowering.cpp161 Register Dst = MI.getOperand(0).getReg(); in matchREV()
162 Register Src = MI.getOperand(1).getReg(); in matchREV()
198 Register Dst = MI.getOperand(0).getReg(); in matchTRN()
203 Register V1 = MI.getOperand(1).getReg(); in matchTRN()
204 Register V2 = MI.getOperand(2).getReg(); in matchTRN()
219 Register Dst = MI.getOperand(0).getReg(); in matchUZP()
224 Register V1 = MI.getOperand(1).getReg(); in matchUZP()
225 Register V2 = MI.getOperand(2).getReg(); in matchUZP()
235 Register Dst = MI.getOperand(0).getReg(); in matchZip()
240 Register V1 = MI.getOperand(1).getReg(); in matchZip()
[all …]
H A DAArch64PreLegalizerCombiner.cpp52 Register DstReg = MI.getOperand(0).getReg(); in matchFConstantToConstant()
69 MIB.buildConstant(MI.getOperand(0).getReg(), ImmValAPF.bitcastToAPInt()); in applyFConstantToConstant()
84 Register LHS = MI.getOperand(2).getReg(); in matchICmpRedundantTrunc()
89 Register RHS = MI.getOperand(3).getReg(); in matchICmpRedundantTrunc()
117 MI.getOperand(3).setReg(WideZero.getReg(0)); in applyICmpRedundantTrunc()
154 Register Dst = MI.getOperand(0).getReg(); in matchFoldGlobalOffset()
160 UseInstr.getOperand(2).getReg(), MRI); in matchFoldGlobalOffset()
223 Register Dst = MI.getOperand(0).getReg(); in applyFoldGlobalOffset()
242 MachineInstr *I1 = getDefIgnoringCopies(MI.getOperand(1).getReg(), MRI); in matchExtAddvToUdotAddv()
243 Register DstReg = MI.getOperand(0).getReg(); in matchExtAddvToUdotAddv()
[all …]
H A DAArch64InstructionSelector.cpp719 return RegSequence.getReg(0); in createTuple()
752 getIConstantVRegValWithLookThrough(Root.getReg(), MRI, true); in getImmedFromMO()
771 LLT Ty = MRI.getType(I.getOperand(0).getReg()); in unsupportedBinOp()
789 if (!MO.getReg().isVirtual()) { in unsupportedBinOp()
794 const RegisterBank *OpBank = RBI.getRegBank(MO.getReg(), MRI, TRI); in unsupportedBinOp()
933 RegOp.setReg(SubRegCopy.getReg(0)); in copySubReg()
937 if (!I.getOperand(0).getReg().isPhysical()) in copySubReg()
938 RBI.constrainGenericRegister(I.getOperand(0).getReg(), *To, MRI); in copySubReg()
951 Register DstReg = I.getOperand(0).getReg(); in getRegClassesForCopy()
952 Register SrcReg = I.getOperand(1).getReg(); in getRegClassesForCopy()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPURegisterBankInfo.cpp129 Register DstReg = MI.getOperand(0).getReg(); in applyBank()
130 Register SrcReg = MI.getOperand(1).getReg(); in applyBank()
145 MRI.setRegBank(True.getReg(0), *NewBank); in applyBank()
146 MRI.setRegBank(False.getReg(0), *NewBank); in applyBank()
157 Register DstReg = MI.getOperand(0).getReg(); in applyBank()
168 Register Reg = Op.getReg(); in applyBank()
320 Register Reg = MI.getOperand(RegSrcOpIdx[I]).getReg(); in addMappingFromTable()
325 unsigned SizeI = getSizeInBits(MI.getOperand(I).getReg(), MRI, *TRI); in addMappingFromTable()
481 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI); in getInstrAlternativeMappings()
507 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI); in getInstrAlternativeMappings()
[all …]
H A DSIOptimizeExecMasking.cpp104 if (Src.isReg() && Src.getReg() == Exec) in isCopyFromExec()
105 return MI.getOperand(0).getReg(); in isCopyFromExec()
119 if (Dst.isReg() && Dst.getReg() == Exec && MI.getOperand(1).isReg()) in isCopyToExec()
120 return MI.getOperand(1).getReg(); in isCopyToExec()
144 if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC) in isLogicalOpOnExec()
145 return MI.getOperand(0).getReg(); in isLogicalOpOnExec()
147 if (Src2.isReg() && Src2.getReg() == AMDGPU::EXEC) in isLogicalOpOnExec()
148 return MI.getOperand(0).getReg(); in isLogicalOpOnExec()
160 if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC_LO) in isLogicalOpOnExec()
161 return MI.getOperand(0).getReg(); in isLogicalOpOnExec()
[all …]
H A DAMDGPULegalizerInfo.cpp588 const LLT PointerTy = MRI.getType(MO.getReg()); in castBufferRsrcFromV4I32()
606 B.buildExtractVectorElementConstant(S32, VectorReg, I).getReg(0); in castBufferRsrcFromV4I32()
637 PointerParts.push_back(Unmerged.getReg(I)); in castBufferRsrcToV4I32()
638 return B.buildBuildVector(VectorTy, PointerParts).getReg(0); in castBufferRsrcToV4I32()
640 Register Scalar = B.buildPtrToInt(ScalarTy, Pointer).getReg(0); in castBufferRsrcToV4I32()
641 return B.buildBitcast(VectorTy, Scalar).getReg(0); in castBufferRsrcToV4I32()
648 const LLT PointerTy = B.getMRI()->getType(MO.getReg()); in castBufferRsrcArgToV4I32()
652 MO.setReg(castBufferRsrcToV4I32(MO.getReg(), B)); in castBufferRsrcArgToV4I32()
2219 return B.buildUnmerge(S32, Dst).getReg(1); in getSegmentAperture()
2251 B.buildConstant(LLT::scalar(64), Offset).getReg(0)); in getSegmentAperture()
[all …]
H A DAMDGPUPostLegalizerCombiner.cpp163 if (!MRI.hasOneNonDBGUse(FCmp.getOperand(0).getReg())) in matchFMinFMaxLegacy()
168 Info.LHS = FCmp.getOperand(2).getReg(); in matchFMinFMaxLegacy()
169 Info.RHS = FCmp.getOperand(3).getReg(); in matchFMinFMaxLegacy()
170 Register True = MI.getOperand(2).getReg(); in matchFMinFMaxLegacy()
171 Register False = MI.getOperand(3).getReg(); in matchFMinFMaxLegacy()
209 Register DstReg = MI.getOperand(0).getReg(); in matchUCharToFloat()
217 Register SrcReg = MI.getOperand(1).getReg(); in matchUCharToFloat()
231 Register DstReg = MI.getOperand(0).getReg(); in applyUCharToFloat()
232 Register SrcReg = MI.getOperand(1).getReg(); in applyUCharToFloat()
236 SrcReg = B.buildAnyExtOrTrunc(S32, SrcReg).getReg(0); in applyUCharToFloat()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DGenericMachineInstrs.h38 Register getReg(unsigned Idx) const { return getOperand(Idx).getReg(); } in getReg() function
84 Register getPointerReg() const { return getOperand(1).getReg(); } in getPointerReg()
105 Register getDstReg() const { return getOperand(0).getReg(); } in getDstReg()
107 Register getWritebackReg() const { return getOperand(1).getReg(); } in getWritebackReg()
109 Register getBaseReg() const { return getOperand(2).getReg(); } in getBaseReg()
111 Register getOffsetReg() const { return getOperand(3).getReg(); } in getOffsetReg()
165 Register getWritebackReg() const { return getOperand(0).getReg(); } in getWritebackReg()
167 Register getValueReg() const { return getOperand(1).getReg(); } in getValueReg()
169 Register getBaseReg() const { return getOperand(2).getReg(); } in getBaseReg()
171 Register getOffsetReg() const { return getOperand(3).getReg(); } in getOffsetReg()
[all …]
H A DLegalizationArtifactCombiner.h67 Register DstReg = MI.getOperand(0).getReg(); in tryCombineAnyExt()
68 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg()); in tryCombineAnyExt()
126 Register DstReg = MI.getOperand(0).getReg(); in tryCombineZExt()
127 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg()); in tryCombineZExt()
143 SextSrc = Builder.buildSExtOrTrunc(DstTy, SextSrc).getReg(0); in tryCombineZExt()
145 TruncSrc = Builder.buildAnyExtOrTrunc(DstTy, TruncSrc).getReg(0); in tryCombineZExt()
201 Register DstReg = MI.getOperand(0).getReg(); in tryCombineSExt()
202 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg()); in tryCombineSExt()
214 TruncSrc = Builder.buildAnyExtOrTrunc(DstTy, TruncSrc).getReg(0); in tryCombineSExt()
266 Register DstReg = MI.getOperand(0).getReg(); in tryCombineTrunc()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCMIPeephole.cpp220 Register Reg = Op->getReg(); in getVRegDefOrNull()
279 getKnownLeadingZeroCount(MI->getOperand(1).getReg(), TII, MRI), in getKnownLeadingZeroCount()
280 getKnownLeadingZeroCount(MI->getOperand(2).getReg(), TII, MRI)); in getKnownLeadingZeroCount()
287 getKnownLeadingZeroCount(MI->getOperand(1).getReg(), TII, MRI), in getKnownLeadingZeroCount()
288 getKnownLeadingZeroCount(MI->getOperand(2).getReg(), TII, MRI)); in getKnownLeadingZeroCount()
363 Register RegOp = VisitedPHI->getOperand(PHIOp).getReg(); in collectUnprimedAccPHIs()
371 Register Reg = Instr->getOperand(1).getReg(); in collectUnprimedAccPHIs()
407 Register RegOp = PHI->getOperand(PHIOp).getReg(); in convertUnprimedAccPHIs()
414 assert(MRI->getRegClass(PHIInput->getOperand(1).getReg()) == in convertUnprimedAccPHIs()
432 PrimedAccPHI->getOperand(0).getReg(), false), in convertUnprimedAccPHIs()
[all …]
H A DPPCMacroFusion.cpp77 return Op1.getReg() == Op2.getReg(); in matchingRegOps()
109 return RA.getReg().isVirtual() || in checkOpConstraints()
110 (RA.getReg() != PPC::ZERO && RA.getReg() != PPC::ZERO8); in checkOpConstraints()
119 if (!RT.getReg().isVirtual()) in checkOpConstraints()
123 (RT.getReg() == PPC::ZERO || RT.getReg() == PPC::ZERO8)) in checkOpConstraints()
172 if (!BT.isReg() || (!BT.getReg().isVirtual() && BT.getReg() ! in checkOpConstraints()
[all...]
H A DPPCVSXCopy.cpp94 if ( IsVSReg(DstMO.getReg(), MRI) && in processBlock()
95 !IsVSReg(SrcMO.getReg(), MRI)) { in processBlock()
100 assert((IsF8Reg(SrcMO.getReg(), MRI) || in processBlock()
101 IsVSSReg(SrcMO.getReg(), MRI) || in processBlock()
102 IsVSFReg(SrcMO.getReg(), MRI)) && in processBlock()
115 } else if (!IsVSReg(DstMO.getReg(), MRI) && in processBlock()
116 IsVSReg(SrcMO.getReg(), MRI)) { in processBlock()
121 assert((IsF8Reg(DstMO.getReg(), MRI) || in processBlock()
122 IsVSFReg(DstMO.getReg(), MRI) || in processBlock()
123 IsVSSReg(DstMO.getReg(), MRI)) && in processBlock()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineCopyPropagation.cpp146 auto Dest = TRI.regunits(CopyOperands->Destination->getReg().asMCReg()); in invalidateRegister()
147 auto Src = TRI.regunits(CopyOperands->Source->getReg().asMCReg()); in invalidateRegister()
180 MCRegister Def = CopyOperands->Destination->getReg().asMCReg(); in clobberRegister()
181 MCRegister Src = CopyOperands->Source->getReg().asMCReg(); in clobberRegister()
233 MCRegister Src = CopyOperands->Source->getReg().asMCReg(); in trackCopy()
234 MCRegister Def = CopyOperands->Destination->getReg().asMCReg(); in trackCopy()
289 Register AvailSrc = CopyOperands->Source->getReg(); in findAvailBackwardCopy()
290 Register AvailDef = CopyOperands->Destination->getReg(); in findAvailBackwardCopy()
319 Register AvailSrc = CopyOperands->Source->getReg(); in findAvailCopy()
320 Register AvailDef = CopyOperands->Destination->getReg(); in findAvailCopy()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMInstPrinter.cpp97 printRegName(O, Reg.getReg()); in printInst()
105 printRegName(O, Reg.getReg()); in printInst()
113 printRegName(O, Reg.getReg()); in printInst()
121 printRegName(O, Reg.getReg()); in printInst()
139 printRegName(O, Dst.getReg()); in printInst()
141 printRegName(O, MO1.getReg()); in printInst()
144 printRegName(O, MO2.getReg()); in printInst()
161 printRegName(O, Dst.getReg()); in printInst()
163 printRegName(O, MO1.getReg()); in printInst()
180 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) { in printInst()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCDuplexInfo.cpp201 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
202 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
219 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
220 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
240 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
241 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
250 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
251 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
260 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
261 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64MIPeepholeOpt.cpp233 if (MI.getOperand(1).getReg() != AArch64::WZR) in visitORR()
236 MachineInstr *SrcMI = MRI->getUniqueVRegDef(MI.getOperand(2).getReg()); in visitORR()
251 SrcMI->getOperand(1).getReg().isVirtual()) { in visitORR()
253 MRI->getRegClass(SrcMI->getOperand(1).getReg()); in visitORR()
261 Register CpySrc = SrcMI->getOperand(1).getReg(); in visitORR()
269 TII->get(AArch64::FMOVSWr), SrcMI->getOperand(0).getReg()) in visitORR()
276 Register DefReg = MI.getOperand(0).getReg(); in visitORR()
277 Register SrcReg = MI.getOperand(2).getReg(); in visitORR()
297 Register DstReg = MI.getOperand(0).getReg(); in visitINSERT()
299 MachineInstr *SrcMI = MRI->getUniqueVRegDef(MI.getOperand(2).getReg()); in visitINSERT()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMRegisterBankInfo.cpp235 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
270 LLT LargeTy = MRI.getType(MI.getOperand(1).getReg()); in getInstrMapping()
280 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
293 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
300 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
314 LLT ToTy = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
315 LLT FromTy = MRI.getType(MI.getOperand(1).getReg()); in getInstrMapping()
323 LLT ToTy = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
324 LLT FromTy = MRI.getType(MI.getOperand(1).getReg()); in getInstrMapping()
333 LLT ToTy = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZAsmPrinter.cpp43 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
47 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
48 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg())) in lowerRILow()
57 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
61 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
62 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg())) in lowerRIHigh()
70 .addReg(MI->getOperand(0).getReg()) in lowerRIEfLow()
71 .addReg(MI->getOperand(1).getReg()) in lowerRIEfLow()
72 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg())) in lowerRIEfLow()
123 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg())) in lowerSubvectorLoad()
[all …]
H A DSystemZTargetStreamer.h37 if (A.getOperand(0).getReg() != B.getOperand(0).getReg()) in operator()
38 return A.getOperand(0).getReg() < B.getOperand(0).getReg(); in operator()
41 if (A.getOperand(3).getReg() != B.getOperand(3).getReg()) in operator()
42 return A.getOperand(3).getReg() < B.getOperand(3).getReg(); in operator()
H A DSystemZShortenInst.cpp79 Register Reg = MI.getOperand(0).getReg(); in shortenIIF()
111 if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16) { in shortenOn0()
121 if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 && in shortenOn01()
122 SystemZMC::getFirstReg(MI.getOperand(1).getReg()) < 16) { in shortenOn01()
133 if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 && in shortenOn001()
134 MI.getOperand(1).getReg() == MI.getOperand(0).getReg() && in shortenOn001()
135 SystemZMC::getFirstReg(MI.getOperand(2).getReg()) < 16) { in shortenOn001()
159 if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 && in shortenFPConv()
160 SystemZMC::getFirstReg(MI.getOperand(1).getReg()) < 16) { in shortenFPConv()
185 if (SystemZMC::getFirstReg(DstMO.getReg()) < 16 && in shortenFusedFPOp()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSplitDouble.cpp213 Register R = Op.getReg(); in isFixedInstr()
260 Register T = MO.getReg(); in partitionRegisters()
373 Register Rs = MI->getOperand(1).getReg(); in profit()
374 Register Rt = MI->getOperand(2).getReg(); in profit()
441 if (Op.isReg() && Part.count(Op.getReg())) in isProfitable()
500 Register PR = Cond[1].getReg(); in collectIndRegsForLoop()
508 CmpI = MRI->getVRegDef(CmpI->getOperand(1).getReg()); in collectIndRegsForLoop()
536 Register R = MD.getReg(); in collectIndRegsForLoop()
552 Register T = UseI->getOperand(0).getReg(); in collectIndRegsForLoop()
600 Register R = Op.getReg(); in createHalfInstr()
[all …]

12345678910>>...28