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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCScheduleP10.td83 // A BF pipeline may take from 7 to 36 cycles to complete.
84 // Some BF operations may keep the pipeline busy for up to 10 cycles.
114 // A BR pipeline may take 2 cycles to complete.
119 // A CY pipeline may take 7 cycles to complete.
124 // A DF pipeline may take from 13 to 174 cycles to complete.
125 // Some DF operations may keep the pipeline busy for up to 67 cycles.
210 // A DV pipeline may take from 20 to 83 cycles to complete.
211 // Some DV operations may keep the pipeline busy for up to 33 cycles.
262 // A DX pipeline may take 5 cycles to complete.
267 // A F2 pipeline may take 4 cycles t
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H A DPPCScheduleP9.td19 // Load latency is 4 or 5 cycles depending on the load. This latency assumes
21 // There are two instructions (lxvl, lxvll) that have a latency of 6 cycles.
23 // of instructions are 4 or 5 cycles.
26 // A total of 16 cycles to recover from a branch mispredict.
191 // An ALU may take either 2 or 3 cycles to complete the operation.
219 // A DIV unit may take from 5 to 40 cycles to complete.
220 // Some DIV operations may keep the unit busy for up to 8 cycles.
245 // A DP unit may take from 2 to 36 cycles to complete.
246 // Some DP operations keep the unit busy for up to 10 cycles.
330 // Loads can have 4, 5 or 6 cycles o
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H A DPPCScheduleP7.td
H A DP9InstrResources.td86 // Restricted Dispatch ALU operation for 3 cycles. The operation runs on a
104 // Standard Dispatch ALU operation for 3 cycles. Only one slice used.
121 // Standard Dispatch ALU operation for 2 cycles. Only one slice used.
176 // Restricted Dispatch ALU operation for 2 cycles. The operation runs on a
786 // Requires Load and ALU pieces totaling 6 cycles. The Load and ALU
795 // Requires Load and ALU pieces totaling 6 cycles. The Load and ALU
814 // Requires consecutive Load and ALU pieces totaling 6 cycles. The Load and ALU
826 // Requires consecutive Load and ALU pieces totaling 6 cycles. The Load and ALU
836 // Requires consecutive Load and ALU pieces totaling 7 cycles. The Load and ALU
846 // Requires consecutive Load (4 cycles) and ALU (3 cycles) pieces totaling 7
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H A DPPCSchedPredicates.td13 // Identify instructions that write BF pipelines with 7 cycles.
206 // Identify instructions that write CY pipelines with 7 cycles.
230 // Identify instructions that write MM pipelines with 10 cycles.
/freebsd/sys/contrib/device-tree/Bindings/bus/
H A Dqcom,ebi2.txt34 FIXME: the manual mentions "write precharge cycles" and "precharge cycles".
77 - qcom,xmem-recovery-cycles: recovery cycles is the time the memory continues to
82 - qcom,xmem-write-hold-cycles: write hold cycles, these are extra cycles
86 - qcom,xmem-write-delta-cycles: initial latency for write cycles inserted for
88 - qcom,xmem-read-delta-cycles: initial latency for read cycles inserted for the
90 - qcom,xmem-write-wait-cycles: number of wait cycles for every write access, 0=1
92 - qcom,xmem-read-wait-cycles: number of wait cycles for every read access, 0=1
99 - qcom,xmem-adv-to-oe-recovery-cycles: the number of cycles elapsed before an OE
101 2 means 2 cycles between ADV and OE. Valid values 0, 1, 2 or 3.
102 - qcom,xmem-read-hold-cycles: the length in cycles of the first segment of a
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H A Dnvidia,tegra20-gmi.txt56 - nvidia,snor-muxed-width: Number of cycles MUX address/data asserted on the
58 - nvidia,snor-hold-width: Number of cycles CE stays asserted after the
61 - nvidia,snor-adv-width: Number of cycles during which ADV stays asserted.
63 - nvidia,snor-ce-width: Number of cycles before CE is asserted.
65 - nvidia,snor-we-width: Number of cycles during which WE stays asserted.
67 - nvidia,snor-oe-width: Number of cycles during which OE stays asserted.
69 - nvidia,snor-wait-width: Number of cycles before READY is asserted.
/freebsd/sys/contrib/device-tree/Bindings/mtd/
H A Dfsmc-nand.txt15 byte 0 TCLR : CLE to RE delay in number of AHB clock cycles, only 4 bits
17 cycles.
19 byte 2 THIZ : number of HCLK clock cycles during which the data bus is
21 Only valid for write transactions. Zero means zero cycles,
22 255 means 255 cycles.
23 byte 3 THOLD : number of HCLK clock cycles to hold the address (and data
25 one cycle, 255 means 256 cycles.
26 byte 4 TWAIT : number of HCLK clock cycles to assert the command to the
28 255 means 256 cycles.
29 byte 5 TSET : number of HCLK clock cycles to assert the address before the
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleA9.td81 // No operand cycles
202 // FIXME: If address is 64-bit aligned, AGU cycles is 1.
346 // FIXME: If address is 64-bit aligned, AGU cycles is 1.
468 // Extra latency cycles since wbck is 2 cycles
477 // Extra latency cycles since wbck is 2 cycles
487 // Extra latency cycles since wbck is 4 cycles
496 // Extra latency cycles sinc
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/freebsd/sys/contrib/dev/athk/
H A Dhw.c144 u32 cycles, busy, rx, tx; in ath_hw_cycle_counters_update() local
151 cycles = REG_READ(ah, AR_CCCNT); in ath_hw_cycle_counters_update()
166 common->cc_ani.cycles += cycles; in ath_hw_cycle_counters_update()
171 common->cc_survey.cycles += cycles; in ath_hw_cycle_counters_update()
183 listen_time = (cc->cycles - cc->rx_frame - cc->tx_frame) / in ath_hw_get_listen_time()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedThunderX3T110.td21 let MispredictPenalty = 12; // Extra cycles for mispredicted branch.
119 // 3 cycles on I1.
125 // 4 cycles on I1.
131 // 5 cycles on I1.
137 // 7 cycles on I1.
143 // 23 cycles on I1.
150 // 39 cycles on I1.
163 // 8 cycles on I2/I3
175 // 8 cycles on I1/I2/I3
187 // 2 cycles o
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H A DAArch64SchedThunderX2T99.td22 let MispredictPenalty = 12; // Extra cycles for mispredicted branch.
95 // 3 cycles on I1.
101 // 1 cycles on I2.
107 // 4 cycles on I1.
113 // 23 cycles on I1.
120 // 39 cycles on I1.
133 // 2 cycles on I0, I1, or I2.
139 // 4 cycles on I0, I1, or I2.
145 // 5 cycles on I0, I1, or I2.
151 // 5 cycles o
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H A DAArch64SchedCyclone.td18 let MispredictPenalty = 16; // 14-19 cycles are typical.
156 // consumes a shift pipeline for two cycles.
207 // 32-bit divide takes 7-13 cycles. 10 cycles covers a 20-bit quotient.
208 // The ID pipe is consumed for 2 cycles: issue and writeback.
214 // 64-bit divide takes 7-21 cycles. 13 cycles covers a 32-bit quotient.
215 // The ID pipe is consumed for 2 cycles: issue and writeback.
226 // Integer loads take 4 cycles and use one LS unit for one cycle.
231 // Store-load forwarding is 4 cycles
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/freebsd/sys/contrib/ncsw/inc/
H A Dncsw_ext.h154 #define CYCLES_TO_USEC(cycles,clk) ((cycles) / (clk)) argument
158 #define CYCLES_TO_NSEC(cycles,clk) (((cycles) * 1000) / (clk)) argument
162 #define CYCLES_TO_PSEC(cycles,clk) (((cycles) * 1000000) / (clk)) argument
/freebsd/contrib/bmake/unit-tests/
H A Ddotwait.exp27 make: Graph cycles through `cycle.2.99'
28 make: Graph cycles through `cycle.2.98'
29 make: Graph cycles through `cycle.2.97'
/freebsd/sys/crypto/openssl/arm/
H A Dsha512-armv4.S22 @ by gcc 3.4 and it spends ~72 clock cycles per byte [on single-issue
28 @ Cortex A8 core and ~40 cycles per processed byte.
33 @ improvement on Coxtex A8 core and ~38 cycles per byte.
38 @ one byte in 23.3 cycles or ~60% faster than integer-only code.
H A Daes-armv4.S25 @ is endian-neutral. The performance is ~42 cycles/byte for 128-bit
35 @ Cortex A8 core and ~25 cycles per byte processed with 128-bit key.
40 @ improvement on Cortex A8 core and ~21.5 cycles per byte.
/freebsd/sys/contrib/device-tree/Bindings/c6x/
H A Dclocks.txt24 - ti,c64x+pll-bypass-delay: CPU cycles to delay when entering bypass mode
26 - ti,c64x+pll-reset-delay: CPU cycles to delay after PLL reset
28 - ti,c64x+pll-lock-delay: CPU cycles to delay after PLL frequency change
/freebsd/sys/contrib/device-tree/src/arm/intel/ixp/
H A Dintel-ixp42x-gateworks-gw2348.dts89 intel,ixp4xx-eb-t1 = <3>; // 3 cycles extra address phase
90 intel,ixp4xx-eb-t2 = <3>; // 3 cycles extra setup phase
91 intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase
92 intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase
93 intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase
H A Dintel-ixp43x-gateworks-gw2358.dts105 intel,ixp4xx-eb-t1 = <3>; // 3 cycles extra address phase
106 intel,ixp4xx-eb-t2 = <3>; // 3 cycles extra setup phase
107 intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase
108 intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase
109 intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase
/freebsd/sys/contrib/device-tree/Bindings/misc/
H A Difm-csi.txt14 - ifm,csi-wait-cycles: sensor bus wait cycles
34 ifm,csi-wait-cycles = <0>;
/freebsd/sys/contrib/device-tree/Bindings/regulator/
H A Dti-abb-regulator.txt22 - ti,clock-cycles: SoC specific data about count of system ti,clock-cycles used for
24 cycles for SR2_WTCNT_VALUE).
79 ti,clock-cycles = <8>;
99 ti,clock-cycles = <16>;
126 ti,clock-cycles = <16>;
/freebsd/sys/contrib/device-tree/Bindings/media/i2c/
H A Dtda1997x.txt11 - YUV422 BT656 8bit per component (8 bits total): YCbCr[11:4] (2-cycles)
12 - YUV422 BT656 10bit per component (10 bits total): YCbCr[11:2] (2-cycles)
13 - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
19 - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
161 * 2 pixclk cycles.
/freebsd/sys/contrib/device-tree/Bindings/display/exynos/
H A Dsamsung-fimd.txt46 - cs-setup: clock cycles for the active period of address signal is enabled
49 - wr-setup: clock cycles for the active period of CS signal is enabled until
52 - wr-active: clock cycles for the active period of CS is enabled.
54 - wr-hold: clock cycles for the active period of CS is disabled until write
/freebsd/sys/dev/pms/freebsd/driver/ini/src/
H A Dosapi.c589 unsigned long long cycles = get_cycles(); in ostiEnter() local
598 pCard->totalCycles[io][prev_layer] += cycles - in ostiEnter()
601 pCard->enterCycles[io][layer] = cycles; in ostiEnter()
617 unsigned long long cycles = get_cycles(); in ostiLeave() local
625 pCard->totalCycles[io][layer] += cycles - pCard->enterCycles[io][layer]; in ostiLeave()
628 cycles; in ostiLeave()

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