Lines Matching refs:cycles

18   let MispredictPenalty = 16; // 14-19 cycles are typical.
156 // consumes a shift pipeline for two cycles.
207 // 32-bit divide takes 7-13 cycles. 10 cycles covers a 20-bit quotient.
208 // The ID pipe is consumed for 2 cycles: issue and writeback.
214 // 64-bit divide takes 7-21 cycles. 13 cycles covers a 32-bit quotient.
215 // The ID pipe is consumed for 2 cycles: issue and writeback.
226 // Integer loads take 4 cycles and use one LS unit for one cycle.
231 // Store-load forwarding is 4 cycles.
307 // Simple vector operations take 2 cycles.
317 // Simple floating-point operations take 2 cycles.
583 // SCVT/UCVT S/D, Rd = VLD5+V4: 9 cycles.
587 // FCVT Rd, S/D = V6+LD4: 10 cycles
617 // Loading into the vector unit takes 5 cycles vs 4 for integer loads.
622 // Store-load forwarding is 4 cycles.
637 // Vd is read 5 cycles after issuing the vector load.