10b57cec5SDimitry Andric//=- ARMScheduleA9.td - ARM Cortex-A9 Scheduling Definitions -*- tablegen -*-=// 20b57cec5SDimitry Andric// 30b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric// 70b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric// 90b57cec5SDimitry Andric// This file defines the itinerary class data for the ARM Cortex A9 processors. 100b57cec5SDimitry Andric// 110b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 120b57cec5SDimitry Andric 130b57cec5SDimitry Andric// ===---------------------------------------------------------------------===// 140b57cec5SDimitry Andric// This section contains legacy support for itineraries. This is 150b57cec5SDimitry Andric// required until SD and PostRA schedulers are replaced by MachineScheduler. 160b57cec5SDimitry Andric 170b57cec5SDimitry Andric// 180b57cec5SDimitry Andric// Ad-hoc scheduling information derived from pretty vague "Cortex-A9 Technical 190b57cec5SDimitry Andric// Reference Manual". 200b57cec5SDimitry Andric// 210b57cec5SDimitry Andric// Functional units 220b57cec5SDimitry Andricdef A9_Issue0 : FuncUnit; // Issue 0 230b57cec5SDimitry Andricdef A9_Issue1 : FuncUnit; // Issue 1 240b57cec5SDimitry Andricdef A9_Branch : FuncUnit; // Branch 250b57cec5SDimitry Andricdef A9_ALU0 : FuncUnit; // ALU / MUL pipeline 0 260b57cec5SDimitry Andricdef A9_ALU1 : FuncUnit; // ALU pipeline 1 270b57cec5SDimitry Andricdef A9_AGU : FuncUnit; // Address generation unit for ld / st 280b57cec5SDimitry Andricdef A9_NPipe : FuncUnit; // NEON pipeline 290b57cec5SDimitry Andricdef A9_MUX0 : FuncUnit; // AGU + NEON/FPU multiplexer 300b57cec5SDimitry Andricdef A9_LSUnit : FuncUnit; // L/S Unit 310b57cec5SDimitry Andricdef A9_DRegsVFP: FuncUnit; // FP register set, VFP side 320b57cec5SDimitry Andricdef A9_DRegsN : FuncUnit; // FP register set, NEON side 330b57cec5SDimitry Andric 340b57cec5SDimitry Andric// Bypasses 350b57cec5SDimitry Andricdef A9_LdBypass : Bypass; 360b57cec5SDimitry Andric 370b57cec5SDimitry Andricdef CortexA9Itineraries : ProcessorItineraries< 380b57cec5SDimitry Andric [A9_Issue0, A9_Issue1, A9_Branch, A9_ALU0, A9_ALU1, A9_AGU, A9_NPipe, A9_MUX0, 390b57cec5SDimitry Andric A9_LSUnit, A9_DRegsVFP, A9_DRegsN], 400b57cec5SDimitry Andric [A9_LdBypass], [ 410b57cec5SDimitry Andric // Two fully-pipelined integer ALU pipelines 420b57cec5SDimitry Andric 430b57cec5SDimitry Andric // 440b57cec5SDimitry Andric // Move instructions, unconditional 450b57cec5SDimitry Andric InstrItinData<IIC_iMOVi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 460b57cec5SDimitry Andric InstrStage<1, [A9_ALU0, A9_ALU1]>], [1]>, 470b57cec5SDimitry Andric InstrItinData<IIC_iMOVr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 480b57cec5SDimitry Andric InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>, 490b57cec5SDimitry Andric InstrItinData<IIC_iMOVsi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 500b57cec5SDimitry Andric InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>, 510b57cec5SDimitry Andric InstrItinData<IIC_iMOVsr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 520b57cec5SDimitry Andric InstrStage<2, [A9_ALU0, A9_ALU1]>], [2, 1, 1]>, 530b57cec5SDimitry Andric InstrItinData<IIC_iMOVix2 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 540b57cec5SDimitry Andric InstrStage<1, [A9_ALU0, A9_ALU1]>, 550b57cec5SDimitry Andric InstrStage<1, [A9_ALU0, A9_ALU1]>], [2]>, 560b57cec5SDimitry Andric InstrItinData<IIC_iMOVix2addpc,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 570b57cec5SDimitry Andric InstrStage<1, [A9_ALU0, A9_ALU1]>, 580b57cec5SDimitry Andric InstrStage<1, [A9_ALU0, A9_ALU1]>, 590b57cec5SDimitry Andric InstrStage<1, [A9_ALU0, A9_ALU1]>], [3]>, 600b57cec5SDimitry Andric InstrItinData<IIC_iMOVix2ld,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 610b57cec5SDimitry Andric InstrStage<1, [A9_ALU0, A9_ALU1]>, 620b57cec5SDimitry Andric InstrStage<1, [A9_ALU0, A9_ALU1]>, 630b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 640b57cec5SDimitry Andric InstrStage<1, [A9_AGU], 0>, 650b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], [5]>, 660b57cec5SDimitry Andric // 670b57cec5SDimitry Andric // MVN instructions 680b57cec5SDimitry Andric InstrItinData<IIC_iMVNi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 690b57cec5SDimitry Andric InstrStage<1, [A9_ALU0, A9_ALU1]>], 700b57cec5SDimitry Andric [1]>, 710b57cec5SDimitry Andric InstrItinData<IIC_iMVNr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 720b57cec5SDimitry Andric InstrStage<1, [A9_ALU0, A9_ALU1]>], 730b57cec5SDimitry Andric [1, 1], [NoBypass, A9_LdBypass]>, 740b57cec5SDimitry Andric InstrItinData<IIC_iMVNsi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 750b57cec5SDimitry Andric InstrStage<2, [A9_ALU0, A9_ALU1]>], 760b57cec5SDimitry Andric [2, 1]>, 770b57cec5SDimitry Andric InstrItinData<IIC_iMVNsr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 780b57cec5SDimitry Andric InstrStage<3, [A9_ALU0, A9_ALU1]>], 790b57cec5SDimitry Andric [3, 1, 1]>, 800b57cec5SDimitry Andric // 810b57cec5SDimitry Andric // No operand cycles 820b57cec5SDimitry Andric InstrItinData<IIC_iALUx , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 830b57cec5SDimitry Andric InstrStage<1, [A9_ALU0, A9_ALU1]>]>, 840b57cec5SDimitry Andric // 850b57cec5SDimitry Andric // Binary Instructions that produce a result 860b57cec5SDimitry Andric InstrItinData<IIC_iALUi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 870b57cec5SDimitry Andric InstrStage<1, [A9_ALU0, A9_ALU1]>], 880b57cec5SDimitry Andric [1, 1], [NoBypass, A9_LdBypass]>, 890b57cec5SDimitry Andric InstrItinData<IIC_iALUr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 900b57cec5SDimitry Andric InstrStage<1, [A9_ALU0, A9_ALU1]>], 910b57cec5SDimitry Andric [1, 1, 1], [NoBypass, A9_LdBypass, A9_LdBypass]>, 920b57cec5SDimitry Andric InstrItinData<IIC_iALUsi, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 930b57cec5SDimitry Andric InstrStage<2, [A9_ALU0, A9_ALU1]>], 940b57cec5SDimitry Andric [2, 1, 1], [NoBypass, A9_LdBypass, NoBypass]>, 950b57cec5SDimitry Andric InstrItinData<IIC_iALUsir,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 960b57cec5SDimitry Andric InstrStage<2, [A9_ALU0, A9_ALU1]>], 970b57cec5SDimitry Andric [2, 1, 1], [NoBypass, NoBypass, A9_LdBypass]>, 980b57cec5SDimitry Andric InstrItinData<IIC_iALUsr, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 990b57cec5SDimitry Andric InstrStage<3, [A9_ALU0, A9_ALU1]>], 1000b57cec5SDimitry Andric [3, 1, 1, 1], 1010b57cec5SDimitry Andric [NoBypass, A9_LdBypass, NoBypass, NoBypass]>, 1020b57cec5SDimitry Andric // 1030b57cec5SDimitry Andric // Bitwise Instructions that produce a result 1040b57cec5SDimitry Andric InstrItinData<IIC_iBITi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 1050b57cec5SDimitry Andric InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>, 1060b57cec5SDimitry Andric InstrItinData<IIC_iBITr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 1070b57cec5SDimitry Andric InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1, 1]>, 1080b57cec5SDimitry Andric InstrItinData<IIC_iBITsi, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 1090b57cec5SDimitry Andric InstrStage<2, [A9_ALU0, A9_ALU1]>], [2, 1, 1]>, 1100b57cec5SDimitry Andric InstrItinData<IIC_iBITsr, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 1110b57cec5SDimitry Andric InstrStage<3, [A9_ALU0, A9_ALU1]>], [3, 1, 1, 1]>, 1120b57cec5SDimitry Andric // 1130b57cec5SDimitry Andric // Unary Instructions that produce a result 1140b57cec5SDimitry Andric 1150b57cec5SDimitry Andric // CLZ, RBIT, etc. 1160b57cec5SDimitry Andric InstrItinData<IIC_iUNAr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 1170b57cec5SDimitry Andric InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>, 1180b57cec5SDimitry Andric 1190b57cec5SDimitry Andric // BFC, BFI, UBFX, SBFX 1200b57cec5SDimitry Andric InstrItinData<IIC_iUNAsi, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 1210b57cec5SDimitry Andric InstrStage<2, [A9_ALU0, A9_ALU1]>], [2, 1]>, 1220b57cec5SDimitry Andric 1230b57cec5SDimitry Andric // 1240b57cec5SDimitry Andric // Zero and sign extension instructions 1250b57cec5SDimitry Andric InstrItinData<IIC_iEXTr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 1260b57cec5SDimitry Andric InstrStage<1, [A9_ALU0, A9_ALU1]>], [2, 1]>, 1270b57cec5SDimitry Andric InstrItinData<IIC_iEXTAr, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 1280b57cec5SDimitry Andric InstrStage<2, [A9_ALU0, A9_ALU1]>], [3, 1, 1]>, 1290b57cec5SDimitry Andric InstrItinData<IIC_iEXTAsr,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 1300b57cec5SDimitry Andric InstrStage<3, [A9_ALU0, A9_ALU1]>], [3, 1, 1, 1]>, 1310b57cec5SDimitry Andric // 1320b57cec5SDimitry Andric // Compare instructions 1330b57cec5SDimitry Andric InstrItinData<IIC_iCMPi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 1340b57cec5SDimitry Andric InstrStage<1, [A9_ALU0, A9_ALU1]>], 1350b57cec5SDimitry Andric [1], [A9_LdBypass]>, 1360b57cec5SDimitry Andric InstrItinData<IIC_iCMPr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 1370b57cec5SDimitry Andric InstrStage<1, [A9_ALU0, A9_ALU1]>], 1380b57cec5SDimitry Andric [1, 1], [A9_LdBypass, A9_LdBypass]>, 1390b57cec5SDimitry Andric InstrItinData<IIC_iCMPsi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 1400b57cec5SDimitry Andric InstrStage<2, [A9_ALU0, A9_ALU1]>], 1410b57cec5SDimitry Andric [1, 1], [A9_LdBypass, NoBypass]>, 1420b57cec5SDimitry Andric InstrItinData<IIC_iCMPsr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 1430b57cec5SDimitry Andric InstrStage<3, [A9_ALU0, A9_ALU1]>], 1440b57cec5SDimitry Andric [1, 1, 1], [A9_LdBypass, NoBypass, NoBypass]>, 1450b57cec5SDimitry Andric // 1460b57cec5SDimitry Andric // Test instructions 1470b57cec5SDimitry Andric InstrItinData<IIC_iTSTi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 1480b57cec5SDimitry Andric InstrStage<1, [A9_ALU0, A9_ALU1]>], [1]>, 1490b57cec5SDimitry Andric InstrItinData<IIC_iTSTr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 1500b57cec5SDimitry Andric InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>, 1510b57cec5SDimitry Andric InstrItinData<IIC_iTSTsi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 1520b57cec5SDimitry Andric InstrStage<2, [A9_ALU0, A9_ALU1]>], [1, 1]>, 1530b57cec5SDimitry Andric InstrItinData<IIC_iTSTsr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 1540b57cec5SDimitry Andric InstrStage<3, [A9_ALU0, A9_ALU1]>], [1, 1, 1]>, 1550b57cec5SDimitry Andric // 1560b57cec5SDimitry Andric // Move instructions, conditional 1570b57cec5SDimitry Andric // FIXME: Correctly model the extra input dep on the destination. 1580b57cec5SDimitry Andric InstrItinData<IIC_iCMOVi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 1590b57cec5SDimitry Andric InstrStage<1, [A9_ALU0, A9_ALU1]>], [1]>, 1600b57cec5SDimitry Andric InstrItinData<IIC_iCMOVr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 1610b57cec5SDimitry Andric InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>, 1620b57cec5SDimitry Andric InstrItinData<IIC_iCMOVsi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 1630b57cec5SDimitry Andric InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>, 1640b57cec5SDimitry Andric InstrItinData<IIC_iCMOVsr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 1650b57cec5SDimitry Andric InstrStage<2, [A9_ALU0, A9_ALU1]>], [2, 1, 1]>, 1660b57cec5SDimitry Andric InstrItinData<IIC_iCMOVix2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 1670b57cec5SDimitry Andric InstrStage<1, [A9_ALU0, A9_ALU1]>, 1680b57cec5SDimitry Andric InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 1690b57cec5SDimitry Andric InstrStage<1, [A9_ALU0, A9_ALU1]>], [2]>, 1700b57cec5SDimitry Andric 1710b57cec5SDimitry Andric // Integer multiply pipeline 1720b57cec5SDimitry Andric // 1730b57cec5SDimitry Andric InstrItinData<IIC_iMUL16 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 1740b57cec5SDimitry Andric InstrStage<2, [A9_ALU0]>], [3, 1, 1]>, 1750b57cec5SDimitry Andric InstrItinData<IIC_iMAC16 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 1760b57cec5SDimitry Andric InstrStage<2, [A9_ALU0]>], 1770b57cec5SDimitry Andric [3, 1, 1, 1]>, 1780b57cec5SDimitry Andric InstrItinData<IIC_iMUL32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 1790b57cec5SDimitry Andric InstrStage<2, [A9_ALU0]>], [4, 1, 1]>, 1800b57cec5SDimitry Andric InstrItinData<IIC_iMAC32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 1810b57cec5SDimitry Andric InstrStage<2, [A9_ALU0]>], 1820b57cec5SDimitry Andric [4, 1, 1, 1]>, 1830b57cec5SDimitry Andric InstrItinData<IIC_iMUL64 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 1840b57cec5SDimitry Andric InstrStage<3, [A9_ALU0]>], [4, 5, 1, 1]>, 1850b57cec5SDimitry Andric InstrItinData<IIC_iMAC64 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 1860b57cec5SDimitry Andric InstrStage<3, [A9_ALU0]>], 1870b57cec5SDimitry Andric [4, 5, 1, 1]>, 1880b57cec5SDimitry Andric // Integer load pipeline 1890b57cec5SDimitry Andric // FIXME: The timings are some rough approximations 1900b57cec5SDimitry Andric // 1910b57cec5SDimitry Andric // Immediate offset 1920b57cec5SDimitry Andric InstrItinData<IIC_iLoad_i , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 1930b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 1940b57cec5SDimitry Andric InstrStage<1, [A9_AGU], 0>, 1950b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], 1960b57cec5SDimitry Andric [3, 1], [A9_LdBypass]>, 1970b57cec5SDimitry Andric InstrItinData<IIC_iLoad_bh_i, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 1980b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 1990b57cec5SDimitry Andric InstrStage<2, [A9_AGU], 0>, 2000b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], 2010b57cec5SDimitry Andric [4, 1], [A9_LdBypass]>, 2020b57cec5SDimitry Andric // FIXME: If address is 64-bit aligned, AGU cycles is 1. 2030b57cec5SDimitry Andric InstrItinData<IIC_iLoad_d_i , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 2040b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 2050b57cec5SDimitry Andric InstrStage<2, [A9_AGU], 0>, 2060b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], 2070b57cec5SDimitry Andric [3, 3, 1], [A9_LdBypass]>, 2080b57cec5SDimitry Andric // 2090b57cec5SDimitry Andric // Register offset 2100b57cec5SDimitry Andric InstrItinData<IIC_iLoad_r , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 2110b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 2120b57cec5SDimitry Andric InstrStage<1, [A9_AGU], 0>, 2130b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], 2140b57cec5SDimitry Andric [3, 1, 1], [A9_LdBypass]>, 2150b57cec5SDimitry Andric InstrItinData<IIC_iLoad_bh_r, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 2160b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 2170b57cec5SDimitry Andric InstrStage<2, [A9_AGU], 0>, 2180b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], 2190b57cec5SDimitry Andric [4, 1, 1], [A9_LdBypass]>, 2200b57cec5SDimitry Andric InstrItinData<IIC_iLoad_d_r , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 2210b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 2220b57cec5SDimitry Andric InstrStage<2, [A9_AGU], 0>, 2230b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], 2240b57cec5SDimitry Andric [3, 3, 1, 1], [A9_LdBypass]>, 2250b57cec5SDimitry Andric // 2260b57cec5SDimitry Andric // Scaled register offset 2270b57cec5SDimitry Andric InstrItinData<IIC_iLoad_si , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 2280b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 2290b57cec5SDimitry Andric InstrStage<1, [A9_AGU], 0>, 2300b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit], 0>], 2310b57cec5SDimitry Andric [4, 1, 1], [A9_LdBypass]>, 2320b57cec5SDimitry Andric InstrItinData<IIC_iLoad_bh_si,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 2330b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 2340b57cec5SDimitry Andric InstrStage<2, [A9_AGU], 0>, 2350b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], 2360b57cec5SDimitry Andric [5, 1, 1], [A9_LdBypass]>, 2370b57cec5SDimitry Andric // 2380b57cec5SDimitry Andric // Immediate offset with update 2390b57cec5SDimitry Andric InstrItinData<IIC_iLoad_iu , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 2400b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 2410b57cec5SDimitry Andric InstrStage<1, [A9_AGU], 0>, 2420b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], 2430b57cec5SDimitry Andric [3, 2, 1], [A9_LdBypass]>, 2440b57cec5SDimitry Andric InstrItinData<IIC_iLoad_bh_iu,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 2450b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 2460b57cec5SDimitry Andric InstrStage<2, [A9_AGU], 0>, 2470b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], 2480b57cec5SDimitry Andric [4, 3, 1], [A9_LdBypass]>, 2490b57cec5SDimitry Andric // 2500b57cec5SDimitry Andric // Register offset with update 2510b57cec5SDimitry Andric InstrItinData<IIC_iLoad_ru , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 2520b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 2530b57cec5SDimitry Andric InstrStage<1, [A9_AGU], 0>, 2540b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], 2550b57cec5SDimitry Andric [3, 2, 1, 1], [A9_LdBypass]>, 2560b57cec5SDimitry Andric InstrItinData<IIC_iLoad_bh_ru,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 2570b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 2580b57cec5SDimitry Andric InstrStage<2, [A9_AGU], 0>, 2590b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], 2600b57cec5SDimitry Andric [4, 3, 1, 1], [A9_LdBypass]>, 2610b57cec5SDimitry Andric InstrItinData<IIC_iLoad_d_ru, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 2620b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 2630b57cec5SDimitry Andric InstrStage<2, [A9_AGU], 0>, 2640b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], 2650b57cec5SDimitry Andric [3, 3, 1, 1], [A9_LdBypass]>, 2660b57cec5SDimitry Andric // 2670b57cec5SDimitry Andric // Scaled register offset with update 2680b57cec5SDimitry Andric InstrItinData<IIC_iLoad_siu , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 2690b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 2700b57cec5SDimitry Andric InstrStage<1, [A9_AGU], 0>, 2710b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], 2720b57cec5SDimitry Andric [4, 3, 1, 1], [A9_LdBypass]>, 2730b57cec5SDimitry Andric InstrItinData<IIC_iLoad_bh_siu,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 2740b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 2750b57cec5SDimitry Andric InstrStage<2, [A9_AGU], 0>, 2760b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], 2770b57cec5SDimitry Andric [5, 4, 1, 1], [A9_LdBypass]>, 2780b57cec5SDimitry Andric // 2790b57cec5SDimitry Andric // Load multiple, def is the 5th operand. 2800b57cec5SDimitry Andric // FIXME: This assumes 3 to 4 registers. 2810b57cec5SDimitry Andric InstrItinData<IIC_iLoad_m , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 2820b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 2830b57cec5SDimitry Andric InstrStage<2, [A9_AGU], 1>, 2840b57cec5SDimitry Andric InstrStage<2, [A9_LSUnit]>], 2850b57cec5SDimitry Andric [1, 1, 1, 1, 3], 2860b57cec5SDimitry Andric [NoBypass, NoBypass, NoBypass, NoBypass, A9_LdBypass], 2870b57cec5SDimitry Andric -1>, // dynamic uops 2880b57cec5SDimitry Andric // 2890b57cec5SDimitry Andric // Load multiple + update, defs are the 1st and 5th operands. 2900b57cec5SDimitry Andric InstrItinData<IIC_iLoad_mu , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 2910b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 2920b57cec5SDimitry Andric InstrStage<2, [A9_AGU], 1>, 2930b57cec5SDimitry Andric InstrStage<2, [A9_LSUnit]>], 2940b57cec5SDimitry Andric [2, 1, 1, 1, 3], 2950b57cec5SDimitry Andric [NoBypass, NoBypass, NoBypass, NoBypass, A9_LdBypass], 2960b57cec5SDimitry Andric -1>, // dynamic uops 2970b57cec5SDimitry Andric // 2980b57cec5SDimitry Andric // Load multiple plus branch 2990b57cec5SDimitry Andric InstrItinData<IIC_iLoad_mBr, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 3000b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 3010b57cec5SDimitry Andric InstrStage<1, [A9_AGU], 1>, 3020b57cec5SDimitry Andric InstrStage<2, [A9_LSUnit]>, 3030b57cec5SDimitry Andric InstrStage<1, [A9_Branch]>], 3040b57cec5SDimitry Andric [1, 2, 1, 1, 3], 3050b57cec5SDimitry Andric [NoBypass, NoBypass, NoBypass, NoBypass, A9_LdBypass], 3060b57cec5SDimitry Andric -1>, // dynamic uops 3070b57cec5SDimitry Andric // 3080b57cec5SDimitry Andric // Pop, def is the 3rd operand. 3090b57cec5SDimitry Andric InstrItinData<IIC_iPop , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 3100b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 3110b57cec5SDimitry Andric InstrStage<2, [A9_AGU], 1>, 3120b57cec5SDimitry Andric InstrStage<2, [A9_LSUnit]>], 3130b57cec5SDimitry Andric [1, 1, 3], 3140b57cec5SDimitry Andric [NoBypass, NoBypass, A9_LdBypass], 3150b57cec5SDimitry Andric -1>, // dynamic uops 3160b57cec5SDimitry Andric // 3170b57cec5SDimitry Andric // Pop + branch, def is the 3rd operand. 3180b57cec5SDimitry Andric InstrItinData<IIC_iPop_Br, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 3190b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 3200b57cec5SDimitry Andric InstrStage<2, [A9_AGU], 1>, 3210b57cec5SDimitry Andric InstrStage<2, [A9_LSUnit]>, 3220b57cec5SDimitry Andric InstrStage<1, [A9_Branch]>], 3230b57cec5SDimitry Andric [1, 1, 3], 3240b57cec5SDimitry Andric [NoBypass, NoBypass, A9_LdBypass], 3250b57cec5SDimitry Andric -1>, // dynamic uops 3260b57cec5SDimitry Andric // 3270b57cec5SDimitry Andric // iLoadi + iALUr for t2LDRpci_pic. 3280b57cec5SDimitry Andric InstrItinData<IIC_iLoadiALU, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 3290b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 3300b57cec5SDimitry Andric InstrStage<1, [A9_AGU], 0>, 3310b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>, 3320b57cec5SDimitry Andric InstrStage<1, [A9_ALU0, A9_ALU1]>], 3330b57cec5SDimitry Andric [2, 1]>, 3340b57cec5SDimitry Andric 3350b57cec5SDimitry Andric // Integer store pipeline 3360b57cec5SDimitry Andric /// 3370b57cec5SDimitry Andric // Immediate offset 3380b57cec5SDimitry Andric InstrItinData<IIC_iStore_i , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 3390b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 3400b57cec5SDimitry Andric InstrStage<1, [A9_AGU], 0>, 3410b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], [1, 1]>, 3420b57cec5SDimitry Andric InstrItinData<IIC_iStore_bh_i,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 3430b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 3440b57cec5SDimitry Andric InstrStage<2, [A9_AGU], 1>, 3450b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], [1, 1]>, 3460b57cec5SDimitry Andric // FIXME: If address is 64-bit aligned, AGU cycles is 1. 3470b57cec5SDimitry Andric InstrItinData<IIC_iStore_d_i, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 3480b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 3490b57cec5SDimitry Andric InstrStage<2, [A9_AGU], 1>, 3500b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], [1, 1]>, 3510b57cec5SDimitry Andric // 3520b57cec5SDimitry Andric // Register offset 3530b57cec5SDimitry Andric InstrItinData<IIC_iStore_r , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 3540b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 3550b57cec5SDimitry Andric InstrStage<1, [A9_AGU], 0>, 3560b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], [1, 1, 1]>, 3570b57cec5SDimitry Andric InstrItinData<IIC_iStore_bh_r,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 3580b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 3590b57cec5SDimitry Andric InstrStage<2, [A9_AGU], 1>, 3600b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], [1, 1, 1]>, 3610b57cec5SDimitry Andric InstrItinData<IIC_iStore_d_r, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 3620b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 3630b57cec5SDimitry Andric InstrStage<2, [A9_AGU], 1>, 3640b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], [1, 1, 1]>, 3650b57cec5SDimitry Andric // 3660b57cec5SDimitry Andric // Scaled register offset 3670b57cec5SDimitry Andric InstrItinData<IIC_iStore_si , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 3680b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 3690b57cec5SDimitry Andric InstrStage<1, [A9_AGU], 0>, 3700b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], [1, 1, 1]>, 3710b57cec5SDimitry Andric InstrItinData<IIC_iStore_bh_si,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 3720b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 3730b57cec5SDimitry Andric InstrStage<2, [A9_AGU], 1>, 3740b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], [1, 1, 1]>, 3750b57cec5SDimitry Andric // 3760b57cec5SDimitry Andric // Immediate offset with update 3770b57cec5SDimitry Andric InstrItinData<IIC_iStore_iu , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 3780b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 3790b57cec5SDimitry Andric InstrStage<1, [A9_AGU], 0>, 3800b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], [2, 1, 1]>, 3810b57cec5SDimitry Andric InstrItinData<IIC_iStore_bh_iu,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 3820b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 3830b57cec5SDimitry Andric InstrStage<2, [A9_AGU], 1>, 3840b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], [3, 1, 1]>, 3850b57cec5SDimitry Andric // 3860b57cec5SDimitry Andric // Register offset with update 3870b57cec5SDimitry Andric InstrItinData<IIC_iStore_ru , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 3880b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 3890b57cec5SDimitry Andric InstrStage<1, [A9_AGU], 0>, 3900b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], 3910b57cec5SDimitry Andric [2, 1, 1, 1]>, 3920b57cec5SDimitry Andric InstrItinData<IIC_iStore_bh_ru,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 3930b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 3940b57cec5SDimitry Andric InstrStage<2, [A9_AGU], 1>, 3950b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], 3960b57cec5SDimitry Andric [3, 1, 1, 1]>, 3970b57cec5SDimitry Andric InstrItinData<IIC_iStore_d_ru, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 3980b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 3990b57cec5SDimitry Andric InstrStage<2, [A9_AGU], 1>, 4000b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], 4010b57cec5SDimitry Andric [3, 1, 1, 1]>, 4020b57cec5SDimitry Andric // 4030b57cec5SDimitry Andric // Scaled register offset with update 4040b57cec5SDimitry Andric InstrItinData<IIC_iStore_siu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 4050b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 4060b57cec5SDimitry Andric InstrStage<1, [A9_AGU], 0>, 4070b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], 4080b57cec5SDimitry Andric [2, 1, 1, 1]>, 4090b57cec5SDimitry Andric InstrItinData<IIC_iStore_bh_siu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 4100b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 4110b57cec5SDimitry Andric InstrStage<2, [A9_AGU], 1>, 4120b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], 4130b57cec5SDimitry Andric [3, 1, 1, 1]>, 4140b57cec5SDimitry Andric // 4150b57cec5SDimitry Andric // Store multiple 4160b57cec5SDimitry Andric InstrItinData<IIC_iStore_m , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 4170b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 4180b57cec5SDimitry Andric InstrStage<1, [A9_AGU], 0>, 4190b57cec5SDimitry Andric InstrStage<2, [A9_LSUnit]>], 4200b57cec5SDimitry Andric [], [], -1>, // dynamic uops 4210b57cec5SDimitry Andric // 4220b57cec5SDimitry Andric // Store multiple + update 4230b57cec5SDimitry Andric InstrItinData<IIC_iStore_mu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 4240b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 4250b57cec5SDimitry Andric InstrStage<1, [A9_AGU], 0>, 4260b57cec5SDimitry Andric InstrStage<2, [A9_LSUnit]>], 4270b57cec5SDimitry Andric [2], [], -1>, // dynamic uops 4280b57cec5SDimitry Andric // 4290b57cec5SDimitry Andric // Preload 4300b57cec5SDimitry Andric InstrItinData<IIC_Preload, [InstrStage<1, [A9_Issue0, A9_Issue1]>], [1, 1]>, 4310b57cec5SDimitry Andric 4320b57cec5SDimitry Andric // Branch 4330b57cec5SDimitry Andric // 4340b57cec5SDimitry Andric // no delay slots, so the latency of a branch is unimportant 4350b57cec5SDimitry Andric InstrItinData<IIC_Br , [InstrStage<1, [A9_Issue0], 0>, 4360b57cec5SDimitry Andric InstrStage<1, [A9_Issue1], 0>, 4370b57cec5SDimitry Andric InstrStage<1, [A9_Branch]>]>, 4380b57cec5SDimitry Andric 4390b57cec5SDimitry Andric // VFP and NEON shares the same register file. This means that every VFP 4400b57cec5SDimitry Andric // instruction should wait for full completion of the consecutive NEON 4410b57cec5SDimitry Andric // instruction and vice-versa. We model this behavior with two artificial FUs: 4420b57cec5SDimitry Andric // DRegsVFP and DRegsVFP. 4430b57cec5SDimitry Andric // 4440b57cec5SDimitry Andric // Every VFP instruction: 4450b57cec5SDimitry Andric // - Acquires DRegsVFP resource for 1 cycle 4460b57cec5SDimitry Andric // - Reserves DRegsN resource for the whole duration (including time to 4470b57cec5SDimitry Andric // register file writeback!). 4480b57cec5SDimitry Andric // Every NEON instruction does the same but with FUs swapped. 4490b57cec5SDimitry Andric // 4500b57cec5SDimitry Andric // Since the reserved FU cannot be acquired, this models precisely 4510b57cec5SDimitry Andric // "cross-domain" stalls. 4520b57cec5SDimitry Andric 4530b57cec5SDimitry Andric // VFP 4540b57cec5SDimitry Andric // Issue through integer pipeline, and execute in NEON unit. 4550b57cec5SDimitry Andric 4560b57cec5SDimitry Andric // FP Special Register to Integer Register File Move 4570b57cec5SDimitry Andric InstrItinData<IIC_fpSTAT , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 4580b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 4590b57cec5SDimitry Andric InstrStage<1, [A9_DRegsVFP], 0, Required>, 4600b57cec5SDimitry Andric InstrStage<2, [A9_DRegsN], 0, Reserved>, 4610b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 4620b57cec5SDimitry Andric [1]>, 4630b57cec5SDimitry Andric // 4640b57cec5SDimitry Andric // Single-precision FP Unary 4650b57cec5SDimitry Andric InstrItinData<IIC_fpUNA32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 4660b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 4670b57cec5SDimitry Andric InstrStage<1, [A9_DRegsVFP], 0, Required>, 4680b57cec5SDimitry Andric // Extra latency cycles since wbck is 2 cycles 4690b57cec5SDimitry Andric InstrStage<3, [A9_DRegsN], 0, Reserved>, 4700b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 4710b57cec5SDimitry Andric [1, 1]>, 4720b57cec5SDimitry Andric // 4730b57cec5SDimitry Andric // Double-precision FP Unary 4740b57cec5SDimitry Andric InstrItinData<IIC_fpUNA64 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 4750b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 4760b57cec5SDimitry Andric InstrStage<1, [A9_DRegsVFP], 0, Required>, 4770b57cec5SDimitry Andric // Extra latency cycles since wbck is 2 cycles 4780b57cec5SDimitry Andric InstrStage<3, [A9_DRegsN], 0, Reserved>, 4790b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 4800b57cec5SDimitry Andric [1, 1]>, 4810b57cec5SDimitry Andric 4820b57cec5SDimitry Andric // 4830b57cec5SDimitry Andric // Single-precision FP Compare 4840b57cec5SDimitry Andric InstrItinData<IIC_fpCMP32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 4850b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 4860b57cec5SDimitry Andric InstrStage<1, [A9_DRegsVFP], 0, Required>, 4870b57cec5SDimitry Andric // Extra latency cycles since wbck is 4 cycles 4880b57cec5SDimitry Andric InstrStage<5, [A9_DRegsN], 0, Reserved>, 4890b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 4900b57cec5SDimitry Andric [1, 1]>, 4910b57cec5SDimitry Andric // 4920b57cec5SDimitry Andric // Double-precision FP Compare 4930b57cec5SDimitry Andric InstrItinData<IIC_fpCMP64 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 4940b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 4950b57cec5SDimitry Andric InstrStage<1, [A9_DRegsVFP], 0, Required>, 4960b57cec5SDimitry Andric // Extra latency cycles since wbck is 4 cycles 4970b57cec5SDimitry Andric InstrStage<5, [A9_DRegsN], 0, Reserved>, 4980b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 4990b57cec5SDimitry Andric [1, 1]>, 5000b57cec5SDimitry Andric // 5010b57cec5SDimitry Andric // Single to Double FP Convert 5020b57cec5SDimitry Andric InstrItinData<IIC_fpCVTSD , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 5030b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 5040b57cec5SDimitry Andric InstrStage<1, [A9_DRegsVFP], 0, Required>, 5050b57cec5SDimitry Andric InstrStage<5, [A9_DRegsN], 0, Reserved>, 5060b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 5070b57cec5SDimitry Andric [4, 1]>, 5080b57cec5SDimitry Andric // 5090b57cec5SDimitry Andric // Double to Single FP Convert 5100b57cec5SDimitry Andric InstrItinData<IIC_fpCVTDS , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 5110b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 5120b57cec5SDimitry Andric InstrStage<1, [A9_DRegsVFP], 0, Required>, 5130b57cec5SDimitry Andric InstrStage<5, [A9_DRegsN], 0, Reserved>, 5140b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 5150b57cec5SDimitry Andric [4, 1]>, 5160b57cec5SDimitry Andric 5170b57cec5SDimitry Andric // 5180b57cec5SDimitry Andric // Single to Half FP Convert 5190b57cec5SDimitry Andric InstrItinData<IIC_fpCVTSH , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 5200b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 5210b57cec5SDimitry Andric InstrStage<1, [A9_DRegsVFP], 0, Required>, 5220b57cec5SDimitry Andric InstrStage<5, [A9_DRegsN], 0, Reserved>, 5230b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 5240b57cec5SDimitry Andric [4, 1]>, 5250b57cec5SDimitry Andric // 5260b57cec5SDimitry Andric // Half to Single FP Convert 5270b57cec5SDimitry Andric InstrItinData<IIC_fpCVTHS , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 5280b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 5290b57cec5SDimitry Andric InstrStage<1, [A9_DRegsVFP], 0, Required>, 5300b57cec5SDimitry Andric InstrStage<3, [A9_DRegsN], 0, Reserved>, 5310b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 5320b57cec5SDimitry Andric [2, 1]>, 5330b57cec5SDimitry Andric 5340b57cec5SDimitry Andric // 5350b57cec5SDimitry Andric // Single-Precision FP to Integer Convert 5360b57cec5SDimitry Andric InstrItinData<IIC_fpCVTSI , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 5370b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 5380b57cec5SDimitry Andric InstrStage<1, [A9_DRegsVFP], 0, Required>, 5390b57cec5SDimitry Andric InstrStage<5, [A9_DRegsN], 0, Reserved>, 5400b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 5410b57cec5SDimitry Andric [4, 1]>, 5420b57cec5SDimitry Andric // 5430b57cec5SDimitry Andric // Double-Precision FP to Integer Convert 5440b57cec5SDimitry Andric InstrItinData<IIC_fpCVTDI , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 5450b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 5460b57cec5SDimitry Andric InstrStage<1, [A9_DRegsVFP], 0, Required>, 5470b57cec5SDimitry Andric InstrStage<5, [A9_DRegsN], 0, Reserved>, 5480b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 5490b57cec5SDimitry Andric [4, 1]>, 5500b57cec5SDimitry Andric // 5510b57cec5SDimitry Andric // Integer to Single-Precision FP Convert 5520b57cec5SDimitry Andric InstrItinData<IIC_fpCVTIS , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 5530b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 5540b57cec5SDimitry Andric InstrStage<1, [A9_DRegsVFP], 0, Required>, 5550b57cec5SDimitry Andric InstrStage<5, [A9_DRegsN], 0, Reserved>, 5560b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 5570b57cec5SDimitry Andric [4, 1]>, 5580b57cec5SDimitry Andric // 5590b57cec5SDimitry Andric // Integer to Double-Precision FP Convert 5600b57cec5SDimitry Andric InstrItinData<IIC_fpCVTID , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 5610b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 5620b57cec5SDimitry Andric InstrStage<1, [A9_DRegsVFP], 0, Required>, 5630b57cec5SDimitry Andric InstrStage<5, [A9_DRegsN], 0, Reserved>, 5640b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 5650b57cec5SDimitry Andric [4, 1]>, 5660b57cec5SDimitry Andric // 5670b57cec5SDimitry Andric // Single-precision FP ALU 5680b57cec5SDimitry Andric InstrItinData<IIC_fpALU32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 5690b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 5700b57cec5SDimitry Andric InstrStage<1, [A9_DRegsVFP], 0, Required>, 5710b57cec5SDimitry Andric InstrStage<5, [A9_DRegsN], 0, Reserved>, 5720b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 5730b57cec5SDimitry Andric [4, 1, 1]>, 5740b57cec5SDimitry Andric // 5750b57cec5SDimitry Andric // Double-precision FP ALU 5760b57cec5SDimitry Andric InstrItinData<IIC_fpALU64 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 5770b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 5780b57cec5SDimitry Andric InstrStage<1, [A9_DRegsVFP], 0, Required>, 5790b57cec5SDimitry Andric InstrStage<5, [A9_DRegsN], 0, Reserved>, 5800b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 5810b57cec5SDimitry Andric [4, 1, 1]>, 5820b57cec5SDimitry Andric // 5830b57cec5SDimitry Andric // Single-precision FP Multiply 5840b57cec5SDimitry Andric InstrItinData<IIC_fpMUL32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 5850b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 5860b57cec5SDimitry Andric InstrStage<1, [A9_DRegsVFP], 0, Required>, 5870b57cec5SDimitry Andric InstrStage<6, [A9_DRegsN], 0, Reserved>, 5880b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 5890b57cec5SDimitry Andric [5, 1, 1]>, 5900b57cec5SDimitry Andric // 5910b57cec5SDimitry Andric // Double-precision FP Multiply 5920b57cec5SDimitry Andric InstrItinData<IIC_fpMUL64 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 5930b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 5940b57cec5SDimitry Andric InstrStage<1, [A9_DRegsVFP], 0, Required>, 5950b57cec5SDimitry Andric InstrStage<7, [A9_DRegsN], 0, Reserved>, 5960b57cec5SDimitry Andric InstrStage<2, [A9_NPipe]>], 5970b57cec5SDimitry Andric [6, 1, 1]>, 5980b57cec5SDimitry Andric // 5990b57cec5SDimitry Andric // Single-precision FP MAC 6000b57cec5SDimitry Andric InstrItinData<IIC_fpMAC32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 6010b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 6020b57cec5SDimitry Andric InstrStage<1, [A9_DRegsVFP], 0, Required>, 6030b57cec5SDimitry Andric InstrStage<9, [A9_DRegsN], 0, Reserved>, 6040b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 6050b57cec5SDimitry Andric [8, 1, 1, 1]>, 6060b57cec5SDimitry Andric // 6070b57cec5SDimitry Andric // Double-precision FP MAC 6080b57cec5SDimitry Andric InstrItinData<IIC_fpMAC64 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 6090b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 6100b57cec5SDimitry Andric InstrStage<1, [A9_DRegsVFP], 0, Required>, 6110b57cec5SDimitry Andric InstrStage<10, [A9_DRegsN], 0, Reserved>, 6120b57cec5SDimitry Andric InstrStage<2, [A9_NPipe]>], 6130b57cec5SDimitry Andric [9, 1, 1, 1]>, 6140b57cec5SDimitry Andric // 6150b57cec5SDimitry Andric // Single-precision Fused FP MAC 6160b57cec5SDimitry Andric InstrItinData<IIC_fpFMAC32, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 6170b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 6180b57cec5SDimitry Andric InstrStage<1, [A9_DRegsVFP], 0, Required>, 6190b57cec5SDimitry Andric InstrStage<9, [A9_DRegsN], 0, Reserved>, 6200b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 6210b57cec5SDimitry Andric [8, 1, 1, 1]>, 6220b57cec5SDimitry Andric // 6230b57cec5SDimitry Andric // Double-precision Fused FP MAC 6240b57cec5SDimitry Andric InstrItinData<IIC_fpFMAC64, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 6250b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 6260b57cec5SDimitry Andric InstrStage<1, [A9_DRegsVFP], 0, Required>, 6270b57cec5SDimitry Andric InstrStage<10, [A9_DRegsN], 0, Reserved>, 6280b57cec5SDimitry Andric InstrStage<2, [A9_NPipe]>], 6290b57cec5SDimitry Andric [9, 1, 1, 1]>, 6300b57cec5SDimitry Andric // 6310b57cec5SDimitry Andric // Single-precision FP DIV 6320b57cec5SDimitry Andric InstrItinData<IIC_fpDIV32 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 6330b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 6340b57cec5SDimitry Andric InstrStage<1, [A9_DRegsVFP], 0, Required>, 6350b57cec5SDimitry Andric InstrStage<16, [A9_DRegsN], 0, Reserved>, 6360b57cec5SDimitry Andric InstrStage<10, [A9_NPipe]>], 6370b57cec5SDimitry Andric [15, 1, 1]>, 6380b57cec5SDimitry Andric // 6390b57cec5SDimitry Andric // Double-precision FP DIV 6400b57cec5SDimitry Andric InstrItinData<IIC_fpDIV64 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 6410b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 6420b57cec5SDimitry Andric InstrStage<1, [A9_DRegsVFP], 0, Required>, 6430b57cec5SDimitry Andric InstrStage<26, [A9_DRegsN], 0, Reserved>, 6440b57cec5SDimitry Andric InstrStage<20, [A9_NPipe]>], 6450b57cec5SDimitry Andric [25, 1, 1]>, 6460b57cec5SDimitry Andric // 6470b57cec5SDimitry Andric // Single-precision FP SQRT 6480b57cec5SDimitry Andric InstrItinData<IIC_fpSQRT32, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 6490b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 6500b57cec5SDimitry Andric InstrStage<1, [A9_DRegsVFP], 0, Required>, 6510b57cec5SDimitry Andric InstrStage<18, [A9_DRegsN], 0, Reserved>, 6520b57cec5SDimitry Andric InstrStage<13, [A9_NPipe]>], 6530b57cec5SDimitry Andric [17, 1]>, 6540b57cec5SDimitry Andric // 6550b57cec5SDimitry Andric // Double-precision FP SQRT 6560b57cec5SDimitry Andric InstrItinData<IIC_fpSQRT64, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 6570b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 6580b57cec5SDimitry Andric InstrStage<1, [A9_DRegsVFP], 0, Required>, 6590b57cec5SDimitry Andric InstrStage<33, [A9_DRegsN], 0, Reserved>, 6600b57cec5SDimitry Andric InstrStage<28, [A9_NPipe]>], 6610b57cec5SDimitry Andric [32, 1]>, 6620b57cec5SDimitry Andric 6630b57cec5SDimitry Andric // 6640b57cec5SDimitry Andric // Integer to Single-precision Move 6650b57cec5SDimitry Andric InstrItinData<IIC_fpMOVIS, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 6660b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 6670b57cec5SDimitry Andric InstrStage<1, [A9_DRegsVFP], 0, Required>, 6680b57cec5SDimitry Andric // Extra 1 latency cycle since wbck is 2 cycles 6690b57cec5SDimitry Andric InstrStage<3, [A9_DRegsN], 0, Reserved>, 6700b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 6710b57cec5SDimitry Andric [1, 1]>, 6720b57cec5SDimitry Andric // 6730b57cec5SDimitry Andric // Integer to Double-precision Move 6740b57cec5SDimitry Andric InstrItinData<IIC_fpMOVID, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 6750b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 6760b57cec5SDimitry Andric InstrStage<1, [A9_DRegsVFP], 0, Required>, 6770b57cec5SDimitry Andric // Extra 1 latency cycle since wbck is 2 cycles 6780b57cec5SDimitry Andric InstrStage<3, [A9_DRegsN], 0, Reserved>, 6790b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 6800b57cec5SDimitry Andric [1, 1, 1]>, 6810b57cec5SDimitry Andric // 6820b57cec5SDimitry Andric // Single-precision to Integer Move 6830b57cec5SDimitry Andric // 6840b57cec5SDimitry Andric // On A9 move-from-VFP is free to issue with no stall if other VFP 6850b57cec5SDimitry Andric // operations are in flight. I assume it still can't dual-issue though. 6860b57cec5SDimitry Andric InstrItinData<IIC_fpMOVSI, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 6870b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>], 6880b57cec5SDimitry Andric [2, 1]>, 6890b57cec5SDimitry Andric // 6900b57cec5SDimitry Andric // Double-precision to Integer Move 6910b57cec5SDimitry Andric // 6920b57cec5SDimitry Andric // On A9 move-from-VFP is free to issue with no stall if other VFP 6930b57cec5SDimitry Andric // operations are in flight. I assume it still can't dual-issue though. 6940b57cec5SDimitry Andric InstrItinData<IIC_fpMOVDI, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 6950b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>], 6960b57cec5SDimitry Andric [2, 1, 1]>, 6970b57cec5SDimitry Andric // 6980b57cec5SDimitry Andric // Single-precision FP Load 6990b57cec5SDimitry Andric InstrItinData<IIC_fpLoad32, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 7000b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 7010b57cec5SDimitry Andric InstrStage<1, [A9_DRegsVFP], 0, Required>, 7020b57cec5SDimitry Andric InstrStage<2, [A9_DRegsN], 0, Reserved>, 7030b57cec5SDimitry Andric InstrStage<1, [A9_NPipe], 0>, 7040b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], 7050b57cec5SDimitry Andric [1, 1]>, 7060b57cec5SDimitry Andric // 7070b57cec5SDimitry Andric // Double-precision FP Load 7080b57cec5SDimitry Andric // FIXME: Result latency is 1 if address is 64-bit aligned. 7090b57cec5SDimitry Andric InstrItinData<IIC_fpLoad64, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 7100b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 7110b57cec5SDimitry Andric InstrStage<1, [A9_DRegsVFP], 0, Required>, 7120b57cec5SDimitry Andric InstrStage<2, [A9_DRegsN], 0, Reserved>, 7130b57cec5SDimitry Andric InstrStage<1, [A9_NPipe], 0>, 7140b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], 7150b57cec5SDimitry Andric [2, 1]>, 7160b57cec5SDimitry Andric // 7170b57cec5SDimitry Andric // FP Load Multiple 7180b57cec5SDimitry Andric // FIXME: assumes 2 doubles which requires 2 LS cycles. 7190b57cec5SDimitry Andric InstrItinData<IIC_fpLoad_m, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 7200b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 7210b57cec5SDimitry Andric InstrStage<1, [A9_DRegsVFP], 0, Required>, 7220b57cec5SDimitry Andric InstrStage<2, [A9_DRegsN], 0, Reserved>, 7230b57cec5SDimitry Andric InstrStage<1, [A9_NPipe], 0>, 7240b57cec5SDimitry Andric InstrStage<2, [A9_LSUnit]>], 7250b57cec5SDimitry Andric [1, 1, 1, 1], [], -1>, // dynamic uops 7260b57cec5SDimitry Andric // 7270b57cec5SDimitry Andric // FP Load Multiple + update 7280b57cec5SDimitry Andric // FIXME: assumes 2 doubles which requires 2 LS cycles. 7290b57cec5SDimitry Andric InstrItinData<IIC_fpLoad_mu,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 7300b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 7310b57cec5SDimitry Andric InstrStage<1, [A9_DRegsVFP], 0, Required>, 7320b57cec5SDimitry Andric InstrStage<2, [A9_DRegsN], 0, Reserved>, 7330b57cec5SDimitry Andric InstrStage<1, [A9_NPipe], 0>, 7340b57cec5SDimitry Andric InstrStage<2, [A9_LSUnit]>], 7350b57cec5SDimitry Andric [2, 1, 1, 1], [], -1>, // dynamic uops 7360b57cec5SDimitry Andric // 7370b57cec5SDimitry Andric // Single-precision FP Store 7380b57cec5SDimitry Andric InstrItinData<IIC_fpStore32,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 7390b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 7400b57cec5SDimitry Andric InstrStage<1, [A9_DRegsVFP], 0, Required>, 7410b57cec5SDimitry Andric InstrStage<2, [A9_DRegsN], 0, Reserved>, 7420b57cec5SDimitry Andric InstrStage<1, [A9_NPipe], 0>, 7430b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], 7440b57cec5SDimitry Andric [1, 1]>, 7450b57cec5SDimitry Andric // 7460b57cec5SDimitry Andric // Double-precision FP Store 7470b57cec5SDimitry Andric InstrItinData<IIC_fpStore64,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 7480b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 7490b57cec5SDimitry Andric InstrStage<1, [A9_DRegsVFP], 0, Required>, 7500b57cec5SDimitry Andric InstrStage<2, [A9_DRegsN], 0, Reserved>, 7510b57cec5SDimitry Andric InstrStage<1, [A9_NPipe], 0>, 7520b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], 7530b57cec5SDimitry Andric [1, 1]>, 7540b57cec5SDimitry Andric // 7550b57cec5SDimitry Andric // FP Store Multiple 7560b57cec5SDimitry Andric // FIXME: assumes 2 doubles which requires 2 LS cycles. 7570b57cec5SDimitry Andric InstrItinData<IIC_fpStore_m,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 7580b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 7590b57cec5SDimitry Andric InstrStage<1, [A9_DRegsVFP], 0, Required>, 7600b57cec5SDimitry Andric InstrStage<2, [A9_DRegsN], 0, Reserved>, 7610b57cec5SDimitry Andric InstrStage<1, [A9_NPipe], 0>, 7620b57cec5SDimitry Andric InstrStage<2, [A9_LSUnit]>], 7630b57cec5SDimitry Andric [1, 1, 1, 1], [], -1>, // dynamic uops 7640b57cec5SDimitry Andric // 7650b57cec5SDimitry Andric // FP Store Multiple + update 7660b57cec5SDimitry Andric // FIXME: assumes 2 doubles which requires 2 LS cycles. 7670b57cec5SDimitry Andric InstrItinData<IIC_fpStore_mu,[InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 7680b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 7690b57cec5SDimitry Andric InstrStage<1, [A9_DRegsVFP], 0, Required>, 7700b57cec5SDimitry Andric InstrStage<2, [A9_DRegsN], 0, Reserved>, 7710b57cec5SDimitry Andric InstrStage<1, [A9_NPipe], 0>, 7720b57cec5SDimitry Andric InstrStage<2, [A9_LSUnit]>], 7730b57cec5SDimitry Andric [2, 1, 1, 1], [], -1>, // dynamic uops 7740b57cec5SDimitry Andric // NEON 7750b57cec5SDimitry Andric // VLD1 7760b57cec5SDimitry Andric InstrItinData<IIC_VLD1, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 7770b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 7780b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 7790b57cec5SDimitry Andric InstrStage<7, [A9_DRegsVFP], 0, Reserved>, 7800b57cec5SDimitry Andric InstrStage<1, [A9_NPipe], 0>, 7810b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], 7820b57cec5SDimitry Andric [1, 1]>, 7830b57cec5SDimitry Andric // VLD1x2 7840b57cec5SDimitry Andric InstrItinData<IIC_VLD1x2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 7850b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 7860b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 7870b57cec5SDimitry Andric InstrStage<7, [A9_DRegsVFP], 0, Reserved>, 7880b57cec5SDimitry Andric InstrStage<1, [A9_NPipe], 0>, 7890b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], 7900b57cec5SDimitry Andric [1, 1, 1]>, 7910b57cec5SDimitry Andric // VLD1x3 7920b57cec5SDimitry Andric InstrItinData<IIC_VLD1x3, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 7930b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 7940b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 7950b57cec5SDimitry Andric InstrStage<8, [A9_DRegsVFP], 0, Reserved>, 7960b57cec5SDimitry Andric InstrStage<2, [A9_NPipe], 0>, 7970b57cec5SDimitry Andric InstrStage<2, [A9_LSUnit]>], 7980b57cec5SDimitry Andric [1, 1, 2, 1]>, 7990b57cec5SDimitry Andric // VLD1x4 8000b57cec5SDimitry Andric InstrItinData<IIC_VLD1x4, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 8010b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 8020b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 8030b57cec5SDimitry Andric InstrStage<8, [A9_DRegsVFP], 0, Reserved>, 8040b57cec5SDimitry Andric InstrStage<2, [A9_NPipe], 0>, 8050b57cec5SDimitry Andric InstrStage<2, [A9_LSUnit]>], 8060b57cec5SDimitry Andric [1, 1, 2, 2, 1]>, 8070b57cec5SDimitry Andric // VLD1u 8080b57cec5SDimitry Andric InstrItinData<IIC_VLD1u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 8090b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 8100b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 8110b57cec5SDimitry Andric InstrStage<7, [A9_DRegsVFP], 0, Reserved>, 8120b57cec5SDimitry Andric InstrStage<1, [A9_NPipe], 0>, 8130b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], 8140b57cec5SDimitry Andric [1, 2, 1]>, 8150b57cec5SDimitry Andric // VLD1x2u 8160b57cec5SDimitry Andric InstrItinData<IIC_VLD1x2u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 8170b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 8180b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 8190b57cec5SDimitry Andric InstrStage<7, [A9_DRegsVFP], 0, Reserved>, 8200b57cec5SDimitry Andric InstrStage<1, [A9_NPipe], 0>, 8210b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], 8220b57cec5SDimitry Andric [1, 1, 2, 1]>, 8230b57cec5SDimitry Andric // VLD1x3u 8240b57cec5SDimitry Andric InstrItinData<IIC_VLD1x3u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 8250b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 8260b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 8270b57cec5SDimitry Andric InstrStage<8, [A9_DRegsVFP], 0, Reserved>, 8280b57cec5SDimitry Andric InstrStage<2, [A9_NPipe], 0>, 8290b57cec5SDimitry Andric InstrStage<2, [A9_LSUnit]>], 8300b57cec5SDimitry Andric [1, 1, 2, 2, 1]>, 8310b57cec5SDimitry Andric // VLD1x4u 8320b57cec5SDimitry Andric InstrItinData<IIC_VLD1x4u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 8330b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 8340b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 8350b57cec5SDimitry Andric InstrStage<8, [A9_DRegsVFP], 0, Reserved>, 8360b57cec5SDimitry Andric InstrStage<2, [A9_NPipe], 0>, 8370b57cec5SDimitry Andric InstrStage<2, [A9_LSUnit]>], 8380b57cec5SDimitry Andric [1, 1, 2, 2, 2, 1]>, 8390b57cec5SDimitry Andric // 8400b57cec5SDimitry Andric // VLD1ln 8410b57cec5SDimitry Andric InstrItinData<IIC_VLD1ln, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 8420b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 8430b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 8440b57cec5SDimitry Andric InstrStage<8, [A9_DRegsVFP], 0, Reserved>, 8450b57cec5SDimitry Andric InstrStage<2, [A9_NPipe], 0>, 8460b57cec5SDimitry Andric InstrStage<2, [A9_LSUnit]>], 8470b57cec5SDimitry Andric [3, 1, 1, 1]>, 8480b57cec5SDimitry Andric // 8490b57cec5SDimitry Andric // VLD1lnu 8500b57cec5SDimitry Andric InstrItinData<IIC_VLD1lnu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 8510b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 8520b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 8530b57cec5SDimitry Andric InstrStage<8, [A9_DRegsVFP], 0, Reserved>, 8540b57cec5SDimitry Andric InstrStage<2, [A9_NPipe], 0>, 8550b57cec5SDimitry Andric InstrStage<2, [A9_LSUnit]>], 8560b57cec5SDimitry Andric [3, 2, 1, 1, 1, 1]>, 8570b57cec5SDimitry Andric // 8580b57cec5SDimitry Andric // VLD1dup 8590b57cec5SDimitry Andric InstrItinData<IIC_VLD1dup, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 8600b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 8610b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 8620b57cec5SDimitry Andric InstrStage<7, [A9_DRegsVFP], 0, Reserved>, 8630b57cec5SDimitry Andric InstrStage<1, [A9_NPipe], 0>, 8640b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], 8650b57cec5SDimitry Andric [2, 1]>, 8660b57cec5SDimitry Andric // 8670b57cec5SDimitry Andric // VLD1dupu 8680b57cec5SDimitry Andric InstrItinData<IIC_VLD1dupu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 8690b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 8700b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 8710b57cec5SDimitry Andric InstrStage<7, [A9_DRegsVFP], 0, Reserved>, 8720b57cec5SDimitry Andric InstrStage<1, [A9_NPipe], 0>, 8730b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], 8740b57cec5SDimitry Andric [2, 2, 1, 1]>, 8750b57cec5SDimitry Andric // 8760b57cec5SDimitry Andric // VLD2 8770b57cec5SDimitry Andric InstrItinData<IIC_VLD2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 8780b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 8790b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 8800b57cec5SDimitry Andric // Extra latency cycles since wbck is 7 cycles 8810b57cec5SDimitry Andric InstrStage<7, [A9_DRegsVFP], 0, Reserved>, 8820b57cec5SDimitry Andric InstrStage<1, [A9_NPipe], 0>, 8830b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], 8840b57cec5SDimitry Andric [2, 2, 1]>, 8850b57cec5SDimitry Andric // 8860b57cec5SDimitry Andric // VLD2x2 8870b57cec5SDimitry Andric InstrItinData<IIC_VLD2x2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 8880b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 8890b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 8900b57cec5SDimitry Andric InstrStage<8, [A9_DRegsVFP], 0, Reserved>, 8910b57cec5SDimitry Andric InstrStage<2, [A9_NPipe], 0>, 8920b57cec5SDimitry Andric InstrStage<2, [A9_LSUnit]>], 8930b57cec5SDimitry Andric [2, 3, 2, 3, 1]>, 8940b57cec5SDimitry Andric // 8950b57cec5SDimitry Andric // VLD2ln 8960b57cec5SDimitry Andric InstrItinData<IIC_VLD2ln, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 8970b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 8980b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 8990b57cec5SDimitry Andric InstrStage<8, [A9_DRegsVFP], 0, Reserved>, 9000b57cec5SDimitry Andric InstrStage<2, [A9_NPipe], 0>, 9010b57cec5SDimitry Andric InstrStage<2, [A9_LSUnit]>], 9020b57cec5SDimitry Andric [3, 3, 1, 1, 1, 1]>, 9030b57cec5SDimitry Andric // 9040b57cec5SDimitry Andric // VLD2u 9050b57cec5SDimitry Andric InstrItinData<IIC_VLD2u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 9060b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 9070b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 9080b57cec5SDimitry Andric // Extra latency cycles since wbck is 7 cycles 9090b57cec5SDimitry Andric InstrStage<7, [A9_DRegsVFP], 0, Reserved>, 9100b57cec5SDimitry Andric InstrStage<1, [A9_NPipe], 0>, 9110b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], 9120b57cec5SDimitry Andric [2, 2, 2, 1, 1, 1]>, 9130b57cec5SDimitry Andric // 9140b57cec5SDimitry Andric // VLD2x2u 9150b57cec5SDimitry Andric InstrItinData<IIC_VLD2x2u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 9160b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 9170b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 9180b57cec5SDimitry Andric InstrStage<8, [A9_DRegsVFP], 0, Reserved>, 9190b57cec5SDimitry Andric InstrStage<2, [A9_NPipe], 0>, 9200b57cec5SDimitry Andric InstrStage<2, [A9_LSUnit]>], 9210b57cec5SDimitry Andric [2, 3, 2, 3, 2, 1]>, 9220b57cec5SDimitry Andric // 9230b57cec5SDimitry Andric // VLD2lnu 9240b57cec5SDimitry Andric InstrItinData<IIC_VLD2lnu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 9250b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 9260b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 9270b57cec5SDimitry Andric InstrStage<8, [A9_DRegsVFP], 0, Reserved>, 9280b57cec5SDimitry Andric InstrStage<2, [A9_NPipe], 0>, 9290b57cec5SDimitry Andric InstrStage<2, [A9_LSUnit]>], 9300b57cec5SDimitry Andric [3, 3, 2, 1, 1, 1, 1, 1]>, 9310b57cec5SDimitry Andric // 9320b57cec5SDimitry Andric // VLD2dup 9330b57cec5SDimitry Andric InstrItinData<IIC_VLD2dup, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 9340b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 9350b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 9360b57cec5SDimitry Andric InstrStage<7, [A9_DRegsVFP], 0, Reserved>, 9370b57cec5SDimitry Andric InstrStage<1, [A9_NPipe], 0>, 9380b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], 9390b57cec5SDimitry Andric [2, 2, 1]>, 9400b57cec5SDimitry Andric // 9410b57cec5SDimitry Andric // VLD2dupu 9420b57cec5SDimitry Andric InstrItinData<IIC_VLD2dupu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 9430b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 9440b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 9450b57cec5SDimitry Andric InstrStage<7, [A9_DRegsVFP], 0, Reserved>, 9460b57cec5SDimitry Andric InstrStage<1, [A9_NPipe], 0>, 9470b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], 9480b57cec5SDimitry Andric [2, 2, 2, 1, 1]>, 9490b57cec5SDimitry Andric // 9500b57cec5SDimitry Andric // VLD3 9510b57cec5SDimitry Andric InstrItinData<IIC_VLD3, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 9520b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 9530b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 9540b57cec5SDimitry Andric InstrStage<9,[A9_DRegsVFP], 0, Reserved>, 9550b57cec5SDimitry Andric InstrStage<3, [A9_NPipe], 0>, 9560b57cec5SDimitry Andric InstrStage<3, [A9_LSUnit]>], 9570b57cec5SDimitry Andric [3, 3, 4, 1]>, 9580b57cec5SDimitry Andric // 9590b57cec5SDimitry Andric // VLD3ln 9600b57cec5SDimitry Andric InstrItinData<IIC_VLD3ln, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 9610b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 9620b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 9630b57cec5SDimitry Andric InstrStage<11,[A9_DRegsVFP], 0, Reserved>, 9640b57cec5SDimitry Andric InstrStage<5, [A9_NPipe], 0>, 9650b57cec5SDimitry Andric InstrStage<5, [A9_LSUnit]>], 9660b57cec5SDimitry Andric [5, 5, 6, 1, 1, 1, 1, 2]>, 9670b57cec5SDimitry Andric // 9680b57cec5SDimitry Andric // VLD3u 9690b57cec5SDimitry Andric InstrItinData<IIC_VLD3u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 9700b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 9710b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 9720b57cec5SDimitry Andric InstrStage<9,[A9_DRegsVFP], 0, Reserved>, 9730b57cec5SDimitry Andric InstrStage<3, [A9_NPipe], 0>, 9740b57cec5SDimitry Andric InstrStage<3, [A9_LSUnit]>], 9750b57cec5SDimitry Andric [3, 3, 4, 2, 1]>, 9760b57cec5SDimitry Andric // 9770b57cec5SDimitry Andric // VLD3lnu 9780b57cec5SDimitry Andric InstrItinData<IIC_VLD3lnu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 9790b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 9800b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 9810b57cec5SDimitry Andric InstrStage<11,[A9_DRegsVFP], 0, Reserved>, 9820b57cec5SDimitry Andric InstrStage<5, [A9_NPipe], 0>, 9830b57cec5SDimitry Andric InstrStage<5, [A9_LSUnit]>], 9840b57cec5SDimitry Andric [5, 5, 6, 2, 1, 1, 1, 1, 1, 2]>, 9850b57cec5SDimitry Andric // 9860b57cec5SDimitry Andric // VLD3dup 9870b57cec5SDimitry Andric InstrItinData<IIC_VLD3dup, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 9880b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 9890b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 9900b57cec5SDimitry Andric InstrStage<9, [A9_DRegsVFP], 0, Reserved>, 9910b57cec5SDimitry Andric InstrStage<3, [A9_NPipe], 0>, 9920b57cec5SDimitry Andric InstrStage<3, [A9_LSUnit]>], 9930b57cec5SDimitry Andric [3, 3, 4, 1]>, 9940b57cec5SDimitry Andric // 9950b57cec5SDimitry Andric // VLD3dupu 9960b57cec5SDimitry Andric InstrItinData<IIC_VLD3dupu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 9970b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 9980b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 9990b57cec5SDimitry Andric InstrStage<9, [A9_DRegsVFP], 0, Reserved>, 10000b57cec5SDimitry Andric InstrStage<3, [A9_NPipe], 0>, 10010b57cec5SDimitry Andric InstrStage<3, [A9_LSUnit]>], 10020b57cec5SDimitry Andric [3, 3, 4, 2, 1, 1]>, 10030b57cec5SDimitry Andric // 10040b57cec5SDimitry Andric // VLD4 10050b57cec5SDimitry Andric InstrItinData<IIC_VLD4, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 10060b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 10070b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 10080b57cec5SDimitry Andric InstrStage<9,[A9_DRegsVFP], 0, Reserved>, 10090b57cec5SDimitry Andric InstrStage<3, [A9_NPipe], 0>, 10100b57cec5SDimitry Andric InstrStage<3, [A9_LSUnit]>], 10110b57cec5SDimitry Andric [3, 3, 4, 4, 1]>, 10120b57cec5SDimitry Andric // 10130b57cec5SDimitry Andric // VLD4ln 10140b57cec5SDimitry Andric InstrItinData<IIC_VLD4ln, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 10150b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 10160b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 10170b57cec5SDimitry Andric InstrStage<10,[A9_DRegsVFP], 0, Reserved>, 10180b57cec5SDimitry Andric InstrStage<4, [A9_NPipe], 0>, 10190b57cec5SDimitry Andric InstrStage<4, [A9_LSUnit]>], 10200b57cec5SDimitry Andric [4, 4, 5, 5, 1, 1, 1, 1, 2, 2]>, 10210b57cec5SDimitry Andric // 10220b57cec5SDimitry Andric // VLD4u 10230b57cec5SDimitry Andric InstrItinData<IIC_VLD4u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 10240b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 10250b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 10260b57cec5SDimitry Andric InstrStage<9,[A9_DRegsVFP], 0, Reserved>, 10270b57cec5SDimitry Andric InstrStage<3, [A9_NPipe], 0>, 10280b57cec5SDimitry Andric InstrStage<3, [A9_LSUnit]>], 10290b57cec5SDimitry Andric [3, 3, 4, 4, 2, 1]>, 10300b57cec5SDimitry Andric // 10310b57cec5SDimitry Andric // VLD4lnu 10320b57cec5SDimitry Andric InstrItinData<IIC_VLD4lnu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 10330b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 10340b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 10350b57cec5SDimitry Andric InstrStage<10,[A9_DRegsVFP], 0, Reserved>, 10360b57cec5SDimitry Andric InstrStage<4, [A9_NPipe], 0>, 10370b57cec5SDimitry Andric InstrStage<4, [A9_LSUnit]>], 10380b57cec5SDimitry Andric [4, 4, 5, 5, 2, 1, 1, 1, 1, 1, 2, 2]>, 10390b57cec5SDimitry Andric // 10400b57cec5SDimitry Andric // VLD4dup 10410b57cec5SDimitry Andric InstrItinData<IIC_VLD4dup, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 10420b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 10430b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 10440b57cec5SDimitry Andric InstrStage<8, [A9_DRegsVFP], 0, Reserved>, 10450b57cec5SDimitry Andric InstrStage<2, [A9_NPipe], 0>, 10460b57cec5SDimitry Andric InstrStage<2, [A9_LSUnit]>], 10470b57cec5SDimitry Andric [2, 2, 3, 3, 1]>, 10480b57cec5SDimitry Andric // 10490b57cec5SDimitry Andric // VLD4dupu 10500b57cec5SDimitry Andric InstrItinData<IIC_VLD4dupu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 10510b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 10520b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 10530b57cec5SDimitry Andric InstrStage<8, [A9_DRegsVFP], 0, Reserved>, 10540b57cec5SDimitry Andric InstrStage<2, [A9_NPipe], 0>, 10550b57cec5SDimitry Andric InstrStage<2, [A9_LSUnit]>], 10560b57cec5SDimitry Andric [2, 2, 3, 3, 2, 1, 1]>, 10570b57cec5SDimitry Andric // 10580b57cec5SDimitry Andric // VST1 10590b57cec5SDimitry Andric InstrItinData<IIC_VST1, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 10600b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 10610b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 10620b57cec5SDimitry Andric InstrStage<1, [A9_DRegsVFP], 0, Reserved>, 10630b57cec5SDimitry Andric InstrStage<1, [A9_NPipe], 0>, 10640b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], 10650b57cec5SDimitry Andric [1, 1, 1]>, 10660b57cec5SDimitry Andric // 10670b57cec5SDimitry Andric // VST1x2 10680b57cec5SDimitry Andric InstrItinData<IIC_VST1x2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 10690b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 10700b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 10710b57cec5SDimitry Andric InstrStage<1, [A9_DRegsVFP], 0, Reserved>, 10720b57cec5SDimitry Andric InstrStage<1, [A9_NPipe], 0>, 10730b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], 10740b57cec5SDimitry Andric [1, 1, 1, 1]>, 10750b57cec5SDimitry Andric // 10760b57cec5SDimitry Andric // VST1x3 10770b57cec5SDimitry Andric InstrItinData<IIC_VST1x3, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 10780b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 10790b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 10800b57cec5SDimitry Andric InstrStage<2, [A9_DRegsVFP], 0, Reserved>, 10810b57cec5SDimitry Andric InstrStage<2, [A9_NPipe], 0>, 10820b57cec5SDimitry Andric InstrStage<2, [A9_LSUnit]>], 10830b57cec5SDimitry Andric [1, 1, 1, 1, 2]>, 10840b57cec5SDimitry Andric // 10850b57cec5SDimitry Andric // VST1x4 10860b57cec5SDimitry Andric InstrItinData<IIC_VST1x4, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 10870b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 10880b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 10890b57cec5SDimitry Andric InstrStage<2, [A9_DRegsVFP], 0, Reserved>, 10900b57cec5SDimitry Andric InstrStage<2, [A9_NPipe], 0>, 10910b57cec5SDimitry Andric InstrStage<2, [A9_LSUnit]>], 10920b57cec5SDimitry Andric [1, 1, 1, 1, 2, 2]>, 10930b57cec5SDimitry Andric // 10940b57cec5SDimitry Andric // VST1u 10950b57cec5SDimitry Andric InstrItinData<IIC_VST1u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 10960b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 10970b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 10980b57cec5SDimitry Andric InstrStage<1, [A9_DRegsVFP], 0, Reserved>, 10990b57cec5SDimitry Andric InstrStage<1, [A9_NPipe], 0>, 11000b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], 11010b57cec5SDimitry Andric [2, 1, 1, 1, 1]>, 11020b57cec5SDimitry Andric // 11030b57cec5SDimitry Andric // VST1x2u 11040b57cec5SDimitry Andric InstrItinData<IIC_VST1x2u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 11050b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 11060b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 11070b57cec5SDimitry Andric InstrStage<1, [A9_DRegsVFP], 0, Reserved>, 11080b57cec5SDimitry Andric InstrStage<1, [A9_NPipe], 0>, 11090b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], 11100b57cec5SDimitry Andric [2, 1, 1, 1, 1, 1]>, 11110b57cec5SDimitry Andric // 11120b57cec5SDimitry Andric // VST1x3u 11130b57cec5SDimitry Andric InstrItinData<IIC_VST1x3u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 11140b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 11150b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 11160b57cec5SDimitry Andric InstrStage<2, [A9_DRegsVFP], 0, Reserved>, 11170b57cec5SDimitry Andric InstrStage<2, [A9_NPipe], 0>, 11180b57cec5SDimitry Andric InstrStage<2, [A9_LSUnit]>], 11190b57cec5SDimitry Andric [2, 1, 1, 1, 1, 1, 2]>, 11200b57cec5SDimitry Andric // 11210b57cec5SDimitry Andric // VST1x4u 11220b57cec5SDimitry Andric InstrItinData<IIC_VST1x4u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 11230b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 11240b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 11250b57cec5SDimitry Andric InstrStage<2, [A9_DRegsVFP], 0, Reserved>, 11260b57cec5SDimitry Andric InstrStage<2, [A9_NPipe], 0>, 11270b57cec5SDimitry Andric InstrStage<2, [A9_LSUnit]>], 11280b57cec5SDimitry Andric [2, 1, 1, 1, 1, 1, 2, 2]>, 11290b57cec5SDimitry Andric // 11300b57cec5SDimitry Andric // VST1ln 11310b57cec5SDimitry Andric InstrItinData<IIC_VST1ln, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 11320b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 11330b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 11340b57cec5SDimitry Andric InstrStage<1, [A9_DRegsVFP], 0, Reserved>, 11350b57cec5SDimitry Andric InstrStage<1, [A9_NPipe], 0>, 11360b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], 11370b57cec5SDimitry Andric [1, 1, 1]>, 11380b57cec5SDimitry Andric // 11390b57cec5SDimitry Andric // VST1lnu 11400b57cec5SDimitry Andric InstrItinData<IIC_VST1lnu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 11410b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 11420b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 11430b57cec5SDimitry Andric InstrStage<1, [A9_DRegsVFP], 0, Reserved>, 11440b57cec5SDimitry Andric InstrStage<1, [A9_NPipe], 0>, 11450b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], 11460b57cec5SDimitry Andric [2, 1, 1, 1, 1]>, 11470b57cec5SDimitry Andric // 11480b57cec5SDimitry Andric // VST2 11490b57cec5SDimitry Andric InstrItinData<IIC_VST2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 11500b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 11510b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 11520b57cec5SDimitry Andric InstrStage<1, [A9_DRegsVFP], 0, Reserved>, 11530b57cec5SDimitry Andric InstrStage<1, [A9_NPipe], 0>, 11540b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], 11550b57cec5SDimitry Andric [1, 1, 1, 1]>, 11560b57cec5SDimitry Andric // 11570b57cec5SDimitry Andric // VST2x2 11580b57cec5SDimitry Andric InstrItinData<IIC_VST2x2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 11590b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 11600b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 11610b57cec5SDimitry Andric InstrStage<3, [A9_DRegsVFP], 0, Reserved>, 11620b57cec5SDimitry Andric InstrStage<3, [A9_NPipe], 0>, 11630b57cec5SDimitry Andric InstrStage<3, [A9_LSUnit]>], 11640b57cec5SDimitry Andric [1, 1, 1, 1, 2, 2]>, 11650b57cec5SDimitry Andric // 11660b57cec5SDimitry Andric // VST2u 11670b57cec5SDimitry Andric InstrItinData<IIC_VST2u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 11680b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 11690b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 11700b57cec5SDimitry Andric InstrStage<1, [A9_DRegsVFP], 0, Reserved>, 11710b57cec5SDimitry Andric InstrStage<1, [A9_NPipe], 0>, 11720b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], 11730b57cec5SDimitry Andric [2, 1, 1, 1, 1, 1]>, 11740b57cec5SDimitry Andric // 11750b57cec5SDimitry Andric // VST2x2u 11760b57cec5SDimitry Andric InstrItinData<IIC_VST2x2u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 11770b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 11780b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 11790b57cec5SDimitry Andric InstrStage<3, [A9_DRegsVFP], 0, Reserved>, 11800b57cec5SDimitry Andric InstrStage<3, [A9_NPipe], 0>, 11810b57cec5SDimitry Andric InstrStage<3, [A9_LSUnit]>], 11820b57cec5SDimitry Andric [2, 1, 1, 1, 1, 1, 2, 2]>, 11830b57cec5SDimitry Andric // 11840b57cec5SDimitry Andric // VST2ln 11850b57cec5SDimitry Andric InstrItinData<IIC_VST2ln, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 11860b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 11870b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 11880b57cec5SDimitry Andric InstrStage<1, [A9_DRegsVFP], 0, Reserved>, 11890b57cec5SDimitry Andric InstrStage<1, [A9_NPipe], 0>, 11900b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], 11910b57cec5SDimitry Andric [1, 1, 1, 1]>, 11920b57cec5SDimitry Andric // 11930b57cec5SDimitry Andric // VST2lnu 11940b57cec5SDimitry Andric InstrItinData<IIC_VST2lnu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 11950b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 11960b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 11970b57cec5SDimitry Andric InstrStage<1, [A9_DRegsVFP], 0, Reserved>, 11980b57cec5SDimitry Andric InstrStage<1, [A9_NPipe], 0>, 11990b57cec5SDimitry Andric InstrStage<1, [A9_LSUnit]>], 12000b57cec5SDimitry Andric [2, 1, 1, 1, 1, 1]>, 12010b57cec5SDimitry Andric // 12020b57cec5SDimitry Andric // VST3 12030b57cec5SDimitry Andric InstrItinData<IIC_VST3, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 12040b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 12050b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 12060b57cec5SDimitry Andric InstrStage<2, [A9_DRegsVFP], 0, Reserved>, 12070b57cec5SDimitry Andric InstrStage<2, [A9_NPipe], 0>, 12080b57cec5SDimitry Andric InstrStage<2, [A9_LSUnit]>], 12090b57cec5SDimitry Andric [1, 1, 1, 1, 2]>, 12100b57cec5SDimitry Andric // 12110b57cec5SDimitry Andric // VST3u 12120b57cec5SDimitry Andric InstrItinData<IIC_VST3u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 12130b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 12140b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 12150b57cec5SDimitry Andric InstrStage<2, [A9_DRegsVFP], 0, Reserved>, 12160b57cec5SDimitry Andric InstrStage<2, [A9_NPipe], 0>, 12170b57cec5SDimitry Andric InstrStage<2, [A9_LSUnit]>], 12180b57cec5SDimitry Andric [2, 1, 1, 1, 1, 1, 2]>, 12190b57cec5SDimitry Andric // 12200b57cec5SDimitry Andric // VST3ln 12210b57cec5SDimitry Andric InstrItinData<IIC_VST3ln, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 12220b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 12230b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 12240b57cec5SDimitry Andric InstrStage<3, [A9_DRegsVFP], 0, Reserved>, 12250b57cec5SDimitry Andric InstrStage<3, [A9_NPipe], 0>, 12260b57cec5SDimitry Andric InstrStage<3, [A9_LSUnit]>], 12270b57cec5SDimitry Andric [1, 1, 1, 1, 2]>, 12280b57cec5SDimitry Andric // 12290b57cec5SDimitry Andric // VST3lnu 12300b57cec5SDimitry Andric InstrItinData<IIC_VST3lnu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 12310b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 12320b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 12330b57cec5SDimitry Andric InstrStage<3, [A9_DRegsVFP], 0, Reserved>, 12340b57cec5SDimitry Andric InstrStage<3, [A9_NPipe], 0>, 12350b57cec5SDimitry Andric InstrStage<3, [A9_LSUnit]>], 12360b57cec5SDimitry Andric [2, 1, 1, 1, 1, 1, 2]>, 12370b57cec5SDimitry Andric // 12380b57cec5SDimitry Andric // VST4 12390b57cec5SDimitry Andric InstrItinData<IIC_VST4, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 12400b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 12410b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 12420b57cec5SDimitry Andric InstrStage<2, [A9_DRegsVFP], 0, Reserved>, 12430b57cec5SDimitry Andric InstrStage<2, [A9_NPipe], 0>, 12440b57cec5SDimitry Andric InstrStage<2, [A9_LSUnit]>], 12450b57cec5SDimitry Andric [1, 1, 1, 1, 2, 2]>, 12460b57cec5SDimitry Andric // 12470b57cec5SDimitry Andric // VST4u 12480b57cec5SDimitry Andric InstrItinData<IIC_VST4u, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 12490b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 12500b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 12510b57cec5SDimitry Andric InstrStage<2, [A9_DRegsVFP], 0, Reserved>, 12520b57cec5SDimitry Andric InstrStage<2, [A9_NPipe], 0>, 12530b57cec5SDimitry Andric InstrStage<2, [A9_LSUnit]>], 12540b57cec5SDimitry Andric [2, 1, 1, 1, 1, 1, 2, 2]>, 12550b57cec5SDimitry Andric // 12560b57cec5SDimitry Andric // VST4ln 12570b57cec5SDimitry Andric InstrItinData<IIC_VST4ln, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 12580b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 12590b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 12600b57cec5SDimitry Andric InstrStage<2, [A9_DRegsVFP], 0, Reserved>, 12610b57cec5SDimitry Andric InstrStage<2, [A9_NPipe], 0>, 12620b57cec5SDimitry Andric InstrStage<2, [A9_LSUnit]>], 12630b57cec5SDimitry Andric [1, 1, 1, 1, 2, 2]>, 12640b57cec5SDimitry Andric // 12650b57cec5SDimitry Andric // VST4lnu 12660b57cec5SDimitry Andric InstrItinData<IIC_VST4lnu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 12670b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 12680b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 12690b57cec5SDimitry Andric InstrStage<2, [A9_DRegsVFP], 0, Reserved>, 12700b57cec5SDimitry Andric InstrStage<2, [A9_NPipe], 0>, 12710b57cec5SDimitry Andric InstrStage<2, [A9_LSUnit]>], 12720b57cec5SDimitry Andric [2, 1, 1, 1, 1, 1, 2, 2]>, 12730b57cec5SDimitry Andric 12740b57cec5SDimitry Andric // 12750b57cec5SDimitry Andric // Double-register Integer Unary 12760b57cec5SDimitry Andric InstrItinData<IIC_VUNAiD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 12770b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 12780b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 12790b57cec5SDimitry Andric // Extra latency cycles since wbck is 6 cycles 12800b57cec5SDimitry Andric InstrStage<7, [A9_DRegsVFP], 0, Reserved>, 12810b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 12820b57cec5SDimitry Andric [4, 2]>, 12830b57cec5SDimitry Andric // 12840b57cec5SDimitry Andric // Quad-register Integer Unary 12850b57cec5SDimitry Andric InstrItinData<IIC_VUNAiQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 12860b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 12870b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 12880b57cec5SDimitry Andric // Extra latency cycles since wbck is 6 cycles 12890b57cec5SDimitry Andric InstrStage<7, [A9_DRegsVFP], 0, Reserved>, 12900b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 12910b57cec5SDimitry Andric [4, 2]>, 12920b57cec5SDimitry Andric // 12930b57cec5SDimitry Andric // Double-register Integer Q-Unary 12940b57cec5SDimitry Andric InstrItinData<IIC_VQUNAiD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 12950b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 12960b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 12970b57cec5SDimitry Andric // Extra latency cycles since wbck is 6 cycles 12980b57cec5SDimitry Andric InstrStage<7, [A9_DRegsVFP], 0, Reserved>, 12990b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 13000b57cec5SDimitry Andric [4, 1]>, 13010b57cec5SDimitry Andric // 13020b57cec5SDimitry Andric // Quad-register Integer CountQ-Unary 13030b57cec5SDimitry Andric InstrItinData<IIC_VQUNAiQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 13040b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 13050b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 13060b57cec5SDimitry Andric // Extra latency cycles since wbck is 6 cycles 13070b57cec5SDimitry Andric InstrStage<7, [A9_DRegsVFP], 0, Reserved>, 13080b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 13090b57cec5SDimitry Andric [4, 1]>, 13100b57cec5SDimitry Andric // 13110b57cec5SDimitry Andric // Double-register Integer Binary 13120b57cec5SDimitry Andric InstrItinData<IIC_VBINiD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 13130b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 13140b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 13150b57cec5SDimitry Andric // Extra latency cycles since wbck is 6 cycles 13160b57cec5SDimitry Andric InstrStage<7, [A9_DRegsVFP], 0, Reserved>, 13170b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 13180b57cec5SDimitry Andric [3, 2, 2]>, 13190b57cec5SDimitry Andric // 13200b57cec5SDimitry Andric // Quad-register Integer Binary 13210b57cec5SDimitry Andric InstrItinData<IIC_VBINiQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 13220b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 13230b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 13240b57cec5SDimitry Andric // Extra latency cycles since wbck is 6 cycles 13250b57cec5SDimitry Andric InstrStage<7, [A9_DRegsVFP], 0, Reserved>, 13260b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 13270b57cec5SDimitry Andric [3, 2, 2]>, 13280b57cec5SDimitry Andric // 13290b57cec5SDimitry Andric // Double-register Integer Subtract 13300b57cec5SDimitry Andric InstrItinData<IIC_VSUBiD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 13310b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 13320b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 13330b57cec5SDimitry Andric // Extra latency cycles since wbck is 6 cycles 13340b57cec5SDimitry Andric InstrStage<7, [A9_DRegsVFP], 0, Reserved>, 13350b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 13360b57cec5SDimitry Andric [3, 2, 1]>, 13370b57cec5SDimitry Andric // 13380b57cec5SDimitry Andric // Quad-register Integer Subtract 13390b57cec5SDimitry Andric InstrItinData<IIC_VSUBiQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 13400b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 13410b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 13420b57cec5SDimitry Andric // Extra latency cycles since wbck is 6 cycles 13430b57cec5SDimitry Andric InstrStage<7, [A9_DRegsVFP], 0, Reserved>, 13440b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 13450b57cec5SDimitry Andric [3, 2, 1]>, 13460b57cec5SDimitry Andric // 13470b57cec5SDimitry Andric // Double-register Integer Shift 13480b57cec5SDimitry Andric InstrItinData<IIC_VSHLiD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 13490b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 13500b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 13510b57cec5SDimitry Andric // Extra latency cycles since wbck is 6 cycles 13520b57cec5SDimitry Andric InstrStage<7, [A9_DRegsVFP], 0, Reserved>, 13530b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 13540b57cec5SDimitry Andric [3, 1, 1]>, 13550b57cec5SDimitry Andric // 13560b57cec5SDimitry Andric // Quad-register Integer Shift 13570b57cec5SDimitry Andric InstrItinData<IIC_VSHLiQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 13580b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 13590b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 13600b57cec5SDimitry Andric // Extra latency cycles since wbck is 6 cycles 13610b57cec5SDimitry Andric InstrStage<7, [A9_DRegsVFP], 0, Reserved>, 13620b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 13630b57cec5SDimitry Andric [3, 1, 1]>, 13640b57cec5SDimitry Andric // 13650b57cec5SDimitry Andric // Double-register Integer Shift (4 cycle) 13660b57cec5SDimitry Andric InstrItinData<IIC_VSHLi4D, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 13670b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 13680b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 13690b57cec5SDimitry Andric // Extra latency cycles since wbck is 6 cycles 13700b57cec5SDimitry Andric InstrStage<7, [A9_DRegsVFP], 0, Reserved>, 13710b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 13720b57cec5SDimitry Andric [4, 1, 1]>, 13730b57cec5SDimitry Andric // 13740b57cec5SDimitry Andric // Quad-register Integer Shift (4 cycle) 13750b57cec5SDimitry Andric InstrItinData<IIC_VSHLi4Q, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 13760b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 13770b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 13780b57cec5SDimitry Andric // Extra latency cycles since wbck is 6 cycles 13790b57cec5SDimitry Andric InstrStage<7, [A9_DRegsVFP], 0, Reserved>, 13800b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 13810b57cec5SDimitry Andric [4, 1, 1]>, 13820b57cec5SDimitry Andric // 13830b57cec5SDimitry Andric // Double-register Integer Binary (4 cycle) 13840b57cec5SDimitry Andric InstrItinData<IIC_VBINi4D, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 13850b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 13860b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 13870b57cec5SDimitry Andric // Extra latency cycles since wbck is 6 cycles 13880b57cec5SDimitry Andric InstrStage<7, [A9_DRegsVFP], 0, Reserved>, 13890b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 13900b57cec5SDimitry Andric [4, 2, 2]>, 13910b57cec5SDimitry Andric // 13920b57cec5SDimitry Andric // Quad-register Integer Binary (4 cycle) 13930b57cec5SDimitry Andric InstrItinData<IIC_VBINi4Q, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 13940b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 13950b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 13960b57cec5SDimitry Andric // Extra latency cycles since wbck is 6 cycles 13970b57cec5SDimitry Andric InstrStage<7, [A9_DRegsVFP], 0, Reserved>, 13980b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 13990b57cec5SDimitry Andric [4, 2, 2]>, 14000b57cec5SDimitry Andric // 14010b57cec5SDimitry Andric // Double-register Integer Subtract (4 cycle) 14020b57cec5SDimitry Andric InstrItinData<IIC_VSUBi4D, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 14030b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 14040b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 14050b57cec5SDimitry Andric // Extra latency cycles since wbck is 6 cycles 14060b57cec5SDimitry Andric InstrStage<7, [A9_DRegsVFP], 0, Reserved>, 14070b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 14080b57cec5SDimitry Andric [4, 2, 1]>, 14090b57cec5SDimitry Andric // 14100b57cec5SDimitry Andric // Quad-register Integer Subtract (4 cycle) 14110b57cec5SDimitry Andric InstrItinData<IIC_VSUBi4Q, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 14120b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 14130b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 14140b57cec5SDimitry Andric // Extra latency cycles since wbck is 6 cycles 14150b57cec5SDimitry Andric InstrStage<7, [A9_DRegsVFP], 0, Reserved>, 14160b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 14170b57cec5SDimitry Andric [4, 2, 1]>, 14180b57cec5SDimitry Andric 14190b57cec5SDimitry Andric // 14200b57cec5SDimitry Andric // Double-register Integer Count 14210b57cec5SDimitry Andric InstrItinData<IIC_VCNTiD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 14220b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 14230b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 14240b57cec5SDimitry Andric // Extra latency cycles since wbck is 6 cycles 14250b57cec5SDimitry Andric InstrStage<7, [A9_DRegsVFP], 0, Reserved>, 14260b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 14270b57cec5SDimitry Andric [3, 2, 2]>, 14280b57cec5SDimitry Andric // 14290b57cec5SDimitry Andric // Quad-register Integer Count 14300b57cec5SDimitry Andric // Result written in N3, but that is relative to the last cycle of multicycle, 14310b57cec5SDimitry Andric // so we use 4 for those cases 14320b57cec5SDimitry Andric InstrItinData<IIC_VCNTiQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 14330b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 14340b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 14350b57cec5SDimitry Andric // Extra latency cycles since wbck is 7 cycles 14360b57cec5SDimitry Andric InstrStage<8, [A9_DRegsVFP], 0, Reserved>, 14370b57cec5SDimitry Andric InstrStage<2, [A9_NPipe]>], 14380b57cec5SDimitry Andric [4, 2, 2]>, 14390b57cec5SDimitry Andric // 14400b57cec5SDimitry Andric // Double-register Absolute Difference and Accumulate 14410b57cec5SDimitry Andric InstrItinData<IIC_VABAD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 14420b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 14430b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 14440b57cec5SDimitry Andric // Extra latency cycles since wbck is 6 cycles 14450b57cec5SDimitry Andric InstrStage<7, [A9_DRegsVFP], 0, Reserved>, 14460b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 14470b57cec5SDimitry Andric [6, 3, 2, 1]>, 14480b57cec5SDimitry Andric // 14490b57cec5SDimitry Andric // Quad-register Absolute Difference and Accumulate 14500b57cec5SDimitry Andric InstrItinData<IIC_VABAQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 14510b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 14520b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 14530b57cec5SDimitry Andric // Extra latency cycles since wbck is 6 cycles 14540b57cec5SDimitry Andric InstrStage<7, [A9_DRegsVFP], 0, Reserved>, 14550b57cec5SDimitry Andric InstrStage<2, [A9_NPipe]>], 14560b57cec5SDimitry Andric [6, 3, 2, 1]>, 14570b57cec5SDimitry Andric // 14580b57cec5SDimitry Andric // Double-register Integer Pair Add Long 14590b57cec5SDimitry Andric InstrItinData<IIC_VPALiD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 14600b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 14610b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 14620b57cec5SDimitry Andric // Extra latency cycles since wbck is 6 cycles 14630b57cec5SDimitry Andric InstrStage<7, [A9_DRegsVFP], 0, Reserved>, 14640b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 14650b57cec5SDimitry Andric [6, 3, 1]>, 14660b57cec5SDimitry Andric // 14670b57cec5SDimitry Andric // Quad-register Integer Pair Add Long 14680b57cec5SDimitry Andric InstrItinData<IIC_VPALiQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 14690b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 14700b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 14710b57cec5SDimitry Andric // Extra latency cycles since wbck is 6 cycles 14720b57cec5SDimitry Andric InstrStage<7, [A9_DRegsVFP], 0, Reserved>, 14730b57cec5SDimitry Andric InstrStage<2, [A9_NPipe]>], 14740b57cec5SDimitry Andric [6, 3, 1]>, 14750b57cec5SDimitry Andric 14760b57cec5SDimitry Andric // 14770b57cec5SDimitry Andric // Double-register Integer Multiply (.8, .16) 14780b57cec5SDimitry Andric InstrItinData<IIC_VMULi16D, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 14790b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 14800b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 14810b57cec5SDimitry Andric // Extra latency cycles since wbck is 6 cycles 14820b57cec5SDimitry Andric InstrStage<7, [A9_DRegsVFP], 0, Reserved>, 14830b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 14840b57cec5SDimitry Andric [6, 2, 2]>, 14850b57cec5SDimitry Andric // 14860b57cec5SDimitry Andric // Quad-register Integer Multiply (.8, .16) 14870b57cec5SDimitry Andric InstrItinData<IIC_VMULi16Q, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 14880b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 14890b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 14900b57cec5SDimitry Andric // Extra latency cycles since wbck is 7 cycles 14910b57cec5SDimitry Andric InstrStage<8, [A9_DRegsVFP], 0, Reserved>, 14920b57cec5SDimitry Andric InstrStage<2, [A9_NPipe]>], 14930b57cec5SDimitry Andric [7, 2, 2]>, 14940b57cec5SDimitry Andric 14950b57cec5SDimitry Andric // 14960b57cec5SDimitry Andric // Double-register Integer Multiply (.32) 14970b57cec5SDimitry Andric InstrItinData<IIC_VMULi32D, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 14980b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 14990b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 15000b57cec5SDimitry Andric // Extra latency cycles since wbck is 7 cycles 15010b57cec5SDimitry Andric InstrStage<8, [A9_DRegsVFP], 0, Reserved>, 15020b57cec5SDimitry Andric InstrStage<2, [A9_NPipe]>], 15030b57cec5SDimitry Andric [7, 2, 1]>, 15040b57cec5SDimitry Andric // 15050b57cec5SDimitry Andric // Quad-register Integer Multiply (.32) 15060b57cec5SDimitry Andric InstrItinData<IIC_VMULi32Q, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 15070b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 15080b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 15090b57cec5SDimitry Andric // Extra latency cycles since wbck is 9 cycles 15100b57cec5SDimitry Andric InstrStage<10, [A9_DRegsVFP], 0, Reserved>, 15110b57cec5SDimitry Andric InstrStage<4, [A9_NPipe]>], 15120b57cec5SDimitry Andric [9, 2, 1]>, 15130b57cec5SDimitry Andric // 15140b57cec5SDimitry Andric // Double-register Integer Multiply-Accumulate (.8, .16) 15150b57cec5SDimitry Andric InstrItinData<IIC_VMACi16D, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 15160b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 15170b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 15180b57cec5SDimitry Andric // Extra latency cycles since wbck is 6 cycles 15190b57cec5SDimitry Andric InstrStage<7, [A9_DRegsVFP], 0, Reserved>, 15200b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 15210b57cec5SDimitry Andric [6, 3, 2, 2]>, 15220b57cec5SDimitry Andric // 15230b57cec5SDimitry Andric // Double-register Integer Multiply-Accumulate (.32) 15240b57cec5SDimitry Andric InstrItinData<IIC_VMACi32D, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 15250b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 15260b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 15270b57cec5SDimitry Andric // Extra latency cycles since wbck is 7 cycles 15280b57cec5SDimitry Andric InstrStage<8, [A9_DRegsVFP], 0, Reserved>, 15290b57cec5SDimitry Andric InstrStage<2, [A9_NPipe]>], 15300b57cec5SDimitry Andric [7, 3, 2, 1]>, 15310b57cec5SDimitry Andric // 15320b57cec5SDimitry Andric // Quad-register Integer Multiply-Accumulate (.8, .16) 15330b57cec5SDimitry Andric InstrItinData<IIC_VMACi16Q, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 15340b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 15350b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 15360b57cec5SDimitry Andric // Extra latency cycles since wbck is 7 cycles 15370b57cec5SDimitry Andric InstrStage<8, [A9_DRegsVFP], 0, Reserved>, 15380b57cec5SDimitry Andric InstrStage<2, [A9_NPipe]>], 15390b57cec5SDimitry Andric [7, 3, 2, 2]>, 15400b57cec5SDimitry Andric // 15410b57cec5SDimitry Andric // Quad-register Integer Multiply-Accumulate (.32) 15420b57cec5SDimitry Andric InstrItinData<IIC_VMACi32Q, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 15430b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 15440b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 15450b57cec5SDimitry Andric // Extra latency cycles since wbck is 9 cycles 15460b57cec5SDimitry Andric InstrStage<10, [A9_DRegsVFP], 0, Reserved>, 15470b57cec5SDimitry Andric InstrStage<4, [A9_NPipe]>], 15480b57cec5SDimitry Andric [9, 3, 2, 1]>, 15490b57cec5SDimitry Andric 15500b57cec5SDimitry Andric // 15510b57cec5SDimitry Andric // Move 15520b57cec5SDimitry Andric InstrItinData<IIC_VMOV, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 15530b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 15540b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 15550b57cec5SDimitry Andric InstrStage<1, [A9_DRegsVFP], 0, Reserved>, 15560b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 15570b57cec5SDimitry Andric [1,1]>, 15580b57cec5SDimitry Andric // 15590b57cec5SDimitry Andric // Move Immediate 15600b57cec5SDimitry Andric InstrItinData<IIC_VMOVImm, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 15610b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 15620b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 15630b57cec5SDimitry Andric // Extra latency cycles since wbck is 6 cycles 15640b57cec5SDimitry Andric InstrStage<7, [A9_DRegsVFP], 0, Reserved>, 15650b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 15660b57cec5SDimitry Andric [3]>, 15670b57cec5SDimitry Andric // 15680b57cec5SDimitry Andric // Double-register Permute Move 15690b57cec5SDimitry Andric InstrItinData<IIC_VMOVD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 15700b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 15710b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 15720b57cec5SDimitry Andric // Extra latency cycles since wbck is 6 cycles 15730b57cec5SDimitry Andric InstrStage<7, [A9_DRegsVFP], 0, Reserved>, 15740b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 15750b57cec5SDimitry Andric [2, 1]>, 15760b57cec5SDimitry Andric // 15770b57cec5SDimitry Andric // Quad-register Permute Move 15780b57cec5SDimitry Andric InstrItinData<IIC_VMOVQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 15790b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 15800b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 15810b57cec5SDimitry Andric // Extra latency cycles since wbck is 6 cycles 15820b57cec5SDimitry Andric InstrStage<7, [A9_DRegsVFP], 0, Reserved>, 15830b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 15840b57cec5SDimitry Andric [2, 1]>, 15850b57cec5SDimitry Andric // 15860b57cec5SDimitry Andric // Integer to Single-precision Move 15870b57cec5SDimitry Andric InstrItinData<IIC_VMOVIS , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 15880b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 15890b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 15900b57cec5SDimitry Andric InstrStage<3, [A9_DRegsVFP], 0, Reserved>, 15910b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 15920b57cec5SDimitry Andric [1, 1]>, 15930b57cec5SDimitry Andric // 15940b57cec5SDimitry Andric // Integer to Double-precision Move 15950b57cec5SDimitry Andric InstrItinData<IIC_VMOVID , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 15960b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 15970b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 15980b57cec5SDimitry Andric InstrStage<3, [A9_DRegsVFP], 0, Reserved>, 15990b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 16000b57cec5SDimitry Andric [1, 1, 1]>, 16010b57cec5SDimitry Andric // 16020b57cec5SDimitry Andric // Single-precision to Integer Move 16030b57cec5SDimitry Andric InstrItinData<IIC_VMOVSI , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 16040b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 16050b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 16060b57cec5SDimitry Andric InstrStage<3, [A9_DRegsVFP], 0, Reserved>, 16070b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 16080b57cec5SDimitry Andric [2, 1]>, 16090b57cec5SDimitry Andric // 16100b57cec5SDimitry Andric // Double-precision to Integer Move 16110b57cec5SDimitry Andric InstrItinData<IIC_VMOVDI , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 16120b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 16130b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 16140b57cec5SDimitry Andric InstrStage<3, [A9_DRegsVFP], 0, Reserved>, 16150b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 16160b57cec5SDimitry Andric [2, 2, 1]>, 16170b57cec5SDimitry Andric // 16180b57cec5SDimitry Andric // Integer to Lane Move 16190b57cec5SDimitry Andric InstrItinData<IIC_VMOVISL , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 16200b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 16210b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 16220b57cec5SDimitry Andric InstrStage<4, [A9_DRegsVFP], 0, Reserved>, 16230b57cec5SDimitry Andric InstrStage<2, [A9_NPipe]>], 16240b57cec5SDimitry Andric [3, 1, 1]>, 16250b57cec5SDimitry Andric 16260b57cec5SDimitry Andric // 16270b57cec5SDimitry Andric // Vector narrow move 16280b57cec5SDimitry Andric InstrItinData<IIC_VMOVN, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 16290b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 16300b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 16310b57cec5SDimitry Andric // Extra latency cycles since wbck is 6 cycles 16320b57cec5SDimitry Andric InstrStage<7, [A9_DRegsVFP], 0, Reserved>, 16330b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 16340b57cec5SDimitry Andric [3, 1]>, 16350b57cec5SDimitry Andric // 16360b57cec5SDimitry Andric // Double-register FP Unary 16370b57cec5SDimitry Andric InstrItinData<IIC_VUNAD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 16380b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 16390b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 16400b57cec5SDimitry Andric // Extra latency cycles since wbck is 6 cycles 16410b57cec5SDimitry Andric InstrStage<7, [A9_DRegsVFP], 0, Reserved>, 16420b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 16430b57cec5SDimitry Andric [5, 2]>, 16440b57cec5SDimitry Andric // 16450b57cec5SDimitry Andric // Quad-register FP Unary 16460b57cec5SDimitry Andric // Result written in N5, but that is relative to the last cycle of multicycle, 16470b57cec5SDimitry Andric // so we use 6 for those cases 16480b57cec5SDimitry Andric InstrItinData<IIC_VUNAQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 16490b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 16500b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 16510b57cec5SDimitry Andric // Extra latency cycles since wbck is 7 cycles 16520b57cec5SDimitry Andric InstrStage<8, [A9_DRegsVFP], 0, Reserved>, 16530b57cec5SDimitry Andric InstrStage<2, [A9_NPipe]>], 16540b57cec5SDimitry Andric [6, 2]>, 16550b57cec5SDimitry Andric // 16560b57cec5SDimitry Andric // Double-register FP Binary 16570b57cec5SDimitry Andric // FIXME: We're using this itin for many instructions and [2, 2] here is too 16580b57cec5SDimitry Andric // optimistic. 16590b57cec5SDimitry Andric InstrItinData<IIC_VBIND, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 16600b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 16610b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 16620b57cec5SDimitry Andric // Extra latency cycles since wbck is 6 cycles 16630b57cec5SDimitry Andric InstrStage<7, [A9_DRegsVFP], 0, Reserved>, 16640b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 16650b57cec5SDimitry Andric [5, 2, 2]>, 16660b57cec5SDimitry Andric 16670b57cec5SDimitry Andric // 16680b57cec5SDimitry Andric // VPADD, etc. 16690b57cec5SDimitry Andric InstrItinData<IIC_VPBIND, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 16700b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 16710b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 16720b57cec5SDimitry Andric // Extra latency cycles since wbck is 6 cycles 16730b57cec5SDimitry Andric InstrStage<7, [A9_DRegsVFP], 0, Reserved>, 16740b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 16750b57cec5SDimitry Andric [5, 1, 1]>, 16760b57cec5SDimitry Andric // 16770b57cec5SDimitry Andric // Double-register FP VMUL 16780b57cec5SDimitry Andric InstrItinData<IIC_VFMULD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 16790b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 16800b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 16810b57cec5SDimitry Andric // Extra latency cycles since wbck is 6 cycles 16820b57cec5SDimitry Andric InstrStage<7, [A9_DRegsVFP], 0, Reserved>, 16830b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 16840b57cec5SDimitry Andric [5, 2, 1]>, 16850b57cec5SDimitry Andric // 16860b57cec5SDimitry Andric // Quad-register FP Binary 16870b57cec5SDimitry Andric // Result written in N5, but that is relative to the last cycle of multicycle, 16880b57cec5SDimitry Andric // so we use 6 for those cases 16890b57cec5SDimitry Andric // FIXME: We're using this itin for many instructions and [2, 2] here is too 16900b57cec5SDimitry Andric // optimistic. 16910b57cec5SDimitry Andric InstrItinData<IIC_VBINQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 16920b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 16930b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 16940b57cec5SDimitry Andric // Extra latency cycles since wbck is 7 cycles 16950b57cec5SDimitry Andric InstrStage<8, [A9_DRegsVFP], 0, Reserved>, 16960b57cec5SDimitry Andric InstrStage<2, [A9_NPipe]>], 16970b57cec5SDimitry Andric [6, 2, 2]>, 16980b57cec5SDimitry Andric // 16990b57cec5SDimitry Andric // Quad-register FP VMUL 17000b57cec5SDimitry Andric InstrItinData<IIC_VFMULQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 17010b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 17020b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 17030b57cec5SDimitry Andric // Extra latency cycles since wbck is 7 cycles 17040b57cec5SDimitry Andric InstrStage<8, [A9_DRegsVFP], 0, Reserved>, 17050b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 17060b57cec5SDimitry Andric [6, 2, 1]>, 17070b57cec5SDimitry Andric // 17080b57cec5SDimitry Andric // Double-register FP Multiple-Accumulate 17090b57cec5SDimitry Andric InstrItinData<IIC_VMACD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 17100b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 17110b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 17120b57cec5SDimitry Andric // Extra latency cycles since wbck is 7 cycles 17130b57cec5SDimitry Andric InstrStage<8, [A9_DRegsVFP], 0, Reserved>, 17140b57cec5SDimitry Andric InstrStage<2, [A9_NPipe]>], 17150b57cec5SDimitry Andric [6, 3, 2, 1]>, 17160b57cec5SDimitry Andric // 17170b57cec5SDimitry Andric // Quad-register FP Multiple-Accumulate 17180b57cec5SDimitry Andric // Result written in N9, but that is relative to the last cycle of multicycle, 17190b57cec5SDimitry Andric // so we use 10 for those cases 17200b57cec5SDimitry Andric InstrItinData<IIC_VMACQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 17210b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 17220b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 17230b57cec5SDimitry Andric // Extra latency cycles since wbck is 9 cycles 17240b57cec5SDimitry Andric InstrStage<10, [A9_DRegsVFP], 0, Reserved>, 17250b57cec5SDimitry Andric InstrStage<4, [A9_NPipe]>], 17260b57cec5SDimitry Andric [8, 4, 2, 1]>, 17270b57cec5SDimitry Andric // 17280b57cec5SDimitry Andric // Double-register Fused FP Multiple-Accumulate 17290b57cec5SDimitry Andric InstrItinData<IIC_VFMACD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 17300b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 17310b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 17320b57cec5SDimitry Andric // Extra latency cycles since wbck is 7 cycles 17330b57cec5SDimitry Andric InstrStage<8, [A9_DRegsVFP], 0, Reserved>, 17340b57cec5SDimitry Andric InstrStage<2, [A9_NPipe]>], 17350b57cec5SDimitry Andric [6, 3, 2, 1]>, 17360b57cec5SDimitry Andric // 17370b57cec5SDimitry Andric // Quad-register Fused FP Multiple-Accumulate 17380b57cec5SDimitry Andric // Result written in N9, but that is relative to the last cycle of multicycle, 17390b57cec5SDimitry Andric // so we use 10 for those cases 17400b57cec5SDimitry Andric InstrItinData<IIC_VFMACQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 17410b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 17420b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 17430b57cec5SDimitry Andric // Extra latency cycles since wbck is 9 cycles 17440b57cec5SDimitry Andric InstrStage<10, [A9_DRegsVFP], 0, Reserved>, 17450b57cec5SDimitry Andric InstrStage<4, [A9_NPipe]>], 17460b57cec5SDimitry Andric [8, 4, 2, 1]>, 17470b57cec5SDimitry Andric // 17480b57cec5SDimitry Andric // Double-register Reciprical Step 17490b57cec5SDimitry Andric InstrItinData<IIC_VRECSD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 17500b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 17510b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 17520b57cec5SDimitry Andric // Extra latency cycles since wbck is 10 cycles 17530b57cec5SDimitry Andric InstrStage<11, [A9_DRegsVFP], 0, Reserved>, 17540b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 17550b57cec5SDimitry Andric [9, 2, 2]>, 17560b57cec5SDimitry Andric // 17570b57cec5SDimitry Andric // Quad-register Reciprical Step 17580b57cec5SDimitry Andric InstrItinData<IIC_VRECSQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 17590b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 17600b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 17610b57cec5SDimitry Andric // Extra latency cycles since wbck is 11 cycles 17620b57cec5SDimitry Andric InstrStage<12, [A9_DRegsVFP], 0, Reserved>, 17630b57cec5SDimitry Andric InstrStage<2, [A9_NPipe]>], 17640b57cec5SDimitry Andric [10, 2, 2]>, 17650b57cec5SDimitry Andric // 17660b57cec5SDimitry Andric // Double-register Permute 17670b57cec5SDimitry Andric InstrItinData<IIC_VPERMD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 17680b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 17690b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 17700b57cec5SDimitry Andric // Extra latency cycles since wbck is 6 cycles 17710b57cec5SDimitry Andric InstrStage<7, [A9_DRegsVFP], 0, Reserved>, 17720b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 17730b57cec5SDimitry Andric [2, 2, 1, 1]>, 17740b57cec5SDimitry Andric // 17750b57cec5SDimitry Andric // Quad-register Permute 17760b57cec5SDimitry Andric // Result written in N2, but that is relative to the last cycle of multicycle, 17770b57cec5SDimitry Andric // so we use 3 for those cases 17780b57cec5SDimitry Andric InstrItinData<IIC_VPERMQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 17790b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 17800b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 17810b57cec5SDimitry Andric // Extra latency cycles since wbck is 7 cycles 17820b57cec5SDimitry Andric InstrStage<8, [A9_DRegsVFP], 0, Reserved>, 17830b57cec5SDimitry Andric InstrStage<2, [A9_NPipe]>], 17840b57cec5SDimitry Andric [3, 3, 1, 1]>, 17850b57cec5SDimitry Andric // 17860b57cec5SDimitry Andric // Quad-register Permute (3 cycle issue) 17870b57cec5SDimitry Andric // Result written in N2, but that is relative to the last cycle of multicycle, 17880b57cec5SDimitry Andric // so we use 4 for those cases 17890b57cec5SDimitry Andric InstrItinData<IIC_VPERMQ3, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 17900b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 17910b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 17920b57cec5SDimitry Andric // Extra latency cycles since wbck is 8 cycles 17930b57cec5SDimitry Andric InstrStage<9, [A9_DRegsVFP], 0, Reserved>, 17940b57cec5SDimitry Andric InstrStage<3, [A9_NPipe]>], 17950b57cec5SDimitry Andric [4, 4, 1, 1]>, 17960b57cec5SDimitry Andric 17970b57cec5SDimitry Andric // 17980b57cec5SDimitry Andric // Double-register VEXT 17990b57cec5SDimitry Andric InstrItinData<IIC_VEXTD, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 18000b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 18010b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 18020b57cec5SDimitry Andric // Extra latency cycles since wbck is 6 cycles 18030b57cec5SDimitry Andric InstrStage<7, [A9_DRegsVFP], 0, Reserved>, 18040b57cec5SDimitry Andric InstrStage<1, [A9_NPipe]>], 18050b57cec5SDimitry Andric [2, 1, 1]>, 18060b57cec5SDimitry Andric // 18070b57cec5SDimitry Andric // Quad-register VEXT 18080b57cec5SDimitry Andric InstrItinData<IIC_VEXTQ, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 18090b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 18100b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 18110b57cec5SDimitry Andric // Extra latency cycles since wbck is 7 cycles 18120b57cec5SDimitry Andric InstrStage<8, [A9_DRegsVFP], 0, Reserved>, 18130b57cec5SDimitry Andric InstrStage<2, [A9_NPipe]>], 18140b57cec5SDimitry Andric [3, 1, 2]>, 18150b57cec5SDimitry Andric // 18160b57cec5SDimitry Andric // VTB 18170b57cec5SDimitry Andric InstrItinData<IIC_VTB1, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 18180b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 18190b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 18200b57cec5SDimitry Andric // Extra latency cycles since wbck is 7 cycles 18210b57cec5SDimitry Andric InstrStage<8, [A9_DRegsVFP], 0, Reserved>, 18220b57cec5SDimitry Andric InstrStage<2, [A9_NPipe]>], 18230b57cec5SDimitry Andric [3, 2, 1]>, 18240b57cec5SDimitry Andric InstrItinData<IIC_VTB2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 18250b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 18260b57cec5SDimitry Andric InstrStage<2, [A9_DRegsN], 0, Required>, 18270b57cec5SDimitry Andric // Extra latency cycles since wbck is 7 cycles 18280b57cec5SDimitry Andric InstrStage<8, [A9_DRegsVFP], 0, Reserved>, 18290b57cec5SDimitry Andric InstrStage<2, [A9_NPipe]>], 18300b57cec5SDimitry Andric [3, 2, 2, 1]>, 18310b57cec5SDimitry Andric InstrItinData<IIC_VTB3, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 18320b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 18330b57cec5SDimitry Andric InstrStage<2, [A9_DRegsN], 0, Required>, 18340b57cec5SDimitry Andric // Extra latency cycles since wbck is 8 cycles 18350b57cec5SDimitry Andric InstrStage<9, [A9_DRegsVFP], 0, Reserved>, 18360b57cec5SDimitry Andric InstrStage<3, [A9_NPipe]>], 18370b57cec5SDimitry Andric [4, 2, 2, 3, 1]>, 18380b57cec5SDimitry Andric InstrItinData<IIC_VTB4, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 18390b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 18400b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 18410b57cec5SDimitry Andric // Extra latency cycles since wbck is 8 cycles 18420b57cec5SDimitry Andric InstrStage<9, [A9_DRegsVFP], 0, Reserved>, 18430b57cec5SDimitry Andric InstrStage<3, [A9_NPipe]>], 18440b57cec5SDimitry Andric [4, 2, 2, 3, 3, 1]>, 18450b57cec5SDimitry Andric // 18460b57cec5SDimitry Andric // VTBX 18470b57cec5SDimitry Andric InstrItinData<IIC_VTBX1, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 18480b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 18490b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 18500b57cec5SDimitry Andric // Extra latency cycles since wbck is 7 cycles 18510b57cec5SDimitry Andric InstrStage<8, [A9_DRegsVFP], 0, Reserved>, 18520b57cec5SDimitry Andric InstrStage<2, [A9_NPipe]>], 18530b57cec5SDimitry Andric [3, 1, 2, 1]>, 18540b57cec5SDimitry Andric InstrItinData<IIC_VTBX2, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 18550b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 18560b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 18570b57cec5SDimitry Andric // Extra latency cycles since wbck is 7 cycles 18580b57cec5SDimitry Andric InstrStage<8, [A9_DRegsVFP], 0, Reserved>, 18590b57cec5SDimitry Andric InstrStage<2, [A9_NPipe]>], 18600b57cec5SDimitry Andric [3, 1, 2, 2, 1]>, 18610b57cec5SDimitry Andric InstrItinData<IIC_VTBX3, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 18620b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 18630b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 18640b57cec5SDimitry Andric // Extra latency cycles since wbck is 8 cycles 18650b57cec5SDimitry Andric InstrStage<9, [A9_DRegsVFP], 0, Reserved>, 18660b57cec5SDimitry Andric InstrStage<3, [A9_NPipe]>], 18670b57cec5SDimitry Andric [4, 1, 2, 2, 3, 1]>, 18680b57cec5SDimitry Andric InstrItinData<IIC_VTBX4, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 18690b57cec5SDimitry Andric InstrStage<1, [A9_MUX0], 0>, 18700b57cec5SDimitry Andric InstrStage<1, [A9_DRegsN], 0, Required>, 18710b57cec5SDimitry Andric // Extra latency cycles since wbck is 8 cycles 18720b57cec5SDimitry Andric InstrStage<9, [A9_DRegsVFP], 0, Reserved>, 18730b57cec5SDimitry Andric InstrStage<2, [A9_NPipe]>], 18740b57cec5SDimitry Andric [4, 1, 2, 2, 3, 3, 1]> 18750b57cec5SDimitry Andric]>; 18760b57cec5SDimitry Andric 18770b57cec5SDimitry Andric// ===---------------------------------------------------------------------===// 18780b57cec5SDimitry Andric// The following definitions describe the simpler per-operand machine model. 18790b57cec5SDimitry Andric// This works with MachineScheduler and will eventually replace itineraries. 18800b57cec5SDimitry Andric 18810b57cec5SDimitry Andricclass A9WriteLMOpsListType<list<WriteSequence> writes> { 18820b57cec5SDimitry Andric list <WriteSequence> Writes = writes; 18830b57cec5SDimitry Andric SchedMachineModel SchedModel = ?; 18840b57cec5SDimitry Andric} 18850b57cec5SDimitry Andric 18860b57cec5SDimitry Andric// Cortex-A9 machine model for scheduling and other instruction cost heuristics. 18870b57cec5SDimitry Andricdef CortexA9Model : SchedMachineModel { 18880b57cec5SDimitry Andric let IssueWidth = 2; // 2 micro-ops are dispatched per cycle. 18890b57cec5SDimitry Andric let MicroOpBufferSize = 56; // Based on available renamed registers. 18900b57cec5SDimitry Andric let LoadLatency = 2; // Optimistic load latency assuming bypass. 18910b57cec5SDimitry Andric // This is overriden by OperandCycles if the 18920b57cec5SDimitry Andric // Itineraries are queried instead. 18930b57cec5SDimitry Andric let MispredictPenalty = 8; // Based on estimate of pipeline depth. 18940b57cec5SDimitry Andric 18950b57cec5SDimitry Andric let Itineraries = CortexA9Itineraries; 18960b57cec5SDimitry Andric 18970b57cec5SDimitry Andric // FIXME: Many vector operations were never given an itinerary. We 18980b57cec5SDimitry Andric // haven't mapped these to the new model either. 18990b57cec5SDimitry Andric let CompleteModel = 0; 19000b57cec5SDimitry Andric 19010b57cec5SDimitry Andric // FIXME: Remove when all errors have been fixed. 19020b57cec5SDimitry Andric let FullInstRWOverlapCheck = 0; 19030b57cec5SDimitry Andric} 19040b57cec5SDimitry Andric 19050b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 19060b57cec5SDimitry Andric// Define each kind of processor resource and number available. 19070b57cec5SDimitry Andric// 19080b57cec5SDimitry Andric// The AGU unit has BufferSize=1 so that the latency between operations 19090b57cec5SDimitry Andric// that use it are considered to stall other operations. 19100b57cec5SDimitry Andric// 19110b57cec5SDimitry Andric// The FP unit has BufferSize=0 so that it is a hard dispatch 19120b57cec5SDimitry Andric// hazard. No instruction may be dispatched while the unit is reserved. 19130b57cec5SDimitry Andric 19140b57cec5SDimitry Andriclet SchedModel = CortexA9Model in { 19150b57cec5SDimitry Andric 19160b57cec5SDimitry Andricdef A9UnitALU : ProcResource<2>; 19170b57cec5SDimitry Andricdef A9UnitMul : ProcResource<1> { let Super = A9UnitALU; } 19180b57cec5SDimitry Andricdef A9UnitAGU : ProcResource<1> { let BufferSize = 1; } 19190b57cec5SDimitry Andricdef A9UnitLS : ProcResource<1>; 19200b57cec5SDimitry Andricdef A9UnitFP : ProcResource<1> { let BufferSize = 0; } 19210b57cec5SDimitry Andricdef A9UnitB : ProcResource<1>; 19220b57cec5SDimitry Andric 19230b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 19240b57cec5SDimitry Andric// Define scheduler read/write types with their resources and latency on A9. 19250b57cec5SDimitry Andric 19260b57cec5SDimitry Andric// Consume an issue slot, but no processor resources. This is useful when all 19270b57cec5SDimitry Andric// other writes associated with the operand have NumMicroOps = 0. 19280b57cec5SDimitry Andricdef A9WriteIssue : SchedWriteRes<[]> { let Latency = 0; } 19290b57cec5SDimitry Andric 19300b57cec5SDimitry Andric// Write an integer register. 19310b57cec5SDimitry Andricdef A9WriteI : SchedWriteRes<[A9UnitALU]>; 19320b57cec5SDimitry Andric// Write an integer shifted-by register 19330b57cec5SDimitry Andricdef A9WriteIsr : SchedWriteRes<[A9UnitALU]> { let Latency = 2; } 19340b57cec5SDimitry Andric 19350b57cec5SDimitry Andric// Basic ALU. 19360b57cec5SDimitry Andricdef A9WriteALU : SchedWriteRes<[A9UnitALU]>; 19370b57cec5SDimitry Andric// ALU with operand shifted by immediate. 19380b57cec5SDimitry Andricdef : WriteRes<WriteALUsi, [A9UnitALU]> { let Latency = 2; } 19390b57cec5SDimitry Andric// ALU with operand shifted by register. 19400b57cec5SDimitry Andricdef A9WriteALUsr : SchedWriteRes<[A9UnitALU]> { let Latency = 3; } 19410b57cec5SDimitry Andric 19420b57cec5SDimitry Andric// Multiplication 19430b57cec5SDimitry Andricdef A9WriteM : SchedWriteRes<[A9UnitMul, A9UnitMul]> { let Latency = 4; } 19440b57cec5SDimitry Andricdef A9WriteMHi : SchedWriteRes<[A9UnitMul]> { let Latency = 5; 19450b57cec5SDimitry Andric let NumMicroOps = 0; } 19460b57cec5SDimitry Andricdef A9WriteM16 : SchedWriteRes<[A9UnitMul]> { let Latency = 3; } 19470b57cec5SDimitry Andricdef A9WriteM16Hi : SchedWriteRes<[A9UnitMul]> { let Latency = 4; 19480b57cec5SDimitry Andric let NumMicroOps = 0; } 19490b57cec5SDimitry Andricdef : SchedAlias<WriteMUL16, A9WriteM16>; 19500b57cec5SDimitry Andricdef : SchedAlias<WriteMUL32, A9WriteM>; 19510b57cec5SDimitry Andricdef : SchedAlias<WriteMUL64Lo, A9WriteM>; 19520b57cec5SDimitry Andricdef : SchedAlias<WriteMUL64Hi, A9WriteMHi>; 19530b57cec5SDimitry Andricdef : SchedAlias<WriteMAC16, A9WriteM16>; 19540b57cec5SDimitry Andricdef : SchedAlias<WriteMAC32, A9WriteM>; 19550b57cec5SDimitry Andricdef : SchedAlias<WriteMAC64Lo, A9WriteM>; 19560b57cec5SDimitry Andricdef : SchedAlias<WriteMAC64Hi, A9WriteMHi>; 19570b57cec5SDimitry Andricdef : ReadAdvance<ReadMUL, 0>; 19580b57cec5SDimitry Andricdef : ReadAdvance<ReadMAC, 0>; 19590b57cec5SDimitry Andric 19600b57cec5SDimitry Andric// Floating-point 19610b57cec5SDimitry Andric// Only one FP or AGU instruction may issue per cycle. We model this 19620b57cec5SDimitry Andric// by having FP instructions consume the AGU resource. 19630b57cec5SDimitry Andricdef A9WriteF : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 4; } 19640b57cec5SDimitry Andricdef A9WriteFMov : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 1; } 19650b57cec5SDimitry Andricdef A9WriteFMulS : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 5; } 19660b57cec5SDimitry Andricdef A9WriteFMulD : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 6; } 19670b57cec5SDimitry Andricdef A9WriteFMAS : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 8; } 19680b57cec5SDimitry Andric 19690b57cec5SDimitry Andricdef A9WriteFMAD : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 9; } 19700b57cec5SDimitry Andricdef A9WriteFDivS : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 15; } 19710b57cec5SDimitry Andricdef A9WriteFDivD : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 25; } 19720b57cec5SDimitry Andricdef A9WriteFSqrtS : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 17; } 19730b57cec5SDimitry Andricdef A9WriteFSqrtD : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 32; } 19740b57cec5SDimitry Andric 19750b57cec5SDimitry Andric// NEON has an odd mix of latencies. Simply name the write types by latency. 19760b57cec5SDimitry Andricdef A9WriteV1 : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 1; } 19770b57cec5SDimitry Andricdef A9WriteV2 : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 2; } 19780b57cec5SDimitry Andricdef A9WriteV3 : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 3; } 19790b57cec5SDimitry Andricdef A9WriteV4 : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 4; } 19800b57cec5SDimitry Andricdef A9WriteV5 : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 5; } 19810b57cec5SDimitry Andricdef A9WriteV6 : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 6; } 19820b57cec5SDimitry Andricdef A9WriteV7 : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 7; } 19830b57cec5SDimitry Andricdef A9WriteV9 : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 9; } 19840b57cec5SDimitry Andricdef A9WriteV10 : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { let Latency = 10; } 19850b57cec5SDimitry Andric 19860b57cec5SDimitry Andricdef : WriteRes<WriteVLD1, []>; 19870b57cec5SDimitry Andricdef : WriteRes<WriteVLD2, []>; 19880b57cec5SDimitry Andricdef : WriteRes<WriteVLD3, []>; 19890b57cec5SDimitry Andricdef : WriteRes<WriteVLD4, []>; 19900b57cec5SDimitry Andricdef : WriteRes<WriteVST1, []>; 19910b57cec5SDimitry Andricdef : WriteRes<WriteVST2, []>; 19920b57cec5SDimitry Andricdef : WriteRes<WriteVST3, []>; 19930b57cec5SDimitry Andricdef : WriteRes<WriteVST4, []>; 19940b57cec5SDimitry Andric 19950b57cec5SDimitry Andric// Reserve A9UnitFP for 2 consecutive cycles. 19960b57cec5SDimitry Andricdef A9Write2V4 : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { 19970b57cec5SDimitry Andric let Latency = 4; 1998*5f757f3fSDimitry Andric let ReleaseAtCycles = [2, 1]; 19990b57cec5SDimitry Andric} 20000b57cec5SDimitry Andricdef A9Write2V7 : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { 20010b57cec5SDimitry Andric let Latency = 7; 2002*5f757f3fSDimitry Andric let ReleaseAtCycles = [2, 1]; 20030b57cec5SDimitry Andric} 20040b57cec5SDimitry Andricdef A9Write2V9 : SchedWriteRes<[A9UnitFP, A9UnitAGU]> { 20050b57cec5SDimitry Andric let Latency = 9; 2006*5f757f3fSDimitry Andric let ReleaseAtCycles = [2, 1]; 20070b57cec5SDimitry Andric} 20080b57cec5SDimitry Andric 20090b57cec5SDimitry Andric// Branches don't have a def operand but still consume resources. 20100b57cec5SDimitry Andricdef A9WriteB : SchedWriteRes<[A9UnitB]>; 20110b57cec5SDimitry Andric 20120b57cec5SDimitry Andric// Address generation. 20130b57cec5SDimitry Andricdef A9WriteAdr : SchedWriteRes<[A9UnitAGU]> { let NumMicroOps = 0; } 20140b57cec5SDimitry Andric 20150b57cec5SDimitry Andric// Load Integer. 20160b57cec5SDimitry Andricdef A9WriteL : SchedWriteRes<[A9UnitLS]> { let Latency = 3; } 20170b57cec5SDimitry Andricdef : SchedAlias<WriteLd, A9WriteL>; 20180b57cec5SDimitry Andric// Load the upper 32-bits using the same micro-op. 20190b57cec5SDimitry Andricdef A9WriteLHi : SchedWriteRes<[]> { let Latency = 3; 20200b57cec5SDimitry Andric let NumMicroOps = 0; } 20210b57cec5SDimitry Andric// Offset shifted by register. 20220b57cec5SDimitry Andricdef A9WriteLsi : SchedWriteRes<[A9UnitLS]> { let Latency = 4; } 20230b57cec5SDimitry Andric// Load (and zero extend) a byte. 20240b57cec5SDimitry Andricdef A9WriteLb : SchedWriteRes<[A9UnitLS]> { let Latency = 4; } 20250b57cec5SDimitry Andricdef A9WriteLbsi : SchedWriteRes<[A9UnitLS]> { let Latency = 5; } 20260b57cec5SDimitry Andric 20270b57cec5SDimitry Andric// Load or Store Float, aligned. 20280b57cec5SDimitry Andricdef A9WriteLSfp : SchedWriteRes<[A9UnitLS, A9UnitFP]> { let Latency = 1; } 20290b57cec5SDimitry Andric 20300b57cec5SDimitry Andric// Store Integer. 20310b57cec5SDimitry Andricdef A9WriteS : SchedWriteRes<[A9UnitLS]>; 20320b57cec5SDimitry Andric 20330b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 20340b57cec5SDimitry Andric// Define resources dynamically for load multiple variants. 20350b57cec5SDimitry Andric 20360b57cec5SDimitry Andric// Define helpers for extra latency without consuming resources. 20370b57cec5SDimitry Andricdef A9WriteCycle1 : SchedWriteRes<[]> { let Latency = 1; let NumMicroOps = 0; } 20380b57cec5SDimitry Andricforeach NumCycles = 2-8 in { 20390b57cec5SDimitry Andricdef A9WriteCycle#NumCycles : WriteSequence<[A9WriteCycle1], NumCycles>; 20400b57cec5SDimitry Andric} // foreach NumCycles 20410b57cec5SDimitry Andric 20420b57cec5SDimitry Andric// Define address generation sequences and predicates for 8 flavors of LDMs. 20430b57cec5SDimitry Andricforeach NumAddr = 1-8 in { 20440b57cec5SDimitry Andric 20450b57cec5SDimitry Andric// Define A9WriteAdr1-8 as a sequence of A9WriteAdr with additive 20460b57cec5SDimitry Andric// latency for instructions that generate multiple loads or stores. 20470b57cec5SDimitry Andricdef A9WriteAdr#NumAddr : WriteSequence<[A9WriteAdr], NumAddr>; 20480b57cec5SDimitry Andric 20490b57cec5SDimitry Andric// Define a predicate to select the LDM based on number of memory addresses. 20500b57cec5SDimitry Andricdef A9LMAdr#NumAddr#Pred : 20510b57cec5SDimitry Andric SchedPredicate<"(TII->getNumLDMAddresses(*MI)+1)/2 == "#NumAddr>; 20520b57cec5SDimitry Andric 20530b57cec5SDimitry Andric} // foreach NumAddr 20540b57cec5SDimitry Andric 20550b57cec5SDimitry Andric// Fall-back for unknown LDMs. 20560b57cec5SDimitry Andricdef A9LMUnknownPred : SchedPredicate<"TII->getNumLDMAddresses(*MI) == 0">; 20570b57cec5SDimitry Andric 20580b57cec5SDimitry Andric// LDM/VLDM/VLDn address generation latency & resources. 20590b57cec5SDimitry Andric// Dynamically select the A9WriteAdrN sequence using a predicate. 20600b57cec5SDimitry Andricdef A9WriteLMAdr : SchedWriteVariant<[ 20610b57cec5SDimitry Andric SchedVar<A9LMAdr1Pred, [A9WriteAdr1]>, 20620b57cec5SDimitry Andric SchedVar<A9LMAdr2Pred, [A9WriteAdr2]>, 20630b57cec5SDimitry Andric SchedVar<A9LMAdr3Pred, [A9WriteAdr3]>, 20640b57cec5SDimitry Andric SchedVar<A9LMAdr4Pred, [A9WriteAdr4]>, 20650b57cec5SDimitry Andric SchedVar<A9LMAdr5Pred, [A9WriteAdr5]>, 20660b57cec5SDimitry Andric SchedVar<A9LMAdr6Pred, [A9WriteAdr6]>, 20670b57cec5SDimitry Andric SchedVar<A9LMAdr7Pred, [A9WriteAdr7]>, 20680b57cec5SDimitry Andric SchedVar<A9LMAdr8Pred, [A9WriteAdr8]>, 20690b57cec5SDimitry Andric // For unknown LDM/VLDM/VSTM, assume 2 32-bit registers. 20700b57cec5SDimitry Andric SchedVar<A9LMUnknownPred, [A9WriteAdr2]>]>; 20710b57cec5SDimitry Andric 20720b57cec5SDimitry Andric// Define LDM Resources. 20730b57cec5SDimitry Andric// These take no issue resource, so they can be combined with other 20740b57cec5SDimitry Andric// writes like WriteB. 20750b57cec5SDimitry Andric// A9WriteLMLo takes a single LS resource and 2 cycles. 20760b57cec5SDimitry Andricdef A9WriteLMLo : SchedWriteRes<[A9UnitLS]> { let Latency = 2; 20770b57cec5SDimitry Andric let NumMicroOps = 0; } 20780b57cec5SDimitry Andric// Assuming aligned access, the upper half of each pair is free with 20790b57cec5SDimitry Andric// the same latency. 20800b57cec5SDimitry Andricdef A9WriteLMHi : SchedWriteRes<[]> { let Latency = 2; 20810b57cec5SDimitry Andric let NumMicroOps = 0; } 20820b57cec5SDimitry Andric// Each A9WriteL#N variant adds N cycles of latency without consuming 20830b57cec5SDimitry Andric// additional resources. 20840b57cec5SDimitry Andricforeach NumAddr = 1-8 in { 20850b57cec5SDimitry Andricdef A9WriteL#NumAddr : WriteSequence< 20860b57cec5SDimitry Andric [A9WriteLMLo, !cast<SchedWrite>("A9WriteCycle"#NumAddr)]>; 20870b57cec5SDimitry Andricdef A9WriteL#NumAddr#Hi : WriteSequence< 20880b57cec5SDimitry Andric [A9WriteLMHi, !cast<SchedWrite>("A9WriteCycle"#NumAddr)]>; 20890b57cec5SDimitry Andric} 20900b57cec5SDimitry Andric 20910b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 20920b57cec5SDimitry Andric// LDM: Load multiple into 32-bit integer registers. 20930b57cec5SDimitry Andric 20940b57cec5SDimitry Andricdef A9WriteLMOpsList : A9WriteLMOpsListType< 20950b57cec5SDimitry Andric [A9WriteL1, A9WriteL1Hi, 20960b57cec5SDimitry Andric A9WriteL2, A9WriteL2Hi, 20970b57cec5SDimitry Andric A9WriteL3, A9WriteL3Hi, 20980b57cec5SDimitry Andric A9WriteL4, A9WriteL4Hi, 20990b57cec5SDimitry Andric A9WriteL5, A9WriteL5Hi, 21000b57cec5SDimitry Andric A9WriteL6, A9WriteL6Hi, 21010b57cec5SDimitry Andric A9WriteL7, A9WriteL7Hi, 21020b57cec5SDimitry Andric A9WriteL8, A9WriteL8Hi]>; 21030b57cec5SDimitry Andric 21040b57cec5SDimitry Andric// A9WriteLM variants expand into a pair of writes for each 64-bit 21050b57cec5SDimitry Andric// value loaded. When the number of registers is odd, the last 21060b57cec5SDimitry Andric// A9WriteLnHi is naturally ignored because the instruction has no 21070b57cec5SDimitry Andric// following def operands. These variants take no issue resource, so 21080b57cec5SDimitry Andric// they may need to be part of a WriteSequence that includes A9WriteIssue. 21090b57cec5SDimitry Andricdef A9WriteLM : SchedWriteVariant<[ 21100b57cec5SDimitry Andric SchedVar<A9LMAdr1Pred, A9WriteLMOpsList.Writes[0-1]>, 21110b57cec5SDimitry Andric SchedVar<A9LMAdr2Pred, A9WriteLMOpsList.Writes[0-3]>, 21120b57cec5SDimitry Andric SchedVar<A9LMAdr3Pred, A9WriteLMOpsList.Writes[0-5]>, 21130b57cec5SDimitry Andric SchedVar<A9LMAdr4Pred, A9WriteLMOpsList.Writes[0-7]>, 21140b57cec5SDimitry Andric SchedVar<A9LMAdr5Pred, A9WriteLMOpsList.Writes[0-9]>, 21150b57cec5SDimitry Andric SchedVar<A9LMAdr6Pred, A9WriteLMOpsList.Writes[0-11]>, 21160b57cec5SDimitry Andric SchedVar<A9LMAdr7Pred, A9WriteLMOpsList.Writes[0-13]>, 21170b57cec5SDimitry Andric SchedVar<A9LMAdr8Pred, A9WriteLMOpsList.Writes[0-15]>, 21180b57cec5SDimitry Andric // For unknown LDMs, define the maximum number of writes, but only 21190b57cec5SDimitry Andric // make the first two consume resources. 21200b57cec5SDimitry Andric SchedVar<A9LMUnknownPred, [A9WriteL1, A9WriteL1Hi, 21210b57cec5SDimitry Andric A9WriteL2, A9WriteL2Hi, 21220b57cec5SDimitry Andric A9WriteL3Hi, A9WriteL3Hi, 21230b57cec5SDimitry Andric A9WriteL4Hi, A9WriteL4Hi, 21240b57cec5SDimitry Andric A9WriteL5Hi, A9WriteL5Hi, 21250b57cec5SDimitry Andric A9WriteL6Hi, A9WriteL6Hi, 21260b57cec5SDimitry Andric A9WriteL7Hi, A9WriteL7Hi, 21270b57cec5SDimitry Andric A9WriteL8Hi, A9WriteL8Hi]>]> { 21280b57cec5SDimitry Andric let Variadic = 1; 21290b57cec5SDimitry Andric} 21300b57cec5SDimitry Andric 21310b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 21320b57cec5SDimitry Andric// VFP Load/Store Multiple Variants, and NEON VLDn/VSTn support. 21330b57cec5SDimitry Andric 21340b57cec5SDimitry Andric// A9WriteLfpOp is the same as A9WriteLSfp but takes no issue resources 21350b57cec5SDimitry Andric// so can be used in WriteSequences for in single-issue instructions that 21360b57cec5SDimitry Andric// encapsulate multiple loads. 21370b57cec5SDimitry Andricdef A9WriteLfpOp : SchedWriteRes<[A9UnitLS, A9UnitFP]> { 21380b57cec5SDimitry Andric let Latency = 1; 21390b57cec5SDimitry Andric let NumMicroOps = 0; 21400b57cec5SDimitry Andric} 21410b57cec5SDimitry Andric 21420b57cec5SDimitry Andricforeach NumAddr = 1-8 in { 21430b57cec5SDimitry Andric 21440b57cec5SDimitry Andric// Helper for A9WriteLfp1-8: A sequence of fp loads with no micro-ops. 21450b57cec5SDimitry Andricdef A9WriteLfp#NumAddr#Seq : WriteSequence<[A9WriteLfpOp], NumAddr>; 21460b57cec5SDimitry Andric 21470b57cec5SDimitry Andric// A9WriteLfp1-8 definitions are statically expanded into a sequence of 21480b57cec5SDimitry Andric// A9WriteLfpOps with additive latency that takes a single issue slot. 21490b57cec5SDimitry Andric// Used directly to describe NEON VLDn. 21500b57cec5SDimitry Andricdef A9WriteLfp#NumAddr : WriteSequence< 21510b57cec5SDimitry Andric [A9WriteIssue, !cast<SchedWrite>("A9WriteLfp"#NumAddr#Seq)]>; 21520b57cec5SDimitry Andric 21530b57cec5SDimitry Andric// A9WriteLfp1-8Mov adds a cycle of latency and FP resource for 21540b57cec5SDimitry Andric// permuting loaded values. 21550b57cec5SDimitry Andricdef A9WriteLfp#NumAddr#Mov : WriteSequence< 21560b57cec5SDimitry Andric [A9WriteF, !cast<SchedWrite>("A9WriteLfp"#NumAddr#Seq)]>; 21570b57cec5SDimitry Andric 21580b57cec5SDimitry Andric} // foreach NumAddr 21590b57cec5SDimitry Andric 21600b57cec5SDimitry Andric// Define VLDM/VSTM PreRA resources. 21610b57cec5SDimitry Andric// A9WriteLMfpPreRA are dynamically expanded into the correct 21620b57cec5SDimitry Andric// A9WriteLfp1-8 sequence based on a predicate. This supports the 21630b57cec5SDimitry Andric// preRA VLDM variants in which all 64-bit loads are written to the 21640b57cec5SDimitry Andric// same tuple of either single or double precision registers. 21650b57cec5SDimitry Andricdef A9WriteLMfpPreRA : SchedWriteVariant<[ 21660b57cec5SDimitry Andric SchedVar<A9LMAdr1Pred, [A9WriteLfp1]>, 21670b57cec5SDimitry Andric SchedVar<A9LMAdr2Pred, [A9WriteLfp2]>, 21680b57cec5SDimitry Andric SchedVar<A9LMAdr3Pred, [A9WriteLfp3]>, 21690b57cec5SDimitry Andric SchedVar<A9LMAdr4Pred, [A9WriteLfp4]>, 21700b57cec5SDimitry Andric SchedVar<A9LMAdr5Pred, [A9WriteLfp5]>, 21710b57cec5SDimitry Andric SchedVar<A9LMAdr6Pred, [A9WriteLfp6]>, 21720b57cec5SDimitry Andric SchedVar<A9LMAdr7Pred, [A9WriteLfp7]>, 21730b57cec5SDimitry Andric SchedVar<A9LMAdr8Pred, [A9WriteLfp8]>, 21740b57cec5SDimitry Andric // For unknown VLDM/VSTM PreRA, assume 2xS registers. 21750b57cec5SDimitry Andric SchedVar<A9LMUnknownPred, [A9WriteLfp2]>]>; 21760b57cec5SDimitry Andric 21770b57cec5SDimitry Andric// Define VLDM/VSTM PostRA Resources. 21780b57cec5SDimitry Andric// A9WriteLMfpLo takes a LS and FP resource and one issue slot but no latency. 21790b57cec5SDimitry Andricdef A9WriteLMfpLo : SchedWriteRes<[A9UnitLS, A9UnitFP]> { let Latency = 0; } 21800b57cec5SDimitry Andric 21810b57cec5SDimitry Andricforeach NumAddr = 1-8 in { 21820b57cec5SDimitry Andric 21830b57cec5SDimitry Andric// Each A9WriteL#N variant adds N cycles of latency without consuming 21840b57cec5SDimitry Andric// additional resources. 21850b57cec5SDimitry Andricdef A9WriteLMfp#NumAddr : WriteSequence< 21860b57cec5SDimitry Andric [A9WriteLMfpLo, !cast<SchedWrite>("A9WriteCycle"#NumAddr)]>; 21870b57cec5SDimitry Andric 21880b57cec5SDimitry Andric// Assuming aligned access, the upper half of each pair is free with 21890b57cec5SDimitry Andric// the same latency. 21900b57cec5SDimitry Andricdef A9WriteLMfp#NumAddr#Hi : WriteSequence< 21910b57cec5SDimitry Andric [A9WriteLMHi, !cast<SchedWrite>("A9WriteCycle"#NumAddr)]>; 21920b57cec5SDimitry Andric 21930b57cec5SDimitry Andric} // foreach NumAddr 21940b57cec5SDimitry Andric 21950b57cec5SDimitry Andric// VLDM PostRA Variants. These variants expand A9WriteLMfpPostRA into a 21960b57cec5SDimitry Andric// pair of writes for each 64-bit data loaded. When the number of 21970b57cec5SDimitry Andric// registers is odd, the last WriteLMfpnHi is naturally ignored because 21980b57cec5SDimitry Andric// the instruction has no following def operands. 21990b57cec5SDimitry Andric 22000b57cec5SDimitry Andricdef A9WriteLMfpPostRAOpsList : A9WriteLMOpsListType< 22010b57cec5SDimitry Andric [A9WriteLMfp1, A9WriteLMfp2, // 0-1 22020b57cec5SDimitry Andric A9WriteLMfp3, A9WriteLMfp4, // 2-3 22030b57cec5SDimitry Andric A9WriteLMfp5, A9WriteLMfp6, // 4-5 22040b57cec5SDimitry Andric A9WriteLMfp7, A9WriteLMfp8, // 6-7 22050b57cec5SDimitry Andric A9WriteLMfp1Hi, // 8-8 22060b57cec5SDimitry Andric A9WriteLMfp2Hi, A9WriteLMfp2Hi, // 9-10 22070b57cec5SDimitry Andric A9WriteLMfp3Hi, A9WriteLMfp3Hi, // 11-12 22080b57cec5SDimitry Andric A9WriteLMfp4Hi, A9WriteLMfp4Hi, // 13-14 22090b57cec5SDimitry Andric A9WriteLMfp5Hi, A9WriteLMfp5Hi, // 15-16 22100b57cec5SDimitry Andric A9WriteLMfp6Hi, A9WriteLMfp6Hi, // 17-18 22110b57cec5SDimitry Andric A9WriteLMfp7Hi, A9WriteLMfp7Hi, // 19-20 22120b57cec5SDimitry Andric A9WriteLMfp8Hi, A9WriteLMfp8Hi]>; // 21-22 22130b57cec5SDimitry Andric 22140b57cec5SDimitry Andricdef A9WriteLMfpPostRA : SchedWriteVariant<[ 22150b57cec5SDimitry Andric SchedVar<A9LMAdr1Pred, A9WriteLMfpPostRAOpsList.Writes[0-0, 8-8]>, 22160b57cec5SDimitry Andric SchedVar<A9LMAdr2Pred, A9WriteLMfpPostRAOpsList.Writes[0-1, 9-10]>, 22170b57cec5SDimitry Andric SchedVar<A9LMAdr3Pred, A9WriteLMfpPostRAOpsList.Writes[0-2, 10-12]>, 22180b57cec5SDimitry Andric SchedVar<A9LMAdr4Pred, A9WriteLMfpPostRAOpsList.Writes[0-3, 11-14]>, 22190b57cec5SDimitry Andric SchedVar<A9LMAdr5Pred, A9WriteLMfpPostRAOpsList.Writes[0-4, 12-16]>, 22200b57cec5SDimitry Andric SchedVar<A9LMAdr6Pred, A9WriteLMfpPostRAOpsList.Writes[0-5, 13-18]>, 22210b57cec5SDimitry Andric SchedVar<A9LMAdr7Pred, A9WriteLMfpPostRAOpsList.Writes[0-6, 14-20]>, 22220b57cec5SDimitry Andric SchedVar<A9LMAdr8Pred, A9WriteLMfpPostRAOpsList.Writes[0-7, 15-22]>, 22230b57cec5SDimitry Andric // For unknown LDMs, define the maximum number of writes, but only 22240b57cec5SDimitry Andric // make the first two consume resources. We are optimizing for the case 22250b57cec5SDimitry Andric // where the operands are DPRs, and this determines the first eight 22260b57cec5SDimitry Andric // types. The remaining eight types are filled to cover the case 22270b57cec5SDimitry Andric // where the operands are SPRs. 22280b57cec5SDimitry Andric SchedVar<A9LMUnknownPred, [A9WriteLMfp1, A9WriteLMfp2, 22290b57cec5SDimitry Andric A9WriteLMfp3Hi, A9WriteLMfp4Hi, 22300b57cec5SDimitry Andric A9WriteLMfp5Hi, A9WriteLMfp6Hi, 22310b57cec5SDimitry Andric A9WriteLMfp7Hi, A9WriteLMfp8Hi, 22320b57cec5SDimitry Andric A9WriteLMfp5Hi, A9WriteLMfp5Hi, 22330b57cec5SDimitry Andric A9WriteLMfp6Hi, A9WriteLMfp6Hi, 22340b57cec5SDimitry Andric A9WriteLMfp7Hi, A9WriteLMfp7Hi, 22350b57cec5SDimitry Andric A9WriteLMfp8Hi, A9WriteLMfp8Hi]>]> { 22360b57cec5SDimitry Andric let Variadic = 1; 22370b57cec5SDimitry Andric} 22380b57cec5SDimitry Andric 22390b57cec5SDimitry Andric// Distinguish between our multiple MI-level forms of the same 22400b57cec5SDimitry Andric// VLDM/VSTM instructions. 22410b57cec5SDimitry Andricdef A9PreRA : SchedPredicate< 2242bdd1243dSDimitry Andric "MI->getOperand(0).getReg().isVirtual()">; 22430b57cec5SDimitry Andricdef A9PostRA : SchedPredicate< 2244bdd1243dSDimitry Andric "MI->getOperand(0).getReg().isPhysical()">; 22450b57cec5SDimitry Andric 22460b57cec5SDimitry Andric// VLDM represents all destination registers as a single register 22470b57cec5SDimitry Andric// tuple, unlike LDM. So the number of write operands is not variadic. 22480b57cec5SDimitry Andricdef A9WriteLMfp : SchedWriteVariant<[ 22490b57cec5SDimitry Andric SchedVar<A9PreRA, [A9WriteLMfpPreRA]>, 22500b57cec5SDimitry Andric SchedVar<A9PostRA, [A9WriteLMfpPostRA]>]>; 22510b57cec5SDimitry Andric 22520b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 22530b57cec5SDimitry Andric// Resources for other (non-LDM/VLDM) Variants. 22540b57cec5SDimitry Andric 22550b57cec5SDimitry Andric// These mov immediate writers are unconditionally expanded with 22560b57cec5SDimitry Andric// additive latency. 22570b57cec5SDimitry Andricdef A9WriteI2 : WriteSequence<[A9WriteI, A9WriteI]>; 22580b57cec5SDimitry Andricdef A9WriteI2pc : WriteSequence<[A9WriteI, A9WriteI, WriteALU]>; 22590b57cec5SDimitry Andricdef A9WriteI2ld : WriteSequence<[A9WriteI, A9WriteI, A9WriteL]>; 22600b57cec5SDimitry Andric 22610b57cec5SDimitry Andric// Some ALU operations can read loaded integer values one cycle early. 22620b57cec5SDimitry Andricdef A9ReadALU : SchedReadAdvance<1, 22630b57cec5SDimitry Andric [A9WriteL, A9WriteLHi, A9WriteLsi, A9WriteLb, A9WriteLbsi, 22640b57cec5SDimitry Andric A9WriteL1, A9WriteL2, A9WriteL3, A9WriteL4, 22650b57cec5SDimitry Andric A9WriteL5, A9WriteL6, A9WriteL7, A9WriteL8, 22660b57cec5SDimitry Andric A9WriteL1Hi, A9WriteL2Hi, A9WriteL3Hi, A9WriteL4Hi, 22670b57cec5SDimitry Andric A9WriteL5Hi, A9WriteL6Hi, A9WriteL7Hi, A9WriteL8Hi]>; 22680b57cec5SDimitry Andric 22690b57cec5SDimitry Andric// Read types for operands that are unconditionally read in cycle N 22700b57cec5SDimitry Andric// after the instruction issues, decreases producer latency by N-1. 22710b57cec5SDimitry Andricdef A9Read2 : SchedReadAdvance<1>; 22720b57cec5SDimitry Andricdef A9Read3 : SchedReadAdvance<2>; 22730b57cec5SDimitry Andricdef A9Read4 : SchedReadAdvance<3>; 22740b57cec5SDimitry Andric 22750b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 22760b57cec5SDimitry Andric// Map itinerary classes to scheduler read/write resources per operand. 22770b57cec5SDimitry Andric// 22780b57cec5SDimitry Andric// For ARM, we piggyback scheduler resources on the Itinerary classes 22790b57cec5SDimitry Andric// to avoid perturbing the existing instruction definitions. 22800b57cec5SDimitry Andric 22810b57cec5SDimitry Andric// This table follows the ARM Cortex-A9 Technical Reference Manuals, 22820b57cec5SDimitry Andric// mostly in order. 22830b57cec5SDimitry Andric 22840b57cec5SDimitry Andricdef :ItinRW<[WriteALU], [IIC_iMOVi,IIC_iMOVr,IIC_iMOVsi, 22850b57cec5SDimitry Andric IIC_iMVNi,IIC_iMVNsi, 22860b57cec5SDimitry Andric IIC_iCMOVi,IIC_iCMOVr,IIC_iCMOVsi]>; 22870b57cec5SDimitry Andricdef :ItinRW<[WriteALU, A9ReadALU],[IIC_iMVNr]>; 22880b57cec5SDimitry Andricdef :ItinRW<[A9WriteIsr], [IIC_iMOVsr,IIC_iMVNsr,IIC_iCMOVsr]>; 22890b57cec5SDimitry Andric 22900b57cec5SDimitry Andricdef :ItinRW<[A9WriteI2], [IIC_iMOVix2,IIC_iCMOVix2]>; 22910b57cec5SDimitry Andricdef :ItinRW<[A9WriteI2pc], [IIC_iMOVix2addpc]>; 22920b57cec5SDimitry Andricdef :ItinRW<[A9WriteI2ld], [IIC_iMOVix2ld]>; 22930b57cec5SDimitry Andric 22940b57cec5SDimitry Andricdef :ItinRW<[WriteALU], [IIC_iBITi,IIC_iBITr,IIC_iUNAr,IIC_iTSTi,IIC_iTSTr]>; 22950b57cec5SDimitry Andricdef :ItinRW<[WriteALU, A9ReadALU], [IIC_iALUi, IIC_iCMPi, IIC_iCMPsi]>; 22960b57cec5SDimitry Andricdef :ItinRW<[WriteALU, A9ReadALU, A9ReadALU],[IIC_iALUr,IIC_iCMPr]>; 22970b57cec5SDimitry Andricdef :ItinRW<[WriteALUsi], [IIC_iBITsi,IIC_iUNAsi,IIC_iEXTr,IIC_iTSTsi]>; 22980b57cec5SDimitry Andricdef :ItinRW<[WriteALUsi, A9ReadALU], [IIC_iALUsi]>; 22990b57cec5SDimitry Andricdef :ItinRW<[WriteALUsi, ReadDefault, A9ReadALU], [IIC_iALUsir]>; // RSB 23000b57cec5SDimitry Andricdef :ItinRW<[A9WriteALUsr], [IIC_iBITsr,IIC_iTSTsr,IIC_iEXTAr,IIC_iEXTAsr]>; 23010b57cec5SDimitry Andricdef :ItinRW<[A9WriteALUsr, A9ReadALU], [IIC_iALUsr,IIC_iCMPsr]>; 23020b57cec5SDimitry Andric 23030b57cec5SDimitry Andric// A9WriteHi ignored for MUL32. 23040b57cec5SDimitry Andricdef :ItinRW<[A9WriteM, A9WriteMHi], [IIC_iMUL32,IIC_iMAC32, 23050b57cec5SDimitry Andric IIC_iMUL64,IIC_iMAC64]>; 23060b57cec5SDimitry Andric// FIXME: SMLALxx needs itin classes 23070b57cec5SDimitry Andricdef :ItinRW<[A9WriteM16, A9WriteM16Hi], [IIC_iMUL16,IIC_iMAC16]>; 23080b57cec5SDimitry Andric 23090b57cec5SDimitry Andric// TODO: For floating-point ops, we model the pipeline forwarding 23100b57cec5SDimitry Andric// latencies here. WAW latencies are sometimes longer. 23110b57cec5SDimitry Andric 23120b57cec5SDimitry Andricdef :ItinRW<[A9WriteFMov], [IIC_fpSTAT, IIC_fpMOVIS, IIC_fpMOVID, IIC_fpMOVSI, 23130b57cec5SDimitry Andric IIC_fpUNA32, IIC_fpUNA64, 23140b57cec5SDimitry Andric IIC_fpCMP32, IIC_fpCMP64]>; 23150b57cec5SDimitry Andricdef :ItinRW<[A9WriteFMov, A9WriteFMov], [IIC_fpMOVDI]>; 23160b57cec5SDimitry Andricdef :ItinRW<[A9WriteF], [IIC_fpCVTSD, IIC_fpCVTDS, IIC_fpCVTSH, IIC_fpCVTHS, 23170b57cec5SDimitry Andric IIC_fpCVTIS, IIC_fpCVTID, IIC_fpCVTSI, IIC_fpCVTDI, 23180b57cec5SDimitry Andric IIC_fpALU32, IIC_fpALU64]>; 23190b57cec5SDimitry Andricdef :ItinRW<[A9WriteFMulS], [IIC_fpMUL32]>; 23200b57cec5SDimitry Andricdef :ItinRW<[A9WriteFMulD], [IIC_fpMUL64]>; 23210b57cec5SDimitry Andricdef :ItinRW<[A9WriteFMAS], [IIC_fpMAC32]>; 23220b57cec5SDimitry Andricdef :ItinRW<[A9WriteFMAD], [IIC_fpMAC64]>; 23230b57cec5SDimitry Andricdef :ItinRW<[A9WriteFDivS], [IIC_fpDIV32]>; 23240b57cec5SDimitry Andricdef :ItinRW<[A9WriteFDivD], [IIC_fpDIV64]>; 23250b57cec5SDimitry Andricdef :ItinRW<[A9WriteFSqrtS], [IIC_fpSQRT32]>; 23260b57cec5SDimitry Andricdef :ItinRW<[A9WriteFSqrtD], [IIC_fpSQRT64]>; 23270b57cec5SDimitry Andric 23280b57cec5SDimitry Andricdef :ItinRW<[A9WriteB], [IIC_Br]>; 23290b57cec5SDimitry Andric 23300b57cec5SDimitry Andric// A9 PLD is processed in a dedicated unit. 23310b57cec5SDimitry Andricdef :ItinRW<[], [IIC_Preload]>; 23320b57cec5SDimitry Andric 23330b57cec5SDimitry Andric// Note: We must assume that loads are aligned, since the machine 23340b57cec5SDimitry Andric// model cannot know this statically and A9 ignores alignment hints. 23350b57cec5SDimitry Andric 23360b57cec5SDimitry Andric// A9WriteAdr consumes AGU regardless address writeback. But it's 23370b57cec5SDimitry Andric// latency is only relevant for users of an updated address. 23380b57cec5SDimitry Andricdef :ItinRW<[A9WriteL, A9WriteAdr], [IIC_iLoad_i,IIC_iLoad_r, 23390b57cec5SDimitry Andric IIC_iLoad_iu,IIC_iLoad_ru]>; 23400b57cec5SDimitry Andricdef :ItinRW<[A9WriteLsi, A9WriteAdr], [IIC_iLoad_si,IIC_iLoad_siu]>; 23410b57cec5SDimitry Andricdef :ItinRW<[A9WriteLb, A9WriteAdr2], [IIC_iLoad_bh_i,IIC_iLoad_bh_r, 23420b57cec5SDimitry Andric IIC_iLoad_bh_iu,IIC_iLoad_bh_ru]>; 23430b57cec5SDimitry Andricdef :ItinRW<[A9WriteLbsi, A9WriteAdr2], [IIC_iLoad_bh_si,IIC_iLoad_bh_siu]>; 23440b57cec5SDimitry Andricdef :ItinRW<[A9WriteL, A9WriteLHi, A9WriteAdr], [IIC_iLoad_d_i,IIC_iLoad_d_r, 23450b57cec5SDimitry Andric IIC_iLoad_d_ru]>; 23460b57cec5SDimitry Andric// Store either has no def operands, or the one def for address writeback. 23470b57cec5SDimitry Andricdef :ItinRW<[A9WriteAdr, A9WriteS], [IIC_iStore_i, IIC_iStore_r, 23480b57cec5SDimitry Andric IIC_iStore_iu, IIC_iStore_ru, 23490b57cec5SDimitry Andric IIC_iStore_d_i, IIC_iStore_d_r, 23500b57cec5SDimitry Andric IIC_iStore_d_ru]>; 23510b57cec5SDimitry Andricdef :ItinRW<[A9WriteAdr2, A9WriteS], [IIC_iStore_si, IIC_iStore_siu, 23520b57cec5SDimitry Andric IIC_iStore_bh_i, IIC_iStore_bh_r, 23530b57cec5SDimitry Andric IIC_iStore_bh_iu, IIC_iStore_bh_ru]>; 23540b57cec5SDimitry Andricdef :ItinRW<[A9WriteAdr3, A9WriteS], [IIC_iStore_bh_si, IIC_iStore_bh_siu]>; 23550b57cec5SDimitry Andric 23560b57cec5SDimitry Andric// A9WriteML will be expanded into a separate write for each def 23570b57cec5SDimitry Andric// operand. Address generation consumes resources, but A9WriteLMAdr 23580b57cec5SDimitry Andric// is listed after all def operands, so has no effective latency. 23590b57cec5SDimitry Andric// 23600b57cec5SDimitry Andric// Note: A9WriteLM expands into an even number of def operands. The 23610b57cec5SDimitry Andric// actual number of def operands may be less by one. 23620b57cec5SDimitry Andricdef :ItinRW<[A9WriteLM, A9WriteLMAdr, A9WriteIssue], [IIC_iLoad_m, IIC_iPop]>; 23630b57cec5SDimitry Andric 23640b57cec5SDimitry Andric// Load multiple with address writeback has an extra def operand in 23650b57cec5SDimitry Andric// front of the loaded registers. 23660b57cec5SDimitry Andric// 23670b57cec5SDimitry Andric// Reuse the load-multiple variants for store-multiple because the 23680b57cec5SDimitry Andric// resources are identical, For stores only the address writeback 23690b57cec5SDimitry Andric// has a def operand so the WriteL latencies are unused. 23700b57cec5SDimitry Andricdef :ItinRW<[A9WriteLMAdr, A9WriteLM, A9WriteIssue], [IIC_iLoad_mu, 23710b57cec5SDimitry Andric IIC_iStore_m, 23720b57cec5SDimitry Andric IIC_iStore_mu]>; 23730b57cec5SDimitry Andricdef :ItinRW<[A9WriteLM, A9WriteLMAdr, A9WriteB], [IIC_iLoad_mBr, IIC_iPop_Br]>; 23740b57cec5SDimitry Andricdef :ItinRW<[A9WriteL, A9WriteAdr, WriteALU], [IIC_iLoadiALU]>; 23750b57cec5SDimitry Andric 23760b57cec5SDimitry Andricdef :ItinRW<[A9WriteLSfp, A9WriteAdr], [IIC_fpLoad32, IIC_fpLoad64]>; 23770b57cec5SDimitry Andric 23780b57cec5SDimitry Andricdef :ItinRW<[A9WriteLMfp, A9WriteLMAdr], [IIC_fpLoad_m]>; 23790b57cec5SDimitry Andricdef :ItinRW<[A9WriteLMAdr, A9WriteLMfp], [IIC_fpLoad_mu]>; 23800b57cec5SDimitry Andricdef :ItinRW<[A9WriteAdr, A9WriteLSfp], [IIC_fpStore32, IIC_fpStore64, 23810b57cec5SDimitry Andric IIC_fpStore_m, IIC_fpStore_mu]>; 23820b57cec5SDimitry Andric 23830b57cec5SDimitry Andric// Note: Unlike VLDM, VLD1 expects the writeback operand after the 23840b57cec5SDimitry Andric// normal writes. 23850b57cec5SDimitry Andricdef :ItinRW<[A9WriteLfp1, A9WriteAdr1], [IIC_VLD1, IIC_VLD1u, 23860b57cec5SDimitry Andric IIC_VLD1x2, IIC_VLD1x2u]>; 23870b57cec5SDimitry Andricdef :ItinRW<[A9WriteLfp2, A9WriteAdr2], [IIC_VLD1x3, IIC_VLD1x3u, 23880b57cec5SDimitry Andric IIC_VLD1x4, IIC_VLD1x4u, 23890b57cec5SDimitry Andric IIC_VLD4dup, IIC_VLD4dupu]>; 23900b57cec5SDimitry Andricdef :ItinRW<[A9WriteLfp1Mov, A9WriteAdr1], [IIC_VLD1dup, IIC_VLD1dupu, 23910b57cec5SDimitry Andric IIC_VLD2, IIC_VLD2u, 23920b57cec5SDimitry Andric IIC_VLD2dup, IIC_VLD2dupu]>; 23930b57cec5SDimitry Andricdef :ItinRW<[A9WriteLfp2Mov, A9WriteAdr1], [IIC_VLD1ln, IIC_VLD1lnu, 23940b57cec5SDimitry Andric IIC_VLD2x2, IIC_VLD2x2u, 23950b57cec5SDimitry Andric IIC_VLD2ln, IIC_VLD2lnu]>; 23960b57cec5SDimitry Andricdef :ItinRW<[A9WriteLfp3Mov, A9WriteAdr3], [IIC_VLD3, IIC_VLD3u, 23970b57cec5SDimitry Andric IIC_VLD3dup, IIC_VLD3dupu]>; 23980b57cec5SDimitry Andricdef :ItinRW<[A9WriteLfp4Mov, A9WriteAdr4], [IIC_VLD4, IIC_VLD4u, 23990b57cec5SDimitry Andric IIC_VLD4ln, IIC_VLD4lnu]>; 24000b57cec5SDimitry Andricdef :ItinRW<[A9WriteLfp5Mov, A9WriteAdr5], [IIC_VLD3ln, IIC_VLD3lnu]>; 24010b57cec5SDimitry Andric 24020b57cec5SDimitry Andric// Vector stores use similar resources to vector loads, so use the 24030b57cec5SDimitry Andric// same write types. The address write must be first for stores with 24040b57cec5SDimitry Andric// address writeback. 24050b57cec5SDimitry Andricdef :ItinRW<[A9WriteAdr1, A9WriteLfp1], [IIC_VST1, IIC_VST1u, 24060b57cec5SDimitry Andric IIC_VST1x2, IIC_VST1x2u, 24070b57cec5SDimitry Andric IIC_VST1ln, IIC_VST1lnu, 24080b57cec5SDimitry Andric IIC_VST2, IIC_VST2u, 24090b57cec5SDimitry Andric IIC_VST2x2, IIC_VST2x2u, 24100b57cec5SDimitry Andric IIC_VST2ln, IIC_VST2lnu]>; 24110b57cec5SDimitry Andricdef :ItinRW<[A9WriteAdr2, A9WriteLfp2], [IIC_VST1x3, IIC_VST1x3u, 24120b57cec5SDimitry Andric IIC_VST1x4, IIC_VST1x4u, 24130b57cec5SDimitry Andric IIC_VST3, IIC_VST3u, 24140b57cec5SDimitry Andric IIC_VST3ln, IIC_VST3lnu, 24150b57cec5SDimitry Andric IIC_VST4, IIC_VST4u, 24160b57cec5SDimitry Andric IIC_VST4ln, IIC_VST4lnu]>; 24170b57cec5SDimitry Andric 24180b57cec5SDimitry Andric// NEON moves. 24190b57cec5SDimitry Andricdef :ItinRW<[A9WriteV2], [IIC_VMOVSI, IIC_VMOVDI, IIC_VMOVD, IIC_VMOVQ]>; 24200b57cec5SDimitry Andricdef :ItinRW<[A9WriteV1], [IIC_VMOV, IIC_VMOVIS, IIC_VMOVID]>; 24210b57cec5SDimitry Andricdef :ItinRW<[A9WriteV3], [IIC_VMOVISL, IIC_VMOVN]>; 24220b57cec5SDimitry Andric 24230b57cec5SDimitry Andric// NEON integer arithmetic 24240b57cec5SDimitry Andric// 24250b57cec5SDimitry Andric// VADD/VAND/VORR/VEOR/VBIC/VORN/VBIT/VBIF/VBSL 24260b57cec5SDimitry Andricdef :ItinRW<[A9WriteV3, A9Read2, A9Read2], [IIC_VBINiD, IIC_VBINiQ]>; 24270b57cec5SDimitry Andric// VSUB/VMVN/VCLSD/VCLZD/VCNTD 24280b57cec5SDimitry Andricdef :ItinRW<[A9WriteV3, A9Read2], [IIC_VSUBiD, IIC_VSUBiQ, IIC_VCNTiD]>; 24290b57cec5SDimitry Andric// VADDL/VSUBL/VNEG are mapped later under IIC_SHLi. 24300b57cec5SDimitry Andric// ... 24310b57cec5SDimitry Andric// VHADD/VRHADD/VQADD/VTST/VADH/VRADH 24320b57cec5SDimitry Andricdef :ItinRW<[A9WriteV4, A9Read2, A9Read2], [IIC_VBINi4D, IIC_VBINi4Q]>; 24330b57cec5SDimitry Andric 24340b57cec5SDimitry Andric// VSBH/VRSBH/VHSUB/VQSUB/VABD/VCEQ/VCGE/VCGT/VMAX/VMIN/VPMAX/VPMIN/VABDL 24350b57cec5SDimitry Andricdef :ItinRW<[A9WriteV4, A9Read2], [IIC_VSUBi4D, IIC_VSUBi4Q]>; 24360b57cec5SDimitry Andric// VQNEG/VQABS 24370b57cec5SDimitry Andricdef :ItinRW<[A9WriteV4], [IIC_VQUNAiD, IIC_VQUNAiQ]>; 24380b57cec5SDimitry Andric// VABS 24390b57cec5SDimitry Andricdef :ItinRW<[A9WriteV4, A9Read2], [IIC_VUNAiD, IIC_VUNAiQ]>; 24400b57cec5SDimitry Andric// VPADD/VPADDL are mapped later under IIC_SHLi. 24410b57cec5SDimitry Andric// ... 24420b57cec5SDimitry Andric// VCLSQ/VCLZQ/VCNTQ, takes two cycles. 24430b57cec5SDimitry Andricdef :ItinRW<[A9Write2V4, A9Read3], [IIC_VCNTiQ]>; 24440b57cec5SDimitry Andric// VMOVimm/VMVNimm/VORRimm/VBICimm 24450b57cec5SDimitry Andricdef :ItinRW<[A9WriteV3], [IIC_VMOVImm]>; 24460b57cec5SDimitry Andricdef :ItinRW<[A9WriteV6, A9Read3, A9Read2], [IIC_VABAD, IIC_VABAQ]>; 24470b57cec5SDimitry Andricdef :ItinRW<[A9WriteV6, A9Read3], [IIC_VPALiD, IIC_VPALiQ]>; 24480b57cec5SDimitry Andric 24490b57cec5SDimitry Andric// NEON integer multiply 24500b57cec5SDimitry Andric// 24510b57cec5SDimitry Andric// Note: these don't quite match the timing docs, but they do match 24520b57cec5SDimitry Andric// the original A9 itinerary. 24530b57cec5SDimitry Andricdef :ItinRW<[A9WriteV6, A9Read2, A9Read2], [IIC_VMULi16D]>; 24540b57cec5SDimitry Andricdef :ItinRW<[A9WriteV7, A9Read2, A9Read2], [IIC_VMULi16Q]>; 24550b57cec5SDimitry Andricdef :ItinRW<[A9Write2V7, A9Read2], [IIC_VMULi32D]>; 24560b57cec5SDimitry Andricdef :ItinRW<[A9Write2V9, A9Read2], [IIC_VMULi32Q]>; 24570b57cec5SDimitry Andricdef :ItinRW<[A9WriteV6, A9Read3, A9Read2, A9Read2], [IIC_VMACi16D]>; 24580b57cec5SDimitry Andricdef :ItinRW<[A9WriteV7, A9Read3, A9Read2, A9Read2], [IIC_VMACi16Q]>; 24590b57cec5SDimitry Andricdef :ItinRW<[A9Write2V7, A9Read3, A9Read2], [IIC_VMACi32D]>; 24600b57cec5SDimitry Andricdef :ItinRW<[A9Write2V9, A9Read3, A9Read2], [IIC_VMACi32Q]>; 24610b57cec5SDimitry Andric 24620b57cec5SDimitry Andric// NEON integer shift 24630b57cec5SDimitry Andric// TODO: Q,Q,Q shifts should actually reserve FP for 2 cycles. 24640b57cec5SDimitry Andricdef :ItinRW<[A9WriteV3], [IIC_VSHLiD, IIC_VSHLiQ]>; 24650b57cec5SDimitry Andricdef :ItinRW<[A9WriteV4], [IIC_VSHLi4D, IIC_VSHLi4Q]>; 24660b57cec5SDimitry Andric 24670b57cec5SDimitry Andric// NEON permute 24680b57cec5SDimitry Andricdef :ItinRW<[A9WriteV2, A9WriteV2], [IIC_VPERMD, IIC_VPERMQ, IIC_VEXTD]>; 24690b57cec5SDimitry Andricdef :ItinRW<[A9WriteV3, A9WriteV4, ReadDefault, A9Read2], 24700b57cec5SDimitry Andric [IIC_VPERMQ3, IIC_VEXTQ]>; 24710b57cec5SDimitry Andricdef :ItinRW<[A9WriteV3, A9Read2], [IIC_VTB1]>; 24720b57cec5SDimitry Andricdef :ItinRW<[A9WriteV3, A9Read2, A9Read2], [IIC_VTB2]>; 24730b57cec5SDimitry Andricdef :ItinRW<[A9WriteV4, A9Read2, A9Read2, A9Read3], [IIC_VTB3]>; 24740b57cec5SDimitry Andricdef :ItinRW<[A9WriteV4, A9Read2, A9Read2, A9Read3, A9Read3], [IIC_VTB4]>; 24750b57cec5SDimitry Andricdef :ItinRW<[A9WriteV3, ReadDefault, A9Read2], [IIC_VTBX1]>; 24760b57cec5SDimitry Andricdef :ItinRW<[A9WriteV3, ReadDefault, A9Read2, A9Read2], [IIC_VTBX2]>; 24770b57cec5SDimitry Andricdef :ItinRW<[A9WriteV4, ReadDefault, A9Read2, A9Read2, A9Read3], [IIC_VTBX3]>; 24780b57cec5SDimitry Andricdef :ItinRW<[A9WriteV4, ReadDefault, A9Read2, A9Read2, A9Read3, A9Read3], 24790b57cec5SDimitry Andric [IIC_VTBX4]>; 24800b57cec5SDimitry Andric 24810b57cec5SDimitry Andric// NEON floating-point 24820b57cec5SDimitry Andricdef :ItinRW<[A9WriteV5, A9Read2, A9Read2], [IIC_VBIND]>; 24830b57cec5SDimitry Andricdef :ItinRW<[A9WriteV6, A9Read2, A9Read2], [IIC_VBINQ]>; 24840b57cec5SDimitry Andricdef :ItinRW<[A9WriteV5, A9Read2], [IIC_VUNAD, IIC_VFMULD]>; 24850b57cec5SDimitry Andricdef :ItinRW<[A9WriteV6, A9Read2], [IIC_VUNAQ, IIC_VFMULQ]>; 24860b57cec5SDimitry Andricdef :ItinRW<[A9WriteV9, A9Read3, A9Read2], [IIC_VMACD, IIC_VFMACD]>; 24870b57cec5SDimitry Andricdef :ItinRW<[A9WriteV10, A9Read3, A9Read2], [IIC_VMACQ, IIC_VFMACQ]>; 24880b57cec5SDimitry Andricdef :ItinRW<[A9WriteV9, A9Read2, A9Read2], [IIC_VRECSD]>; 24890b57cec5SDimitry Andricdef :ItinRW<[A9WriteV10, A9Read2, A9Read2], [IIC_VRECSQ]>; 24900b57cec5SDimitry Andric 24910b57cec5SDimitry Andric// Map SchedRWs that are identical for cortexa9 to existing resources. 24920b57cec5SDimitry Andricdef : SchedAlias<WriteALU, A9WriteALU>; 24930b57cec5SDimitry Andricdef : SchedAlias<WriteALUsr, A9WriteALUsr>; 24940b57cec5SDimitry Andricdef : SchedAlias<WriteALUSsr, A9WriteALUsr>; 24950b57cec5SDimitry Andricdef : SchedAlias<ReadALU, A9ReadALU>; 24960b57cec5SDimitry Andricdef : SchedAlias<ReadALUsr, A9ReadALU>; 24970b57cec5SDimitry Andricdef : SchedAlias<WriteST, A9WriteS>; 24980b57cec5SDimitry Andric 24990b57cec5SDimitry Andric// ===---------------------------------------------------------------------===// 25000b57cec5SDimitry Andric// Floating-point. Map target defined SchedReadWrite to processor specific ones 25010b57cec5SDimitry Andric// 25020b57cec5SDimitry Andricdef : WriteRes<WriteFPCVT, [A9UnitFP, A9UnitAGU]> { let Latency = 4; } 25030b57cec5SDimitry Andricdef : SchedAlias<WriteFPMOV, A9WriteFMov>; 25040b57cec5SDimitry Andric 25050b57cec5SDimitry Andricdef : SchedAlias<WriteFPALU32, A9WriteF>; 25060b57cec5SDimitry Andricdef : SchedAlias<WriteFPALU64, A9WriteF>; 25070b57cec5SDimitry Andric 25080b57cec5SDimitry Andricdef : SchedAlias<WriteFPMUL32, A9WriteFMulS>; 25090b57cec5SDimitry Andricdef : SchedAlias<WriteFPMUL64, A9WriteFMulD>; 25100b57cec5SDimitry Andric 25110b57cec5SDimitry Andricdef : SchedAlias<WriteFPMAC32, A9WriteFMAS>; 25120b57cec5SDimitry Andricdef : SchedAlias<WriteFPMAC64, A9WriteFMAD>; 25130b57cec5SDimitry Andric 25140b57cec5SDimitry Andricdef : SchedAlias<WriteFPDIV32, A9WriteFDivS>; 25150b57cec5SDimitry Andricdef : SchedAlias<WriteFPDIV64, A9WriteFDivD>; 25160b57cec5SDimitry Andricdef : SchedAlias<WriteFPSQRT32, A9WriteFSqrtS>; 25170b57cec5SDimitry Andricdef : SchedAlias<WriteFPSQRT64, A9WriteFSqrtD>; 25180b57cec5SDimitry Andric 25190b57cec5SDimitry Andricdef : ReadAdvance<ReadFPMUL, 0>; 25200b57cec5SDimitry Andricdef : ReadAdvance<ReadFPMAC, 0>; 25210b57cec5SDimitry Andric 25220b57cec5SDimitry Andric// ===---------------------------------------------------------------------===// 25230b57cec5SDimitry Andric// Subtarget-specific overrides. Map opcodes to list of SchedReadWrite types. 25240b57cec5SDimitry Andric// 25250b57cec5SDimitry Andricdef : InstRW< [WriteALU], 25260b57cec5SDimitry Andric (instregex "ANDri", "ORRri", "EORri", "BICri", "ANDrr", "ORRrr", "EORrr", 25270b57cec5SDimitry Andric "BICrr")>; 2528e8d8bef9SDimitry Andricdef : InstRW< [WriteALUsi], (instrs ANDrsi, ORRrsi, EORrsi, BICrsi)>; 2529e8d8bef9SDimitry Andricdef : InstRW< [WriteALUsr], (instrs ANDrsr, ORRrsr, EORrsr, BICrsr)>; 25300b57cec5SDimitry Andric 25310b57cec5SDimitry Andric 25320b57cec5SDimitry Andricdef : SchedAlias<WriteCMP, A9WriteALU>; 25330b57cec5SDimitry Andricdef : SchedAlias<WriteCMPsi, A9WriteALU>; 25340b57cec5SDimitry Andricdef : SchedAlias<WriteCMPsr, A9WriteALU>; 25350b57cec5SDimitry Andric 25360b57cec5SDimitry Andricdef : InstRW< [A9WriteIsr], (instregex "MOVsr", "MOVsi", "MVNsr", "MOVCCsi", 25370b57cec5SDimitry Andric "MOVCCsr")>; 25380b57cec5SDimitry Andricdef : InstRW< [WriteALU, A9ReadALU], (instregex "MVNr")>; 25390b57cec5SDimitry Andricdef : InstRW< [A9WriteI2], (instregex "MOVCCi32imm", "MOVi32imm")>; 25400b57cec5SDimitry Andricdef : InstRW< [A9WriteI2pc], (instregex "MOV_ga_pcrel")>; 25410b57cec5SDimitry Andricdef : InstRW< [A9WriteI2ld], (instregex "MOV_ga_pcrel_ldr")>; 25420b57cec5SDimitry Andric 25430b57cec5SDimitry Andricdef : InstRW< [WriteALU], (instregex "SEL")>; 25440b57cec5SDimitry Andric 25450b57cec5SDimitry Andricdef : InstRW< [WriteALUsi], (instregex "BFC", "BFI", "UBFX", "SBFX")>; 25460b57cec5SDimitry Andric 25470b57cec5SDimitry Andricdef : InstRW< [A9WriteM], 25480b57cec5SDimitry Andric (instregex "MUL", "MULv5", "SMMUL", "SMMULR", "MLA", "MLAv5", "MLS", 25490b57cec5SDimitry Andric "SMMLA", "SMMLAR", "SMMLS", "SMMLSR")>; 25500b57cec5SDimitry Andricdef : InstRW< [A9WriteM, A9WriteMHi], 25510b57cec5SDimitry Andric (instregex "SMULL", "SMULLv5", "UMULL", "UMULLv5", "SMLAL$", "UMLAL", 25520b57cec5SDimitry Andric "UMAAL", "SMLALv5", "UMLALv5", "SMLALBB", "SMLALBT", "SMLALTB", 25530b57cec5SDimitry Andric "SMLALTT")>; 25540b57cec5SDimitry Andric// FIXME: These instructions used to have NoItinerary. Just copied the one from above. 25550b57cec5SDimitry Andricdef : InstRW< [A9WriteM, A9WriteMHi], 25560b57cec5SDimitry Andric (instregex "SMLAD", "SMLADX", "SMLALD", "SMLALDX", "SMLSD", "SMLSDX", 25570b57cec5SDimitry Andric "SMLSLD", "SMLSLDX", "SMUAD", "SMUADX", "SMUSD", "SMUSDX")>; 25580b57cec5SDimitry Andric 25590b57cec5SDimitry Andricdef : InstRW<[A9WriteM16, A9WriteM16Hi], 25600b57cec5SDimitry Andric (instregex "SMULBB", "SMULBT", "SMULTB", "SMULTT", "SMULWB", "SMULWT")>; 25610b57cec5SDimitry Andricdef : InstRW<[A9WriteM16, A9WriteM16Hi], 25620b57cec5SDimitry Andric (instregex "SMLABB", "SMLABT", "SMLATB", "SMLATT", "SMLAWB", "SMLAWT")>; 25630b57cec5SDimitry Andric 25640b57cec5SDimitry Andricdef : InstRW<[A9WriteL], (instregex "LDRi12", "PICLDR$")>; 25650b57cec5SDimitry Andricdef : InstRW<[A9WriteLsi], (instregex "LDRrs")>; 25660b57cec5SDimitry Andricdef : InstRW<[A9WriteLb], 25670b57cec5SDimitry Andric (instregex "LDRBi12", "PICLDRH", "PICLDRB", "PICLDRSH", "PICLDRSB", 25680b57cec5SDimitry Andric "LDRH", "LDRSH", "LDRSB")>; 25690b57cec5SDimitry Andricdef : InstRW<[A9WriteLbsi], (instregex "LDRrs")>; 25700b57cec5SDimitry Andric 25710b57cec5SDimitry Andricdef : WriteRes<WriteDIV, []> { let Latency = 0; } 25720b57cec5SDimitry Andric 25730b57cec5SDimitry Andricdef : WriteRes<WriteBr, [A9UnitB]>; 25740b57cec5SDimitry Andricdef : WriteRes<WriteBrL, [A9UnitB]>; 25750b57cec5SDimitry Andricdef : WriteRes<WriteBrTbl, [A9UnitB]>; 25760b57cec5SDimitry Andricdef : WriteRes<WritePreLd, []>; 25770b57cec5SDimitry Andricdef : WriteRes<WriteNoop, []> { let Latency = 0; let NumMicroOps = 0; } 25780b57cec5SDimitry Andric} // SchedModel = CortexA9Model 2579