Lines Matching refs:cycles

19   // Load latency is 4 or 5 cycles depending on the load. This latency assumes
21   // There are two instructions (lxvl, lxvll) that have a latency of 6 cycles.
23   // of instructions are 4 or 5 cycles.
26   // A total of 16 cycles to recover from a branch mispredict.
191   // An ALU may take either 2 or 3 cycles to complete the operation.
219   // A DIV unit may take from 5 to 40 cycles to complete.
220   // Some DIV operations may keep the unit busy for up to 8 cycles.
245   // A DP unit may take from 2 to 36 cycles to complete.
246   // Some DP operations keep the unit busy for up to 10 cycles.
330   // Loads can have 4, 5 or 6 cycles of latency.
353   // Can take from 12 cycles to 76 cycles to obtain a result.
354   // The unit may be busy for up to 62 cycles.