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Searched refs:Vd (Results 1 – 23 of 23) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrNEON.td264 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
274 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
284 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
295 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
305 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
315 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
325 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
335 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
347 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
357 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
[all …]
H A DARMInstrCDE.td299 iname#"\t$coproc, $Vd, $imm", params.Cstr> {
313 bits<5> Vd;
315 let Inst{22} = Vd{0};
316 let Inst{15-12} = Vd{4-1};
323 bits<5> Vd;
325 let Inst{22} = Vd{4};
326 let Inst{15-12} = Vd{3-0};
360 iname#"\t$coproc, $Vd, $Vm, $imm", params.Cstr> {
374 bits<5> Vd;
377 let Inst{15-12} = Vd{4-1};
[all …]
H A DARMInstrFormats.td2278 bits<5> Vd;
2282 let Inst{22} = Vd{4};
2283 let Inst{15-12} = Vd{3-0};
2348 bits<5> Vd;
2351 let Inst{15-12} = Vd{3-0};
2352 let Inst{22} = Vd{4};
2374 bits<5> Vd;
2377 let Inst{15-12} = Vd{3-0};
2378 let Inst{22} = Vd{4};
2388 OpcodeStr, Dt, "$Vd, $Vm", "", pattern> {
[all …]
H A DARMInstrVFP.td1823 // if dp_operation then UInt(D:Vd) else UInt(Vd:D);
1836 // if dp_operation then UInt(D:Vd) else UInt(Vd:D);
/freebsd/tests/sys/cddl/zfs/tests/acl/nontrivial/
H A Dzfs_acl_chmod_inherit_003_pos.ksh292 $LS -Vd $basedir
293 $LS -Vd $node
309 $LS -Vd $basedir
310 $LS -Vd $node
334 $LS -Vd $basedir
335 $LS -Vd $node
/freebsd/contrib/llvm-project/clang/include/clang/Analysis/Analyses/
H A DThreadSafetyTIL.h379 Variable(const Variable &Vd, SExpr *D) // rewrite constructor in Variable() argument
380 : SExpr(Vd), Name(Vd.Name), Definition(D), Cvdecl(Vd.Cvdecl) { in Variable()
381 Flags = Vd.kind(); in Variable()
675 Function(Variable *Vd, SExpr *Bd) in Function() argument
676 : SExpr(COP_Function), VarDecl(Vd), Body(Bd) { in Function()
677 Vd->setKind(Variable::VK_Fun); in Function()
680 Function(const Function &F, Variable *Vd, SExpr *Bd) // rewrite constructor in Function() argument
681 : SExpr(F), VarDecl(Vd), Body(Bd) { in Function()
682 Vd->setKind(Variable::VK_Fun); in Function()
726 SFunction(Variable *Vd, SExpr *B) in SFunction() argument
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.td1460 : Pat<(VecTy (OpNode (VecTy V128:$Vd), (VecTy V128:$Vn), (VecTy V128:$Vm))),
1461 (INST (VecTy V128:$Vd), (VecTy V128:$Vn), (VecTy V128:$Vm))>;
1534 : Pat<(v4i32 (OpNode (v4i32 V128:$Vd), (v4i32 V128:$Vn), (v4i32 V128:$Vm))),
1535 (INST (v4i32 V128:$Vd), (v4i32 V128:$Vn), (v4i32 V128:$Vm))>;
1538 …: Pat<(v4i32 (OpNode (v4i32 V128:$Vd), (v4i32 V128:$Vn), (v4i32 V128:$Vm), (i64 VectorIndexS_timm:…
1539 (INST (v4i32 V128:$Vd), (v4i32 V128:$Vn), (v4i32 V128:$Vm), (VectorIndexS_timm:$imm))>;
5342 def : InstAlias<"mvn{ $Vd.8b, $Vn.8b|.8b $Vd, $Vn}",
5343 (NOTv8i8 V64:$Vd, V64:$Vn)>;
5344 def : InstAlias<"mvn{ $Vd.16b, $Vn.16b|.16b $Vd, $Vn}",
5345 (NOTv16i8 V128:$Vd, V128:$Vn)>;
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H A DAArch64SchedPredNeoverse.td81 // MOVI Vd.2D, #0
H A DAArch64SchedPredicates.td326 [// MOVI Vd, #0
331 // MOVI Vd, #0, LSL #0
H A DAArch64InstrFormats.td6743 def : InstAlias<asm # "\t$Vd.4h, $Vn.4h, #0",
6744 (!cast<Instruction>(NAME # v4i16rz) V64:$Vd, V64:$Vn), 0>;
6745 def : InstAlias<asm # "\t$Vd.8h, $Vn.8h, #0",
6746 (!cast<Instruction>(NAME # v8i16rz) V128:$Vd, V128:$Vn), 0>;
6748 def : InstAlias<asm # "\t$Vd.2s, $Vn.2s, #0",
6749 (!cast<Instruction>(NAME # v2i32rz) V64:$Vd, V64:$Vn), 0>;
6750 def : InstAlias<asm # "\t$Vd.4s, $Vn.4s, #0",
6751 (!cast<Instruction>(NAME # v4i32rz) V128:$Vd, V128:$Vn), 0>;
6752 def : InstAlias<asm # "\t$Vd.2d, $Vn.2d, #0",
6753 (!cast<Instruction>(NAME # v2i64rz) V128:$Vd, V128:$Vn), 0>;
[all …]
H A DAArch64SchedCyclone.td327 // FMOVv2f64ns Vd.2d, #0.0
336 // ORR.16b Vd,Vn,Vn
637 // Vd is read 5 cycles after issuing the vector load.
H A DAArch64InstrGISel.td462 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
H A DSVEInstrFormats.td5463 : I<(outs dstOpType:$Vd), (ins PPR3bAny:$Pg, zprty:$Zn),
5464 asm, "\t$Vd, $Pg, $Zn",
5468 bits<5> Vd;
5477 let Inst{4-0} = Vd;
7003 : I<(outs dstRegtype:$Vd), (ins PPR3bAny:$Pg, zprty:$Zn),
7004 asm, "\t$Vd, $Pg, $Zn",
7008 bits<5> Vd;
7017 let Inst{4-0} = Vd;
8298 : I<(outs dstOpType:$Vd), (ins PPR3bAny:$Pg, zprty:$Zn),
8299 asm, "\t$Vd, $Pg, $Zn",
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAGHVX.cpp808 // Vd = vpack(Vu, Vv, Size, TakeOdd)
809 // Vd = vshuff(Vu, Vv, Size, TakeOdd)
810 // Vd = vdeal(Vu, Vv, Size, TakeOdd)
811 // Vd = vdealb4w(Vu, Vv)
858 MaskT Vd(Len); in vpack() local
863 Vd[i * Size + b] = Vv[(2 * i + Odd) * Size + b]; in vpack()
864 Vd[i * Size + b + Len / 2] = Vu[(2 * i + Odd) * Size + b]; in vpack()
868 return Vd; in vpack()
873 MaskT Vd(Len); in vshuff() local
877 Vd[( in vshuff()
892 MaskT Vd(Len); vdealb4w() local
[all...]
H A DHexagonPseudo.td432 class Vsplatr_template : InstHexagon<(outs HvxVR:$Vd), (ins IntRegs:$Rs),
440 class Vsplati_template : InstHexagon<(outs HvxVR:$Vd), (ins s32_0Imm:$Val),
506 def PS_vdd0: InstHexagon<(outs HvxWR:$Vd), (ins), "", [], "",
H A DHexagonInstrInfo.cpp1278 Register Vd = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
1279 BuildMI(MBB, MI, DL, get(Hexagon::V6_vsubw_dv), Vd) in expandPostRAPseudo()
1280 .addReg(Vd, RegState::Undef) in expandPostRAPseudo()
1281 .addReg(Vd, RegState::Undef); in expandPostRAPseudo()
/freebsd/sys/contrib/openzfs/tests/zfs-tests/tests/functional/acl/
H A Dacl_common.kshlib61 ls -Vd $obj | awk '(NR != 1) {print $0}'
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1789 unsigned Vd = fieldFromInstruction(Val, 8, 5); in DecodeSPRRegListOperand() local
1793 if (regs == 0 || (Vd + regs) > 32) { in DecodeSPRRegListOperand()
1794 regs = Vd + regs > 32 ? 32 - Vd : regs; in DecodeSPRRegListOperand()
1799 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) in DecodeSPRRegListOperand()
1802 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) in DecodeSPRRegListOperand()
1814 unsigned Vd = fieldFromInstruction(Val, 8, 5); in DecodeDPRRegListOperand() local
1818 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { in DecodeDPRRegListOperand()
1819 regs = Vd + regs > 32 ? 32 - Vd : regs; in DecodeDPRRegListOperand()
1825 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) in DecodeDPRRegListOperand()
1828 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) in DecodeDPRRegListOperand()
[all …]
/freebsd/tests/sys/cddl/zfs/tests/acl/
H A Dacl_common.kshlib80 $LS -Vd $obj | $NAWK '(NR != 1) {print $0}'
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsRISCVXsf.td58 … !if(HasDst, [], [ImmArg<ArgIndex<1>>]), // Vd or bit<11-7>
/freebsd/contrib/file/tests/
H A DHWP97.hwp.testfile8 …L�rQ9L�#������ 9�}\��q]ɰ^6�G�����] ��Փ3Q׻�"����l����a�ˤ�&W:Ln�VdR�u�;*g�^���|�N���…
/freebsd/contrib/llvm-project/llvm/tools/llvm-objdump/
H A DMachODump.cpp10150 MachO::version_min_command Vd = Obj->getVersionMinLoadCommand(Command); in PrintLoadCommands() local
10151 PrintVersionMinLoadCommand(Vd); in PrintLoadCommands()
/freebsd/contrib/llvm-project/clang/include/clang/Driver/
H A DOptions.td8838 def dxc_disable_validation : DXCFlag<"Vd">,