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Searched refs:Vd (Results 1 – 24 of 24) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrNEON.td264 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
274 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
284 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
295 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
305 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
315 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
325 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
335 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
347 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
357 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
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H A DARMInstrCDE.td299 iname#"\t$coproc, $Vd, $imm", params.Cstr> {
313 bits<5> Vd;
315 let Inst{22} = Vd{0};
316 let Inst{15-12} = Vd{4-1};
323 bits<5> Vd;
325 let Inst{22} = Vd{4};
326 let Inst{15-12} = Vd{3-0};
360 iname#"\t$coproc, $Vd, $Vm, $imm", params.Cstr> {
374 bits<5> Vd;
377 let Inst{15-12} = Vd{4-1};
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H A DARMInstrFormats.td2273 bits<5> Vd;
2277 let Inst{22} = Vd{4};
2278 let Inst{15-12} = Vd{3-0};
2343 bits<5> Vd;
2346 let Inst{15-12} = Vd{3-0};
2347 let Inst{22} = Vd{4};
2369 bits<5> Vd;
2372 let Inst{15-12} = Vd{3-0};
2373 let Inst{22} = Vd{4};
2383 OpcodeStr, Dt, "$Vd, $Vm", "", pattern> {
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H A DARMInstrVFP.td1838 // if dp_operation then UInt(D:Vd) else UInt(Vd:D);
1851 // if dp_operation then UInt(D:Vd) else UInt(Vd:D);
/freebsd/tests/sys/cddl/zfs/tests/acl/nontrivial/
H A Dzfs_acl_chmod_inherit_003_pos.ksh292 $LS -Vd $basedir
293 $LS -Vd $node
309 $LS -Vd $basedir
310 $LS -Vd $node
334 $LS -Vd $basedir
335 $LS -Vd $node
/freebsd/contrib/llvm-project/clang/include/clang/Analysis/Analyses/
H A DThreadSafetyTIL.h380 Variable(const Variable &Vd, SExpr *D) // rewrite constructor in Variable() argument
381 : SExpr(Vd), Name(Vd.Name), Definition(D), Cvdecl(Vd.Cvdecl) { in Variable()
382 Flags = Vd.kind(); in Variable()
676 Function(Variable *Vd, SExpr *Bd) in Function() argument
677 : SExpr(COP_Function), VarDecl(Vd), Body(Bd) { in Function()
678 Vd->setKind(Variable::VK_Fun); in Function()
681 Function(const Function &F, Variable *Vd, SExpr *Bd) // rewrite constructor in Function() argument
682 : SExpr(F), VarDecl(Vd), Body(Bd) { in Function()
683 Vd->setKind(Variable::VK_Fun); in Function()
727 SFunction(Variable *Vd, SExpr *B) in SFunction() argument
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/freebsd/contrib/llvm-project/clang/lib/Analysis/
H A DThreadSafety.cpp273 bool containsMutexDecl(FactManager &FM, const ValueDecl* Vd) const { in containsMutexDecl()
275 *this, [&](FactID ID) -> bool { return FM[ID].valueDecl() == Vd; }); in containsMutexDecl()
306 BeforeInfo* insertAttrExprs(const ValueDecl* Vd,
309 BeforeInfo *getBeforeInfoForDecl(const ValueDecl *Vd,
312 void checkBeforeAfter(const ValueDecl* Vd,
1159 BeforeSet::BeforeInfo* BeforeSet::insertAttrExprs(const ValueDecl* Vd, in insertAttrExprs() argument
1166 std::unique_ptr<BeforeInfo> &InfoPtr = BMap[Vd]; in insertAttrExprs()
1172 for (const auto *At : Vd->attrs()) { in insertAttrExprs()
1200 ArgInfo->Vect.push_back(Vd); in insertAttrExprs()
1214 BeforeSet::getBeforeInfoForDecl(const ValueDecl *Vd, in getBeforeInfoForDecl() argument
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAGHVX.cpp853 MaskT Vd(Len); in vpack() local
858 Vd[i * Size + b] = Vv[(2 * i + Odd) * Size + b]; in vpack()
859 Vd[i * Size + b + Len / 2] = Vu[(2 * i + Odd) * Size + b]; in vpack()
863 return Vd; in vpack()
868 MaskT Vd(Len); in vshuff() local
872 Vd[(2 * i + 0) * Size + b] = Vv[(2 * i + Odd) * Size + b]; in vshuff()
873 Vd[(2 * i + 1) * Size + b] = Vu[(2 * i + Odd) * Size + b]; in vshuff()
876 return Vd; in vshuff()
887 MaskT Vd(Len); in vdealb4w() local
889 Vd[0 * (Len / 4) + i] = Vv[4 * i + 0]; in vdealb4w()
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H A DHexagonPseudo.td432 class Vsplatr_template : InstHexagon<(outs HvxVR:$Vd), (ins IntRegs:$Rs),
440 class Vsplati_template : InstHexagon<(outs HvxVR:$Vd), (ins s32_0Imm:$Val),
506 def PS_vdd0: InstHexagon<(outs HvxWR:$Vd), (ins), "", [], "",
H A DHexagonInstrInfo.cpp1281 Register Vd = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
1282 BuildMI(MBB, MI, DL, get(Hexagon::V6_vsubw_dv), Vd) in expandPostRAPseudo()
1283 .addReg(Vd, RegState::Undef) in expandPostRAPseudo()
1284 .addReg(Vd, RegState::Undef); in expandPostRAPseudo()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedPredNeoverse.td81 // MOVI Vd.2D, #0
H A DAArch64InstrInfo.td1763 : Pat<(VecTy (OpNode (VecTy V128:$Vd), (VecTy V128:$Vn), (VecTy V128:$Vm))),
1764 (INST (VecTy V128:$Vd), (VecTy V128:$Vn), (VecTy V128:$Vm))>;
1837 : Pat<(v4i32 (OpNode (v4i32 V128:$Vd), (v4i32 V128:$Vn), (v4i32 V128:$Vm))),
1838 (INST (v4i32 V128:$Vd), (v4i32 V128:$Vn), (v4i32 V128:$Vm))>;
1841 …: Pat<(v4i32 (OpNode (v4i32 V128:$Vd), (v4i32 V128:$Vn), (v4i32 V128:$Vm), (i64 VectorIndexS_timm:…
1842 (INST (v4i32 V128:$Vd), (v4i32 V128:$Vn), (v4i32 V128:$Vm), (VectorIndexS_timm:$imm))>;
5828 def : InstAlias<"mvn{ $Vd.8b, $Vn.8b|.8b $Vd, $Vn}",
5829 (NOTv8i8 V64:$Vd, V64:$Vn)>;
5830 def : InstAlias<"mvn{ $Vd.16b, $Vn.16b|.16b $Vd, $Vn}",
5831 (NOTv16i8 V128:$Vd, V128:$Vn)>;
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H A DAArch64SchedPredicates.td326 [// MOVI Vd, #0
331 // MOVI Vd, #0, LSL #0
H A DAArch64InstrFormats.td7143 def : InstAlias<asm # "\t$Vd.4h, $Vn.4h, #0",
7144 (!cast<Instruction>(NAME # v4i16rz) V64:$Vd, V64:$Vn), 0>;
7145 def : InstAlias<asm # "\t$Vd.8h, $Vn.8h, #0",
7146 (!cast<Instruction>(NAME # v8i16rz) V128:$Vd, V128:$Vn), 0>;
7148 def : InstAlias<asm # "\t$Vd.2s, $Vn.2s, #0",
7149 (!cast<Instruction>(NAME # v2i32rz) V64:$Vd, V64:$Vn), 0>;
7150 def : InstAlias<asm # "\t$Vd.4s, $Vn.4s, #0",
7151 (!cast<Instruction>(NAME # v4i32rz) V128:$Vd, V128:$Vn), 0>;
7152 def : InstAlias<asm # "\t$Vd.2d, $Vn.2d, #0",
7153 (!cast<Instruction>(NAME # v2i64rz) V128:$Vd, V128:$Vn), 0>;
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H A DAArch64InstrGISel.td405 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
H A DAArch64SchedCyclone.td327 // FMOVv2f64ns Vd.2d, #0.0
336 // ORR.16b Vd,Vn,Vn
637 // Vd is read 5 cycles after issuing the vector load.
H A DSVEInstrFormats.td5961 : I<(outs dstOpType:$Vd), (ins PPR3bAny:$Pg, zprty:$Zn),
5962 asm, "\t$Vd, $Pg, $Zn",
5966 bits<5> Vd;
5975 let Inst{4-0} = Vd;
7501 : I<(outs dstRegtype:$Vd), (ins PPR3bAny:$Pg, zprty:$Zn),
7502 asm, "\t$Vd, $Pg, $Zn",
7506 bits<5> Vd;
7515 let Inst{4-0} = Vd;
8925 : I<(outs dstOpType:$Vd), (ins PPR3bAny:$Pg, zprty:$Zn),
8926 asm, "\t$Vd, $Pg, $Zn",
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/freebsd/sys/contrib/openzfs/tests/zfs-tests/tests/functional/acl/
H A Dacl_common.kshlib52 ls -Vd $obj | awk '(NR != 1) {print $0}'
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1794 unsigned Vd = fieldFromInstruction(Val, 8, 5); in DecodeSPRRegListOperand() local
1798 if (regs == 0 || (Vd + regs) > 32) { in DecodeSPRRegListOperand()
1799 regs = Vd + regs > 32 ? 32 - Vd : regs; in DecodeSPRRegListOperand()
1804 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) in DecodeSPRRegListOperand()
1807 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) in DecodeSPRRegListOperand()
1819 unsigned Vd = fieldFromInstruction(Val, 8, 5); in DecodeDPRRegListOperand() local
1824 if (regs == 0 || (Vd + regs) > MaxReg) { in DecodeDPRRegListOperand()
1825 regs = Vd + regs > MaxReg ? MaxReg - Vd : regs; in DecodeDPRRegListOperand()
1831 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) in DecodeDPRRegListOperand()
1834 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) in DecodeDPRRegListOperand()
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/freebsd/tests/sys/cddl/zfs/tests/acl/
H A Dacl_common.kshlib80 $LS -Vd $obj | $NAWK '(NR != 1) {print $0}'
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsRISCVXsf.td51 … !if(HasDst, [], [ImmArg<ArgIndex<1>>]), // Vd or bit<11-7>
/freebsd/contrib/file/tests/
H A DHWP97.hwp.testfile8 …L�rQ9L�#������ 9�}\��q]ɰ^6�G�����] ��Փ3Q׻�"����l����a�ˤ�&W:Ln�VdR�u�;*g�^���|�N���…
/freebsd/contrib/llvm-project/llvm/tools/llvm-objdump/
H A DMachODump.cpp10169 MachO::version_min_command Vd = Obj->getVersionMinLoadCommand(Command); in PrintLoadCommands() local
10170 PrintVersionMinLoadCommand(Vd); in PrintLoadCommands()
/freebsd/contrib/llvm-project/clang/include/clang/Driver/
H A DOptions.td9413 def dxc_disable_validation : DXCFlag<"Vd">,