Lines Matching refs:Vd
264 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
274 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
284 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
295 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
305 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
315 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
325 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
335 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
347 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
357 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
367 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
377 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
387 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
398 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
408 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
418 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
428 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
438 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
600 : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd),
602 "vld1", Dt, "$Vd, $Rn", "", []>, Sched<[WriteVLD1]> {
608 : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd),
610 "vld1", Dt, "$Vd, $Rn", "", []>, Sched<[WriteVLD2]> {
628 def _fixed : NLdSt<0,0b10, 0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
630 "vld1", Dt, "$Vd, $Rn!",
636 def _register : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
638 "vld1", Dt, "$Vd, $Rn, $Rm",
645 def _fixed : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),
647 "vld1", Dt, "$Vd, $Rn!",
653 def _register : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),
655 "vld1", Dt, "$Vd, $Rn, $Rm",
673 : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd),
675 "$Vd, $Rn", "", []>, Sched<[WriteVLD3]> {
681 def _fixed : NLdSt<0,0b10,0b0110, op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
683 "vld1", Dt, "$Vd, $Rn!",
689 def _register : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
691 "vld1", Dt, "$Vd, $Rn, $Rm",
736 : NLdSt<0, 0b10, 0b0010, op7_4, (outs VecListFourD:$Vd),
738 "$Vd, $Rn", "", []>, Sched<[WriteVLD4]> {
744 def _fixed : NLdSt<0,0b10,0b0010, op7_4, (outs VecListFourD:$Vd, GPR:$wb),
746 "vld1", Dt, "$Vd, $Rn!",
752 def _register : NLdSt<0,0b10,0b0010,op7_4, (outs VecListFourD:$Vd, GPR:$wb),
754 "vld1", Dt, "$Vd, $Rn, $Rm",
800 : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd),
802 "vld2", Dt, "$Vd, $Rn", "", []> {
829 def _fixed : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb),
831 "vld2", Dt, "$Vd, $Rn!",
837 def _register : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb),
839 "vld2", Dt, "$Vd, $Rn, $Rm",
883 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
885 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []>, Sched<[WriteVLD3]> {
902 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
904 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm",
942 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
944 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []>,
962 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
964 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
1031 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
1033 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
1034 "$src = $Vd",
1035 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
1043 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
1045 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
1046 "$src = $Vd",
1047 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
1117 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, GPR:$wb),
1120 "\\{$Vd[$lane]\\}, $Rn$Rm",
1121 "$src = $Vd, $Rn.addr = $wb", []>, Sched<[WriteVLD1]> {
1144 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
1146 IIC_VLD2ln, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn",
1147 "$src1 = $Vd, $src2 = $dst2", []>, Sched<[WriteVLD1]> {
1180 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
1183 "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm",
1184 "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb", []> {
1215 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
1218 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn",
1219 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3", []>, Sched<[WriteVLD2]> {
1252 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
1256 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm",
1257 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb",
1289 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
1292 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn",
1293 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>,
1330 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
1334 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn$Rm",
1335 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb",
1372 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListOneDAllLanes:$Vd),
1374 IIC_VLD1dup, "vld1", Dt, "$Vd, $Rn", "",
1375 [(set VecListOneDAllLanes:$Vd,
1396 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListDPairAllLanes:$Vd),
1398 "vld1", Dt, "$Vd, $Rn", "",
1399 [(set VecListDPairAllLanes:$Vd,
1422 (outs VecListOneDAllLanes:$Vd, GPR:$wb),
1424 "vld1", Dt, "$Vd, $Rn!",
1431 (outs VecListOneDAllLanes:$Vd, GPR:$wb),
1433 "vld1", Dt, "$Vd, $Rn, $Rm",
1441 (outs VecListDPairAllLanes:$Vd, GPR:$wb),
1443 "vld1", Dt, "$Vd, $Rn!",
1450 (outs VecListDPairAllLanes:$Vd, GPR:$wb),
1452 "vld1", Dt, "$Vd, $Rn, $Rm",
1469 : NLdSt<1, 0b10, 0b1101, op7_4, (outs VdTy:$Vd),
1471 "vld2", Dt, "$Vd, $Rn", "", []> {
1519 (outs VdTy:$Vd, GPR:$wb),
1521 "vld2", Dt, "$Vd, $Rn!",
1528 (outs VdTy:$Vd, GPR:$wb),
1530 "vld2", Dt, "$Vd, $Rn, $Rm",
1560 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
1562 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn", "", []>,
1591 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
1593 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn$Rm",
1618 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
1620 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn", "", []> {
1649 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
1651 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn$Rm",
1717 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins AddrMode:$Rn, VecListOneD:$Vd),
1718 IIC_VST1, "vst1", Dt, "$Vd, $Rn", "", []>, Sched<[WriteVST1]> {
1724 : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins AddrMode:$Rn, VecListDPair:$Vd),
1725 IIC_VST1x2, "vst1", Dt, "$Vd, $Rn", "", []>, Sched<[WriteVST2]> {
1744 (ins AddrMode:$Rn, VecListOneD:$Vd), IIC_VLD1u,
1745 "vst1", Dt, "$Vd, $Rn!",
1752 (ins AddrMode:$Rn, rGPR:$Rm, VecListOneD:$Vd),
1754 "vst1", Dt, "$Vd, $Rn, $Rm",
1762 (ins AddrMode:$Rn, VecListDPair:$Vd), IIC_VLD1x2u,
1763 "vst1", Dt, "$Vd, $Rn!",
1770 (ins AddrMode:$Rn, rGPR:$Rm, VecListDPair:$Vd),
1772 "vst1", Dt, "$Vd, $Rn, $Rm",
1792 (ins AddrMode:$Rn, VecListThreeD:$Vd),
1793 IIC_VST1x3, "vst1", Dt, "$Vd, $Rn", "", []>, Sched<[WriteVST3]> {
1800 (ins AddrMode:$Rn, VecListThreeD:$Vd), IIC_VLD1x3u,
1801 "vst1", Dt, "$Vd, $Rn!",
1808 (ins AddrMode:$Rn, rGPR:$Rm, VecListThreeD:$Vd),
1810 "vst1", Dt, "$Vd, $Rn, $Rm",
1858 (ins AddrMode:$Rn, VecListFourD:$Vd),
1859 IIC_VST1x4, "vst1", Dt, "$Vd, $Rn", "",
1867 (ins AddrMode:$Rn, VecListFourD:$Vd), IIC_VLD1x4u,
1868 "vst1", Dt, "$Vd, $Rn!",
1875 (ins AddrMode:$Rn, rGPR:$Rm, VecListFourD:$Vd),
1877 "vst1", Dt, "$Vd, $Rn, $Rm",
1925 : NLdSt<0, 0b00, op11_8, op7_4, (outs), (ins AddrMode:$Rn, VdTy:$Vd),
1926 itin, "vst2", Dt, "$Vd, $Rn", "", []> {
1954 (ins AddrMode:$Rn, VdTy:$Vd), IIC_VLD1u,
1955 "vst2", Dt, "$Vd, $Rn!",
1962 (ins AddrMode:$Rn, rGPR:$Rm, VdTy:$Vd), IIC_VLD1u,
1963 "vst2", Dt, "$Vd, $Rn, $Rm",
1971 (ins AddrMode:$Rn, VecListFourD:$Vd), IIC_VLD1u,
1972 "vst2", Dt, "$Vd, $Rn!",
1979 (ins AddrMode:$Rn, rGPR:$Rm, VecListFourD:$Vd),
1981 "vst2", Dt, "$Vd, $Rn, $Rm",
2023 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3,
2024 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []>, Sched<[WriteVST3]> {
2042 DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3u,
2043 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
2081 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
2082 IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
2101 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u,
2102 "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
2167 (ins AddrMode:$Rn, DPR:$Vd, nohash_imm:$lane),
2168 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
2169 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), AddrMode:$Rn)]>,
2217 DPR:$Vd, nohash_imm:$lane), IIC_VST1lnu, "vst1", Dt,
2218 "\\{$Vd[$lane]\\}, $Rn$Rm",
2220 [(set GPR:$wb, (StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane),
2255 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane),
2256 IIC_VST2ln, "vst2", Dt, "\\{$Vd[$lane], $src2[$lane]\\}, $Rn",
2294 DPR:$Vd, DPR:$src2, nohash_imm:$lane), IIC_VST2lnu, "vst2", Dt,
2295 "\\{$Vd[$lane], $src2[$lane]\\}, $Rn$Rm",
2328 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3,
2330 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []>,
2365 DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane),
2367 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm",
2399 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4,
2401 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn",
2439 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
2441 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm",
2524 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2525 (ins DPR:$Vm), IIC_VUNAD, OpcodeStr, Dt,"$Vd, $Vm", "",
2526 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm))))]>;
2530 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2531 (ins QPR:$Vm), IIC_VUNAQ, OpcodeStr, Dt,"$Vd, $Vm", "",
2532 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm))))]>;
2539 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2540 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2541 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2546 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2547 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2548 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2554 : N2Vnp<op19_18, op17_16, op10_8, op7, 0, (outs DPR:$Vd), (ins DPR:$Vm),
2556 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2561 : N2Vnp<op19_18, op17_16, op10_8, op7, 1, (outs QPR:$Vd), (ins QPR:$Vm),
2563 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2569 : N2Vnp<op19_18, op17_16, op10_8, op7, op6, (outs QPR:$Vd), (ins QPR:$Vm),
2571 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2573 // Same as N2VQIntXnp but with Vd as a src register.
2578 (outs QPR:$Vd), (ins QPR:$src, QPR:$Vm),
2580 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src), (OpTy QPR:$Vm))))]> {
2581 let Constraints = "$src = $Vd";
2589 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
2590 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2591 [(set DPR:$Vd, (TyD (OpNode (TyQ QPR:$Vm))))]>;
2598 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
2599 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2600 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vm))))]>;
2607 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
2608 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2609 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vm))))]>;
2616 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
2617 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2618 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vm))))]>;
2622 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$Vd, DPR:$Vm),
2624 OpcodeStr, Dt, "$Vd, $Vm",
2625 "$src1 = $Vd, $src2 = $Vm", []>;
2628 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$Vd, QPR:$Vm),
2629 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$Vd, $Vm",
2630 "$src1 = $Vd, $src2 = $Vm", []>;
2637 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2638 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2639 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
2641 let TwoOperandAliasConstraint = "$Vn = $Vd";
2650 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2651 OpcodeStr, "$Vd, $Vn, $Vm", "",
2652 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>{
2654 let TwoOperandAliasConstraint = "$Vn = $Vd";
2662 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2663 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2664 [(set (Ty DPR:$Vd),
2668 let TwoOperandAliasConstraint = "$Vn = $Vd";
2674 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2675 NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane","",
2676 [(set (Ty DPR:$Vd),
2680 let TwoOperandAliasConstraint = "$Vn = $Vd";
2688 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2689 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2690 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2692 let TwoOperandAliasConstraint = "$Vn = $Vd";
2699 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2700 OpcodeStr, "$Vd, $Vn, $Vm", "",
2701 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>{
2703 let TwoOperandAliasConstraint = "$Vn = $Vd";
2710 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2711 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2712 [(set (ResTy QPR:$Vd),
2717 let TwoOperandAliasConstraint = "$Vn = $Vd";
2723 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2724 NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane", "",
2725 [(set (ResTy QPR:$Vd),
2730 let TwoOperandAliasConstraint = "$Vn = $Vd";
2739 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), f, itin,
2740 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2741 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
2743 let TwoOperandAliasConstraint = "$Vn = $Vd";
2752 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), f, itin, OpcodeStr, Dt,
2753 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
2761 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2762 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2763 [(set (Ty DPR:$Vd),
2773 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2774 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2775 [(set (Ty DPR:$Vd),
2784 (outs DPR:$Vd), (ins DPR:$Vm, DPR:$Vn), f, itin,
2785 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
2786 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (OpTy DPR:$Vn))))]> {
2787 let TwoOperandAliasConstraint = "$Vm = $Vd";
2795 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin,
2796 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2797 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2799 let TwoOperandAliasConstraint = "$Vn = $Vd";
2808 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin, OpcodeStr, Dt,
2809 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2813 // Same as N3VQIntnp but with Vd as a src register.
2819 (outs QPR:$Vd), (ins QPR:$src, QPR:$Vn, QPR:$Vm),
2821 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src), (OpTy QPR:$Vn),
2823 let Constraints = "$src = $Vd";
2831 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2832 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2833 [(set (ResTy QPR:$Vd),
2843 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2844 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2845 [(set (ResTy QPR:$Vd),
2855 (outs QPR:$Vd), (ins QPR:$Vm, QPR:$Vn), f, itin,
2856 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
2857 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (OpTy QPR:$Vn))))]> {
2858 let TwoOperandAliasConstraint = "$Vm = $Vd";
2867 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2868 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2869 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2876 (outs DPR:$Vd),
2879 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2880 [(set (Ty DPR:$Vd),
2889 (outs DPR:$Vd),
2892 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2893 [(set (Ty DPR:$Vd),
2903 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2904 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2905 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2911 (outs QPR:$Vd),
2914 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2915 [(set (ResTy QPR:$Vd),
2925 (outs QPR:$Vd),
2928 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2929 [(set (ResTy QPR:$Vd),
2940 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2941 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2942 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2948 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2949 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2950 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2959 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2960 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2961 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$src1),
2967 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2968 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2969 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src1),
2977 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2978 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2979 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2985 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2988 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2989 [(set QPR:$Vd,
2997 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
3000 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
3001 [(set QPR:$Vd,
3013 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
3014 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
3015 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
3025 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
3026 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
3027 [(set QPR:$Vd,
3033 (outs QPR:$Vd),
3036 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
3037 [(set (ResTy QPR:$Vd),
3046 (outs QPR:$Vd),
3049 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
3050 [(set (ResTy QPR:$Vd),
3061 (outs DPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINi4D,
3062 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
3063 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vn), (TyQ QPR:$Vm))))]> {
3072 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
3073 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
3074 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
3082 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
3083 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
3084 [(set QPR:$Vd,
3091 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
3092 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
3093 [(set QPR:$Vd,
3103 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
3104 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
3105 [(set QPR:$Vd, (OpNode (TyQ (ExtOp (TyD DPR:$Vn))),
3116 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
3117 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
3118 [(set QPR:$Vd, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
3128 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
3129 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
3130 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
3140 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin, OpcodeStr, Dt,
3141 [(set QPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
3150 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
3151 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
3152 [(set (ResTy QPR:$Vd),
3160 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
3161 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
3162 [(set (ResTy QPR:$Vd),
3172 (outs QPR:$Vd), (ins QPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VSUBiD,
3173 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
3174 [(set QPR:$Vd, (OpNode (TyQ QPR:$Vn),
3177 let TwoOperandAliasConstraint = "$Vn = $Vd";
3186 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
3187 (ins DPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
3188 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
3193 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
3194 (ins QPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
3195 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
3205 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vm), IIC_VPALiD,
3206 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
3207 [(set DPR:$Vd, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$Vm))))]>;
3213 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vm), IIC_VPALiQ,
3214 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
3215 [(set QPR:$Vd, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$Vm))))]>;
3219 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
3224 (outs DPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), f, itin,
3225 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3226 [(set DPR:$Vd, (Ty (OpNode (Ty DPR:$Vm), (i32 imm:$SIMM))))]>;
3231 (outs QPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), f, itin,
3232 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3233 [(set QPR:$Vd, (Ty (OpNode (Ty QPR:$Vm), (i32 imm:$SIMM))))]>;
3242 (outs QPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), N2RegVShLFrm,
3243 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3244 [(set QPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm), ImmTy:$SIMM)))]>;
3252 (outs DPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, itin,
3253 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3254 [(set DPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm),
3259 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
3263 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
3265 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
3266 [(set DPR:$Vd, (Ty (add DPR:$src1,
3271 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
3273 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
3274 [(set QPR:$Vd, (Ty (add QPR:$src1,
3280 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
3284 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
3286 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
3287 [(set DPR:$Vd, (Ty (ShOp DPR:$src1, DPR:$Vm, (i32 imm:$SIMM))))]>;
3291 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
3293 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
3294 [(set QPR:$Vd, (Ty (ShOp QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))]>;
3303 (outs DPR:$Vd), (ins DPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
3304 IIC_VUNAD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3305 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (i32 imm:$SIMM))))]>;
3310 (outs QPR:$Vd), (ins QPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
3311 IIC_VUNAQ, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3312 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (i32 imm:$SIMM))))]>;
3333 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3335 [(set DPR:$Vd, (v8i8 (ARMvcmpz (v8i8 DPR:$Vm), fc)))]>;
3337 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3339 [(set DPR:$Vd, (v4i16 (ARMvcmpz (v4i16 DPR:$Vm), fc)))]>;
3341 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3343 [(set DPR:$Vd, (v2i32 (ARMvcmpz (v2i32 DPR:$Vm), fc)))]>;
3345 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3347 [(set DPR:$Vd, (v2i32 (ARMvcmpz (v2f32 DPR:$Vm), fc)))]> {
3351 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3353 [(set DPR:$Vd, (v4i16 (ARMvcmpz (v4f16 DPR:$Vm), fc)))]>,
3360 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3362 [(set QPR:$Vd, (v16i8 (ARMvcmpz (v16i8 QPR:$Vm), fc)))]>;
3364 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3366 [(set QPR:$Vd, (v8i16 (ARMvcmpz (v8i16 QPR:$Vm), fc)))]>;
3368 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3370 [(set QPR:$Vd, (v4i32 (ARMvcmpz (v4i32 QPR:$Vm), fc)))]>;
3372 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3374 [(set QPR:$Vd, (v4i32 (ARMvcmpz (v4f32 QPR:$Vm), fc)))]> {
3378 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3380 [(set QPR:$Vd, (v8i16 (ARMvcmpz (v8f16 QPR:$Vm), fc)))]>,
3391 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
3392 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
3393 [(set QPR:$Vd, (ResTy (ARMvcmp (OpTy QPR:$Vn), (OpTy QPR:$Vm), fc)))]> {
3395 let TwoOperandAliasConstraint = "$Vn = $Vd";
3403 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
3404 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
3405 [(set DPR:$Vd, (ResTy (ARMvcmp (OpTy DPR:$Vn), (OpTy DPR:$Vm), fc)))]> {
3407 let TwoOperandAliasConstraint = "$Vn = $Vd";
4821 (ins RegTy:$Vd, RegTy:$Vn, RegTy:$Vm), N3RegFrm, IIC_VDOTPROD,
4824 (OpNode (AccumTy RegTy:$Vd),
4829 let Constraints = "$dst = $Vd";
4842 (ins Ty:$Vd, Ty:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
4846 let AsmString = !strconcat(opc, ".", dt, "\t$Vd, $Vn, $Vm$lane");
4847 let Constraints = "$dst = $Vd";
4853 (AccumType (OpNode (AccumType Ty:$Vd),
4858 (!cast<Instruction>(NAME) Ty:$Vd, Ty:$Vn, RHS, VectorIndex32:$lane)>;
4875 (ins QPR:$Vd, QPR:$Vn, QPR:$Vm), N3RegFrm, NoItinerary,
4877 [(set (v4i32 QPR:$dst), (OpNode (v4i32 QPR:$Vd),
4881 let Constraints = "$dst = $Vd";
4889 (ins RegTy:$Vd, RegTy:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane), N3RegFrm,
4893 let AsmString = !strconcat(Asm, ".", AsmTy, "\t$Vd, $Vn, $Vm$lane");
4895 let Constraints = "$dst = $Vd";
4899 (AccumTy (OpNode (AccumTy RegTy:$Vd),
4904 (!cast<Instruction>(NAME) RegTy:$Vd, RegTy:$Vn, RHS, VectorIndex32:$lane)>;
4911 (AccumTy (int_arm_neon_usdot (AccumTy RegTy:$Vd),
4916 (!cast<Instruction>(NAME) RegTy:$Vd, RegTy:$Vn, RHS, VectorIndex32:$lane)>;
4938 iops, itin, opc, dt, "$Vd, $Vn, $Vm, $rot", "$src1 = $Vd", pattern>{
4947 iops, itin, opc, dt, "$Vd, $Vn, $Vm, $rot", "", pattern> {
4956 "$Vd, $Vn, $Vm$lane, $rot", "$src1 = $Vd", pattern> {
4968 "$Vd, $Vn, $Vm$lane, $rot", "$src1 = $Vd", pattern> {
4983 def v4f16 : BaseN3VCP8ComplexTied<op21, op4, 0, 0, IIC_VMACD, (outs DPR:$Vd),
4986 def v8f16 : BaseN3VCP8ComplexTied<op21, op4, 0, 1, IIC_VMACQ, (outs QPR:$Vd),
4991 def v2f32 : BaseN3VCP8ComplexTied<op21, op4, 1, 0, IIC_VMACD, (outs DPR:$Vd),
4994 def v4f32 : BaseN3VCP8ComplexTied<op21, op4, 1, 1, IIC_VMACQ, (outs QPR:$Vd),
5004 (outs DPR:$Vd),
5008 (outs QPR:$Vd),
5014 (outs DPR:$Vd),
5018 (outs QPR:$Vd),
5029 (outs DPR:$Vd),
5034 (outs QPR:$Vd),
5041 (outs DPR:$Vd),
5046 (outs QPR:$Vd),
5146 let TwoOperandAliasConstraint = "$Vm = $Vd" in
5148 "$Vd, $Vm, #0", ARMCCeq>;
5166 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
5168 "$Vd, $Vm, #0", ARMCCge>;
5170 "$Vd, $Vm, #0", ARMCCle>;
5189 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
5191 "$Vd, $Vm, #0", ARMCCgt>;
5193 "$Vd, $Vm, #0", ARMCClt>;
5222 def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vn, $Vm",
5223 (VACGTfd DPR:$Vd, DPR:$Vm, DPR:$Vn, pred:$p)>;
5224 def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vn, $Vm",
5225 (VACGTfq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p)>;
5226 def: NEONInstAlias<"vacle${p}.f32 $Vd, $Vn, $Vm",
5227 (VACGEfd DPR:$Vd, DPR:$Vm, DPR:$Vn, pred:$p)>;
5228 def: NEONInstAlias<"vacle${p}.f32 $Vd, $Vn, $Vm",
5229 (VACGEfq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p)>;
5231 def: NEONInstAlias<"vaclt${p}.f16 $Vd, $Vn, $Vm",
5232 (VACGThd DPR:$Vd, DPR:$Vm, DPR:$Vn, pred:$p)>;
5233 def: NEONInstAlias<"vaclt${p}.f16 $Vd, $Vn, $Vm",
5234 (VACGThq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p)>;
5235 def: NEONInstAlias<"vacle${p}.f16 $Vd, $Vn, $Vm",
5236 (VACGEhd DPR:$Vd, DPR:$Vm, DPR:$Vn, pred:$p)>;
5237 def: NEONInstAlias<"vacle${p}.f16 $Vd, $Vn, $Vm",
5238 (VACGEhq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p)>;
5246 : N3VCP8<op1, op2, 1, op3, (outs Td:$Vd), (ins Tn:$Vn, Tm:$Vm), NoItinerary,
5247 asm, "f16", "$Vd, $Vn, $Vm", "", []>;
5251 : N3VCP8Q0<op1, op2, 0, op3, (outs Td:$Vd), (ins Tn:$Vn, Tm:$Vm), NoItinerary,
5252 asm, "f16", "$Vd, $Vn, $Vm", "", []>;
5254 // Vd, Vs, Vs[0-15], Idx[0-1]
5256 : N3VLaneCP8<0, S, 0, 1, (outs DPR:$Vd),
5258 IIC_VMACD, opc, type, "$Vd, $Vn, $Vm$idx", "", []> {
5267 // Vq, Vd, Vd[0-7], Idx[0-3]
5269 : N3VLaneCP8<0, S, 1, 1, (outs QPR:$Vd),
5271 IIC_VMACD, opc, type, "$Vd, $Vn, $Vm$idx", "", []> {
5289 def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vm",
5290 (VACGTfd DPR:$Vd, DPR:$Vm, DPR:$Vd, pred:$p)>;
5291 def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vm",
5292 (VACGTfq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p)>;
5293 def: NEONInstAlias<"vacle${p}.f32 $Vd, $Vm",
5294 (VACGEfd DPR:$Vd, DPR:$Vm, DPR:$Vd, pred:$p)>;
5295 def: NEONInstAlias<"vacle${p}.f32 $Vd, $Vm",
5296 (VACGEfq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p)>;
5298 def: NEONInstAlias<"vaclt${p}.f16 $Vd, $Vm",
5299 (VACGThd DPR:$Vd, DPR:$Vm, DPR:$Vd, pred:$p)>;
5300 def: NEONInstAlias<"vaclt${p}.f16 $Vd, $Vm",
5301 (VACGThq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p)>;
5302 def: NEONInstAlias<"vacle${p}.f16 $Vd, $Vm",
5303 (VACGEhd DPR:$Vd, DPR:$Vm, DPR:$Vd, pred:$p)>;
5304 def: NEONInstAlias<"vacle${p}.f16 $Vd, $Vm",
5305 (VACGEhq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p)>;
5358 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
5360 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
5361 [(set DPR:$Vd,
5367 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
5369 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
5370 [(set DPR:$Vd,
5376 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
5378 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
5379 [(set QPR:$Vd,
5385 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
5387 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
5388 [(set QPR:$Vd,
5395 let TwoOperandAliasConstraint = "$Vn = $Vd" in {
5396 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
5398 "vbic", "$Vd, $Vn, $Vm", "",
5399 [(set DPR:$Vd, (v2i32 (and DPR:$Vn,
5401 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
5403 "vbic", "$Vd, $Vn, $Vm", "",
5404 [(set QPR:$Vd, (v4i32 (and QPR:$Vn,
5414 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
5416 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
5417 [(set DPR:$Vd,
5423 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
5425 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
5426 [(set DPR:$Vd,
5432 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
5434 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
5435 [(set QPR:$Vd,
5441 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
5443 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
5444 [(set QPR:$Vd,
5450 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$Vd),
5452 "vorn", "$Vd, $Vn, $Vm", "",
5453 [(set DPR:$Vd, (v2i32 (or DPR:$Vn,
5455 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$Vd),
5457 "vorn", "$Vd, $Vn, $Vm", "",
5458 [(set QPR:$Vd, (v4i32 (or QPR:$Vn,
5470 def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$Vd),
5472 "vmvn", "i16", "$Vd, $SIMM", "",
5473 [(set DPR:$Vd, (v4i16 (ARMvmvnImm timm:$SIMM)))]> {
5477 def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$Vd),
5479 "vmvn", "i16", "$Vd, $SIMM", "",
5480 [(set QPR:$Vd, (v8i16 (ARMvmvnImm timm:$SIMM)))]> {
5484 def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$Vd),
5486 "vmvn", "i32", "$Vd, $SIMM", "",
5487 [(set DPR:$Vd, (v2i32 (ARMvmvnImm timm:$SIMM)))]> {
5491 def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$Vd),
5493 "vmvn", "i32", "$Vd, $SIMM", "",
5494 [(set QPR:$Vd, (v4i32 (ARMvmvnImm timm:$SIMM)))]> {
5501 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VSUBiD,
5502 "vmvn", "$Vd, $Vm", "",
5503 [(set DPR:$Vd, (v2i32 (vnotd DPR:$Vm)))]>;
5505 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VSUBiD,
5506 "vmvn", "$Vd, $Vm", "",
5507 [(set QPR:$Vd, (v4i32 (vnotq QPR:$Vm)))]>;
5528 : PseudoNeonI<(outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
5530 [(set DPR:$Vd,
5549 def : Pat<(v8i8 (or (and DPR:$Vn, DPR:$Vd),
5550 (and DPR:$Vm, (vnotd DPR:$Vd)))),
5551 (VBSPd DPR:$Vd, DPR:$Vn, DPR:$Vm)>;
5552 def : Pat<(v4i16 (or (and DPR:$Vn, DPR:$Vd),
5553 (and DPR:$Vm, (vnotd DPR:$Vd)))),
5554 (VBSPd DPR:$Vd, DPR:$Vn, DPR:$Vm)>;
5555 def : Pat<(v2i32 (or (and DPR:$Vn, DPR:$Vd),
5556 (and DPR:$Vm, (vnotd DPR:$Vd)))),
5557 (VBSPd DPR:$Vd, DPR:$Vn, DPR:$Vm)>;
5558 def : Pat<(v1i64 (or (and DPR:$Vn, DPR:$Vd),
5559 (and DPR:$Vm, (vnotd DPR:$Vd)))),
5560 (VBSPd DPR:$Vd, DPR:$Vn, DPR:$Vm)>;
5564 : PseudoNeonI<(outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
5566 [(set QPR:$Vd,
5585 def : Pat<(v16i8 (or (and QPR:$Vn, QPR:$Vd),
5586 (and QPR:$Vm, (vnotq QPR:$Vd)))),
5587 (VBSPq QPR:$Vd, QPR:$Vn, QPR:$Vm)>;
5588 def : Pat<(v8i16 (or (and QPR:$Vn, QPR:$Vd),
5589 (and QPR:$Vm, (vnotq QPR:$Vd)))),
5590 (VBSPq QPR:$Vd, QPR:$Vn, QPR:$Vm)>;
5591 def : Pat<(v4i32 (or (and QPR:$Vn, QPR:$Vd),
5592 (and QPR:$Vm, (vnotq QPR:$Vd)))),
5593 (VBSPq QPR:$Vd, QPR:$Vn, QPR:$Vm)>;
5594 def : Pat<(v2i64 (or (and QPR:$Vn, QPR:$Vd),
5595 (and QPR:$Vm, (vnotq QPR:$Vd)))),
5596 (VBSPq QPR:$Vd, QPR:$Vn, QPR:$Vm)>;
5600 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
5603 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
5606 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
5609 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
5615 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
5617 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
5620 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
5622 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
5628 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
5630 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
5633 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
5635 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
6137 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$Vd), (ins DPR:$Vm),
6138 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
6139 [(set DPR:$Vd, (Ty (vnegd DPR:$Vm)))]>;
6141 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$Vd), (ins QPR:$Vm),
6142 IIC_VSHLiQ, OpcodeStr, Dt, "$Vd, $Vm", "",
6143 [(set QPR:$Vd, (Ty (vnegq QPR:$Vm)))]>;
6155 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VUNAD,
6156 "vneg", "f32", "$Vd, $Vm", "",
6157 [(set DPR:$Vd, (v2f32 (fneg DPR:$Vm)))]>;
6159 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VUNAQ,
6160 "vneg", "f32", "$Vd, $Vm", "",
6161 [(set QPR:$Vd, (v4f32 (fneg QPR:$Vm)))]>;
6163 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VUNAD,
6164 "vneg", "f16", "$Vd, $Vm", "",
6165 [(set DPR:$Vd, (v4f16 (fneg DPR:$Vm)))]>,
6168 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VUNAQ,
6169 "vneg", "f16", "$Vd, $Vm", "",
6170 [(set QPR:$Vd, (v8f16 (fneg QPR:$Vm)))]>,
6207 (outs DPR:$Vd, DPR:$Vm), (ins DPR:$in1, DPR:$in2),
6208 NoItinerary, "vswp", "$Vd, $Vm", "$in1 = $Vd, $in2 = $Vm",
6211 (outs QPR:$Vd, QPR:$Vm), (ins QPR:$in1, QPR:$in2),
6212 NoItinerary, "vswp", "$Vd, $Vm", "$in1 = $Vd, $in2 = $Vm",
6218 def : NEONInstAlias<"vmov${p} $Vd, $Vm",
6219 (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
6220 def : NEONInstAlias<"vmov${p} $Vd, $Vm",
6221 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
6229 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$Vd),
6231 "vmov", "i8", "$Vd, $SIMM", "",
6232 [(set DPR:$Vd, (v8i8 (ARMvmovImm timm:$SIMM)))]>;
6233 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$Vd),
6235 "vmov", "i8", "$Vd, $SIMM", "",
6236 [(set QPR:$Vd, (v16i8 (ARMvmovImm timm:$SIMM)))]>;
6238 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$Vd),
6240 "vmov", "i16", "$Vd, $SIMM", "",
6241 [(set DPR:$Vd, (v4i16 (ARMvmovImm timm:$SIMM)))]> {
6245 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$Vd),
6247 "vmov", "i16", "$Vd, $SIMM", "",
6248 [(set QPR:$Vd, (v8i16 (ARMvmovImm timm:$SIMM)))]> {
6252 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$Vd),
6254 "vmov", "i32", "$Vd, $SIMM", "",
6255 [(set DPR:$Vd, (v2i32 (ARMvmovImm timm:$SIMM)))]> {
6259 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$Vd),
6261 "vmov", "i32", "$Vd, $SIMM", "",
6262 [(set QPR:$Vd, (v4i32 (ARMvmovImm timm:$SIMM)))]> {
6266 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$Vd),
6268 "vmov", "i64", "$Vd, $SIMM", "",
6269 [(set DPR:$Vd, (v1i64 (ARMvmovImm timm:$SIMM)))]>;
6270 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$Vd),
6272 "vmov", "i64", "$Vd, $SIMM", "",
6273 [(set QPR:$Vd, (v2i64 (ARMvmovImm timm:$SIMM)))]>;
6275 def VMOVv2f32 : N1ModImm<1, 0b000, 0b1111, 0, 0, 0, 1, (outs DPR:$Vd),
6277 "vmov", "f32", "$Vd, $SIMM", "",
6278 [(set DPR:$Vd, (v2f32 (ARMvmovFPImm timm:$SIMM)))]>;
6279 def VMOVv4f32 : N1ModImm<1, 0b000, 0b1111, 0, 1, 0, 1, (outs QPR:$Vd),
6281 "vmov", "f32", "$Vd, $SIMM", "",
6282 [(set QPR:$Vd, (v4f32 (ARMvmovFPImm timm:$SIMM)))]>;
6294 def : NEONInstAlias<"vmov${p}.i" # To.Size # " $Vd, $Vm",
6295 (VMOVv8i8 DPR:$Vd, nImmVMOVIReplicate<i8, To>:$Vm, pred:$p)>;
6296 def : NEONInstAlias<"vmov${p}.i" # To.Size # " $Vd, $Vm",
6297 (VMOVv16i8 QPR:$Vd, nImmVMOVIReplicate<i8, To>:$Vm, pred:$p)>;
6302 def : NEONInstAlias<"vmvn${p}.i" # To.Size # " $Vd, $Vm",
6303 (VMOVv8i8 DPR:$Vd, nImmVINVIReplicate<i8, To>:$Vm, pred:$p)>;
6304 def : NEONInstAlias<"vmvn${p}.i" # To.Size # " $Vd, $Vm",
6305 (VMOVv16i8 QPR:$Vd, nImmVINVIReplicate<i8, To>:$Vm, pred:$p)>;
6318 def : NEONInstAlias<"vmov${p}.i" # To.Size # " $Vd, $Vm",
6319 (V8 DPR:$Vd, nImmVMOVIReplicate<From, To>:$Vm, pred:$p)>;
6320 def : NEONInstAlias<"vmov${p}.i" # To.Size # " $Vd, $Vm",
6321 (V16 QPR:$Vd, nImmVMOVIReplicate<From, To>:$Vm, pred:$p)>;
6322 def : NEONInstAlias<"vmvn${p}.i" # To.Size # " $Vd, $Vm",
6323 (NV8 DPR:$Vd, nImmVMOVIReplicate<From, To>:$Vm, pred:$p)>;
6324 def : NEONInstAlias<"vmvn${p}.i" # To.Size # " $Vd, $Vm",
6325 (NV16 QPR:$Vd, nImmVMOVIReplicate<From, To>:$Vm, pred:$p)>;
6347 def VMOVD0 : ARMPseudoExpand<(outs DPR:$Vd), (ins), 4, IIC_VMOVImm,
6348 [(set DPR:$Vd, (v2i32 ARMimmAllZerosD))],
6349 (VMOVv2i32 DPR:$Vd, 0, (ops 14, zero_reg))>,
6351 def VMOVQ0 : ARMPseudoExpand<(outs QPR:$Vd), (ins), 4, IIC_VMOVImm,
6352 [(set QPR:$Vd, (v4i32 ARMimmAllZerosV))],
6353 (VMOVv4i32 QPR:$Vd, 0, (ops 14, zero_reg))>,
6668 : NVDupLane<op19_16, 0, (outs DPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
6669 IIC_VMOVD, OpcodeStr, Dt, "$Vd, $Vm$lane",
6670 [(set DPR:$Vd, (Ty (ARMvduplane (Ty DPR:$Vm), imm:$lane)))]>;
6674 : NVDupLane<op19_16, 1, (outs QPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
6675 IIC_VMOVQ, OpcodeStr, Dt, "$Vd, $Vm$lane",
6676 [(set QPR:$Vd, (ResTy (ARMvduplane (OpTy DPR:$Vm),
6965 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$Vd),
6967 OpcodeStr, Dt, "$Vd, $Vm", "",
6968 [(set DPR:$Vd, (Ty (ARMvrev64 (Ty DPR:$Vm))))]>;
6970 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$Vd),
6972 OpcodeStr, Dt, "$Vd, $Vm", "",
6973 [(set QPR:$Vd, (Ty (ARMvrev64 (Ty QPR:$Vm))))]>;
7002 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$Vd),
7004 OpcodeStr, Dt, "$Vd, $Vm", "",
7005 [(set DPR:$Vd, (Ty (ARMvrev32 (Ty DPR:$Vm))))]>;
7007 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$Vd),
7009 OpcodeStr, Dt, "$Vd, $Vm", "",
7010 [(set QPR:$Vd, (Ty (ARMvrev32 (Ty QPR:$Vm))))]>;
7032 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$Vd),
7034 OpcodeStr, Dt, "$Vd, $Vm", "",
7035 [(set DPR:$Vd, (Ty (ARMvrev16 (Ty DPR:$Vm))))]>;
7037 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$Vd),
7039 OpcodeStr, Dt, "$Vd, $Vm", "",
7040 [(set QPR:$Vd, (Ty (ARMvrev16 (Ty QPR:$Vm))))]>;
7066 let TwoOperandAliasConstraint = "$Vn = $Vd" in {
7068 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$Vd),
7070 IIC_VEXTD, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
7071 [(set DPR:$Vd, (Ty (NEONvext (Ty DPR:$Vn),
7079 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$Vd),
7081 IIC_VEXTQ, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
7082 [(set QPR:$Vd, (Ty (NEONvext (Ty QPR:$Vn),
7178 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$Vd),
7180 "vtbl", "8", "$Vd, $Vn, $Vm", "",
7181 [(set DPR:$Vd, (v8i8 (NEONvtbl1 VecListOneD:$Vn, DPR:$Vm)))]>;
7185 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$Vd),
7187 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
7189 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$Vd),
7191 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
7193 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$Vd),
7196 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
7206 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$Vd),
7208 "vtbx", "8", "$Vd, $Vn, $Vm", "$orig = $Vd",
7209 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbx1
7213 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$Vd),
7215 "vtbx", "8", "$Vd, $Vn, $Vm", "$orig = $Vd", []>;
7217 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$Vd),
7220 "vtbx", "8", "$Vd, $Vn, $Vm",
7221 "$orig = $Vd", []>;
7223 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$Vd),
7225 "vtbx", "8", "$Vd, $Vn, $Vm",
7226 "$orig = $Vd", []>;
8118 defm : NEONDTAnyInstAlias<"vand${p}", "$Vd, $Vn, $Vm",
8119 (VANDd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
8120 defm : NEONDTAnyInstAlias<"vand${p}", "$Vd, $Vn, $Vm",
8121 (VANDq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
8122 defm : NEONDTAnyInstAlias<"vbic${p}", "$Vd, $Vn, $Vm",
8123 (VBICd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
8124 defm : NEONDTAnyInstAlias<"vbic${p}", "$Vd, $Vn, $Vm",
8125 (VBICq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
8126 defm : NEONDTAnyInstAlias<"veor${p}", "$Vd, $Vn, $Vm",
8127 (VEORd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
8128 defm : NEONDTAnyInstAlias<"veor${p}", "$Vd, $Vn, $Vm",
8129 (VEORq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
8130 defm : NEONDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm",
8131 (VORRd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
8132 defm : NEONDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm",
8133 (VORRq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
8148 def : NEONInstAlias<"vand${p}.i16 $Vd, $imm",
8149 (VBICiv4i16 DPR:$Vd, nImmSplatNotI16:$imm, pred:$p)>;
8150 def : NEONInstAlias<"vand${p}.i32 $Vd, $imm",
8151 (VBICiv2i32 DPR:$Vd, nImmSplatNotI32:$imm, pred:$p)>;
8152 def : NEONInstAlias<"vand${p}.i16 $Vd, $imm",
8153 (VBICiv8i16 QPR:$Vd, nImmSplatNotI16:$imm, pred:$p)>;
8154 def : NEONInstAlias<"vand${p}.i32 $Vd, $imm",
8155 (VBICiv4i32 QPR:$Vd, nImmSplatNotI32:$imm, pred:$p)>;
8994 defm : NEONDTAnyInstAlias<"vmov${p}", "$Vd, $Vm",
8995 (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
8996 defm : NEONDTAnyInstAlias<"vmov${p}", "$Vd, $Vm",
8997 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
8999 defm : NEONDTAnyInstAlias<"vmvn${p}", "$Vd, $Vm",
9000 (VMVNd DPR:$Vd, DPR:$Vm, pred:$p)>;
9001 defm : NEONDTAnyInstAlias<"vmvn${p}", "$Vd, $Vm",
9002 (VMVNq QPR:$Vd, QPR:$Vm, pred:$p)>;
9081 defm : NEONDTAnyInstAlias<"vswp${p}", "$Vd, $Vm",
9082 (VSWPd DPR:$Vd, DPR:$Vm, pred:$p)>;
9083 defm : NEONDTAnyInstAlias<"vswp${p}", "$Vd, $Vm",
9084 (VSWPq QPR:$Vd, QPR:$Vm, pred:$p)>;
9087 defm : NEONDTAnyInstAlias<"vbif${p}", "$Vd, $Vn, $Vm",
9088 (VBIFd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
9089 defm : NEONDTAnyInstAlias<"vbit${p}", "$Vd, $Vn, $Vm",
9090 (VBITd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
9091 defm : NEONDTAnyInstAlias<"vbsl${p}", "$Vd, $Vn, $Vm",
9092 (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
9093 defm : NEONDTAnyInstAlias<"vbif${p}", "$Vd, $Vn, $Vm",
9094 (VBIFq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
9095 defm : NEONDTAnyInstAlias<"vbit${p}", "$Vd, $Vn, $Vm",
9096 (VBITq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
9097 defm : NEONDTAnyInstAlias<"vbsl${p}", "$Vd, $Vn, $Vm",
9098 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
9101 def : NEONInstAlias<"vmov${p}.i32 $Vd, $imm",
9102 (VMVNv2i32 DPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
9103 def : NEONInstAlias<"vmov${p}.i32 $Vd, $imm",
9104 (VMVNv4i32 QPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
9105 def : NEONInstAlias<"vmvn${p}.i32 $Vd, $imm",
9106 (VMOVv2i32 DPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
9107 def : NEONInstAlias<"vmvn${p}.i32 $Vd, $imm",
9108 (VMOVv4i32 QPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
9154 def : NEONInstAlias<"vmov${p}.f32 $Vd, $imm",
9155 (VMOVv4i32 QPR:$Vd, nImmVMOVI32:$imm, pred:$p)>;
9156 def : NEONInstAlias<"vmov${p}.f32 $Vd, $imm",
9157 (VMOVv2i32 DPR:$Vd, nImmVMOVI32:$imm, pred:$p)>;
9171 (ins RegTy:$Vd, RegTy:$Vn, RegTy:$Vm),
9173 (int_arm_neon_bfdot (AccumTy RegTy:$Vd),
9176 let Constraints = "$dst = $Vd";
9177 let AsmString = !strconcat(opc, ".bf16", "\t$Vd, $Vn, $Vm");
9185 (ins RegTy:$Vd, RegTy:$Vn,
9189 let Constraints = "$dst = $Vd";
9190 let AsmString = !strconcat(opc, ".bf16", "\t$Vd, $Vn, $Vm$lane");
9195 (AccumTy (int_arm_neon_bfdot (AccumTy RegTy:$Vd),
9200 (!cast<Instruction>(NAME) RegTy:$Vd, RegTy:$Vn, RHS, VectorIndex32:$lane)>;
9212 (outs RegTy:$dst), (ins RegTy:$Vd, RegTy:$Vn, RegTy:$Vm),
9214 [(set (v4f32 QPR:$dst), (int_arm_neon_bfmmla (v4f32 QPR:$Vd),
9217 let Constraints = "$dst = $Vd";
9218 let AsmString = !strconcat(opc, ".bf16", "\t$Vd, $Vn, $Vm");
9226 (outs QPR:$dst), (ins QPR:$Vd, QPR:$Vn, QPR:$Vm),
9227 NoItinerary, "vfma" # suffix, "bf16", "$Vd, $Vn, $Vm", "",
9229 (OpNode (v4f32 QPR:$Vd),
9232 let Constraints = "$dst = $Vd";
9241 (ins QPR:$Vd, QPR:$Vn, DPR_8:$Vm, VectorIndex16:$idx),
9242 IIC_VMACD, "vfma" # suffix, "bf16", "$Vd, $Vn, $Vm$idx", "", []> {
9246 let Constraints = "$dst = $Vd";
9251 (v4f32 (OpNode (v4f32 QPR:$Vd),
9255 (!cast<Instruction>(NAME) QPR:$Vd,
9266 (outs DPR:$Vd), (ins QPR:$Vm),
9267 NoItinerary, "vcvt", "bf16.f32", "$Vd, $Vm", "", []>;